Дисертації з теми "Adaptive Phase Lock Loop"
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Myers, Michael D. "THE DEVELOPMENT OF A NONLINEAR PHASE-LOCK LOOP WITH ADAPTIVE GAIN CONTROL BASED ON MODERN CONTROL THEORY." Wright State University / OhioLINK, 2008. http://rave.ohiolink.edu/etdc/view?acc_num=wright1204823575.
Повний текст джерелаUGAZIO, SABRINA. "High-performance velocity, frequency and time estimation using GNSS." Doctoral thesis, Politecnico di Torino, 2013. http://hdl.handle.net/11583/2513765.
Повний текст джерелаHussain, Zahir M. "Adaptive instantaneous frequency estimation: Techniques and algorithms." Thesis, Queensland University of Technology, 2002. https://eprints.qut.edu.au/36137/7/36137_Digitised%20Thesis.pdf.
Повний текст джерелаMartin, Daniel. "Analysis and Design of Phase Lock Loop Based Islanding Detection Methods." Thesis, Virginia Tech, 2011. http://hdl.handle.net/10919/32967.
Повний текст джерелаMaster of Science
Johannes, Michael T. "A fixed-point phase lock loop in a software defined radio." Thesis, Monterey, Calif. : Springfield, Va. : Naval Postgraduate School ; Available from National Technical Information Service, 2002. http://library.nps.navy.mil/uhtbin/hyperion-image/02sep%5FJohannes.pdf.
Повний текст джерелаHardwicke, K. R. "A SELF TUNING PHASE-LOCKED LOOP." International Foundation for Telemetering, 1992. http://hdl.handle.net/10150/608941.
Повний текст джерелаThe uncertainty in the gain of voltage controlled crystal oscillators (VCXOs) used in the implementation of certain analog phase-locked loops (PLLs) suggests some form of automatic tuning algorithm, both for pretuning and during operation. This paper proposes an adaptive PLL (APLL) algorithm to fill this need for PLLs used in the recovery of tones in noise. This algorithm makes use of a resonant error algorithm to remove the effects of VCXO noise, measurement noise, and parasitic poles. Both classical convergence theorems and robustness theorems that indicate the functionality of the proposed algorithm are given. Finally, the implementation of this algorithm is considered.
Kokel, Samuel John. "Retrodirective phase-lock loop controlled phased array antenna for a solar power satellite system." Texas A&M University, 2004. http://hdl.handle.net/1969.1/3047.
Повний текст джерелаBishop, Andrew J. "An adaptive phase-locked loop for a video CODEC /." Thesis, McGill University, 1992. http://digitool.Library.McGill.CA:80/R/?func=dbin-jump-full&object_id=69584.
Повний текст джерелаTang, Yiwu. "Adaptive phase locked loop in multi-standard frequency synthesizers /." The Ohio State University, 2001. http://rave.ohiolink.edu/etdc/view?acc_num=osu1486401895208464.
Повний текст джерелаRideout, Howard. "A true-time delay beamforming system incorporating a wavelength tunable optical phase-lock loop." Thesis, University of Ottawa (Canada), 2007. http://hdl.handle.net/10393/27550.
Повний текст джерелаPark, Joohwan. "Fractional-N PLL with 90 degree phase shift lock and active switched-capacitor loop filter." Diss., Texas A&M University, 2005. http://hdl.handle.net/1969.1/4194.
Повний текст джерелаMelester, M. T., and M. S. Geoghegan. "An Intelligent Digital Phase-Locked Loop with Integral Gain Control, Signal Quality and Lock Detection." International Foundation for Telemetering, 1988. http://hdl.handle.net/10150/615089.
Повний текст джерелаAn intelligent digital phase-locked loop with integral automatic gain control, signal quality and lock detection suitable for implementation using current digital signal processing devices is presented. By exploiting information derived from these functions operating in unison, it is possible to realize improved performance in an adverse environment where fading or abrupt signal outages are encountered. The system described consists of several functions operating under the direction of a stored program. The state diagram model of the program is discussed along with design considerations for the system elements. Various aspects of the system are simulated in the presence of noise and signal outage and compared to the performance of a conventional phase-locked loop.
Lei, Feiran. "Injection Locked Synchronous Oscillators (SOs) and Reference Injected Phase-Locke Loops (PLL-RIs)." The Ohio State University, 2017. http://rave.ohiolink.edu/etdc/view?acc_num=osu1492789278258943.
Повний текст джерелаShen, Baike 1972. "Slip frequency phase lock loop (PLL) for decoupled P-Q control of doubly-fed induction generator (DFIG)." Thesis, McGill University, 2004. http://digitool.Library.McGill.CA:80/R/?func=dbin-jump-full&object_id=81568.
Повний текст джерелаThe accuracy of the Slip Frequency Phase Lock Loop in speed estimation is evaluated; the origin of a shortcoming (small phase lag) located and compensated for.
The Slip Frequency Phase Lock Loop (PLL) and a gamma-delta Axes Aligner are then evaluated as parts of the decoupled P-Q control of a wind turbine driven doubly-ed induction generator. The research succeeds in realizing robust decoupled P-Q control, that is one in which the generator parameters do not have to be known precisely and can have minor variations such as drifts with temperature. The system has been successfully tested for optimal wind power acquisition.
Fábik, Peter. "Zesilovač s fázovým závěsem." Master's thesis, Vysoké učení technické v Brně. Fakulta elektrotechniky a komunikačních technologií, 2013. http://www.nusl.cz/ntk/nusl-219941.
Повний текст джерелаJiang, Bo. "A Wide Band Adaptive All Digital Phase Locked Loop With Self Jitter Measurement And Calibration." ScholarWorks @ UVM, 2016. http://scholarworks.uvm.edu/graddis/562.
Повний текст джерелаHejlek, Pavel. "Návrh smyčky fázového závěsu." Master's thesis, Vysoké učení technické v Brně. Fakulta elektrotechniky a komunikačních technologií, 2013. http://www.nusl.cz/ntk/nusl-220085.
Повний текст джерелаAraÃjo, Renato Guerreiro. "PLL (Phase-Locked Loop) structures for single phase and three phase systems with a high rejection capacity to sub and interharmonic." Universidade Federal do CearÃ, 2015. http://www.teses.ufc.br/tde_busca/arquivo.php?codArquivo=15882.
Повний текст джерелаIn applications related to power converters, such as inverters, rectifiers and the use of active filters, the synchronization method represent a very important element in the performance of the control strategy of this equipment. The estimated values of the synchronism angle, frequency and amplitude determined by the synchronization algorithms present, facing strongly distorted signals with the presence of sub and interharmonics, high errors. This study presents two algorithms: one applied on single-phase electrical systems and one applied on three-phase electrical systems, with high immunity to interharmonics and subharmonics. First are presented the main synchronization systems that are used in the electrical power systems. In addition, will be presented the main causes and consequences of the presence of subharmonics and interharmnics in the system, as well as the mathematical modeling of the two algorithms with high rejection to these disturbances. Will be presented the simulation and the experimental results of the proposed algorithms and the comparison between these synchronization methods with particular methods present in the literature. As a result of the study, it can be seen that the proposed structures present a higher response time, but the error of the estimated signal with respect the fundamental component of the input signal is lower when compared to structures such as EPLL and structures based on SOGI. It was observed that the proposed synchronization methods are enabled to estimate the synchronism angle, the frequency and the fundamental component of the input signal adequately and can be used in control strategies of power converters.
Em aplicaÃÃes relacionadas à EletrÃnica de PotÃncia, como inversores, retificadores e a utilizaÃÃo de filtros ativos, o mÃtodo de sincronizaÃÃo representa um elemento chave no desempenho da estratÃgia de controle destes equipamentos. Os valores do Ãngulo de sincronismo, frequÃncia e amplitude estimados com determinados algoritmos de sincronizaÃÃo apresentam, diante de sinais fortemente distorcidos com a presenÃa de sub e inter-harmÃnicos, erros elevados. Neste trabalho sÃo apresentados dois algoritmos: um aplicado a sistemas elÃtricos monofÃsicos e outro aplicado a sistemas elÃtricos trifÃsicos, com elevada imunidade a inter-harmÃnicos e sub-harmÃnicos. Primeiramente sÃo apresentados os principais sistemas de sincronizaÃÃo utilizados em sistemas elÃtricos de potÃncia. AlÃm disso, sÃo apresentadas as principais causas e consequÃncias da presenÃa de sub-harmÃnicos e inter-harmÃnicos no sistema, bem como a modelagem matemÃtica dos dois algoritmos com elevada rejeiÃÃo a estes distÃrbios. SÃo apresentados os resultados de simulaÃÃo e experimentais dos algoritmos propostos e a comparaÃÃo entre estes mÃtodos de sincronizaÃÃo com determinados mÃtodos presentes na literatura. Como resultado do estudo, pode-se observar que as estruturas de sincronizaÃÃo propostas apresentam um tempo de resposta mais elevado, porÃm o erro do sinal estimado em relaÃÃo a componente fundamental do sinal de entrada à inferior quando comparado a estruturas como o EPLL e estruturas baseadas no SOGI. Com isso, tem-se que as mesmas estÃo habilitadas para estimar o Ãngulo de sincronismo, a frequÃncia e a componente fundamental do sinal de entrada adequadamente e podem serem utilizadas eficientemente em estratÃgias de controle de conversores de potÃncia.
Rejnuš, Milan. "Měřicí zesilovač využívající vektorové synchronní detekce." Master's thesis, Vysoké učení technické v Brně. Fakulta elektrotechniky a komunikačních technologií, 2014. http://www.nusl.cz/ntk/nusl-221146.
Повний текст джерелаPoslušný, Marek. "Vícepásmový mikrovlnný vysílač pro studium šíření elektromagnetických vln v atmosféře." Master's thesis, Vysoké učení technické v Brně. Fakulta elektrotechniky a komunikačních technologií, 2013. http://www.nusl.cz/ntk/nusl-219945.
Повний текст джерелаČada, David. "Spektrální analyzátor do 500 MHz." Master's thesis, Vysoké učení technické v Brně. Fakulta elektrotechniky a komunikačních technologií, 2015. http://www.nusl.cz/ntk/nusl-221242.
Повний текст джерелаHordeski, Theodore J. "Digital FSK/AM/PM Sub-Carrier Modulator on a 6U-VME-Card." International Foundation for Telemetering, 1996. http://hdl.handle.net/10150/611475.
Повний текст джерелаAerospace Report No. TOR-0059(6110-01)-3, section 1.3.3 outlines the design and performance requirements of SGLS (Space Ground Link Subsystem) uplink services equipment. This modulation system finds application in the U.S. Air Force satellite uplink commanding system. The SGLS signal generator is specified as an FSK (Frequency Shift Keyed)/AM (Amplitude Modulation)/PM (Phase Modulation) sub-carrier modulator. GDP Space Systems has implemented, on a single 6U-VME card, a SGLS signal generator. The modulator accepts data from several possible sources and uses the data to key one of three FSK tone frequencies. This ternary FSK signal is amplitude modulated by a synchronized triangle wave running at one half the data rate. The FSK/AM signal is then used to phase modulate a tunable HF (High-Frequency) sub-carrier. A digital design approach and the availability of integrated circuits with a high level of functionality enabled the realization of a SGLS signal generator on a single VME card. An analog implementation would have required up to three rack-mounted units to generate the same signal. The digital design improve performance, economy and reliability over analog approaches. This paper describes the advantages of a digital FSK/AM/PM modulation method, as well as DDS (Direct Digital Synthesis) and digital phase-lock techniques.
Jung, Seok Min, and Seok Min Jung. "Design and Implementation of Low Jitter Clock Generators in Communication and Aerospace System." Diss., The University of Arizona, 2016. http://hdl.handle.net/10150/621292.
Повний текст джерелаSvoboda, Josef. "Přímý číslicový frekvenční syntezátor." Master's thesis, Vysoké učení technické v Brně. Fakulta elektrotechniky a komunikačních technologií, 2009. http://www.nusl.cz/ntk/nusl-217986.
Повний текст джерелаUmansky, Alec. "HIGH BANDWIDTH PORTABLE TRANSMISSION SYSTEMS USE OF xDSL TECHNOLOGY IN MILITARY, INDUSTRIAL AND TELEMETRIC APPLICATIONS." International Foundation for Telemetering, 2001. http://hdl.handle.net/10150/606418.
Повний текст джерелаThis paper introduces new telemetry (communications) equipment based on Digital Subscriber Loop DSL technology (high speed transmission over copper cables) for defense and industrial applications. A brief xDSL technology overview is followed with introduction of the new ‘P3’ product and its application, reviewing advantages of using copper as a communications medium whenever rapidly deployed data and voice links are essential. An Australian Army report, detailing a specific equipment deployment’s findings is reproduced as an independent reference material.
Umansky, Alec. "HIGH BANDWIDTH PORTABLE TRANSMISSION SYSTEMS USE OF xDSL TECHNOLOGY IN MILITARY AND INDUSTRIAL TELEMETRIC APPLICATIONS." International Foundation for Telemetering, 2000. http://hdl.handle.net/10150/606792.
Повний текст джерелаThis paper introduces new telemetry equipment based on Digital Subscriber Loop DSL technology (high speed transmission over copper cables) for military and industrial applications. A brief xDSL technology overview is followed with introduction of the new ‘P3’ product. A number of new applications for remote data transmission are presented and further highlighted in the Australian Army report detailing their recent equipment operational deployments.
Sagha, Hossein. "Development of innovative robust stability enhancement algorithms for distribution systems containing distributed generators." Thesis, Queensland University of Technology, 2015. https://eprints.qut.edu.au/91052/1/Hossein_Sagha_Thesis.pdf.
Повний текст джерелаAl, Ghossini Hossam. "Contributions to the study of control for small-scale wind turbine connected to electrical microgrid with and without sensor." Thesis, Compiègne, 2016. http://www.theses.fr/2016COMP2310/document.
Повний текст джерелаThe aim of this thesis is to propose the most appropriate approach in order to minimize the cost of integration of a wind generator into a DC urban microgrid. A small-scale wind generator based on a permanent magnet synchronous machine (PMSM) is considered to be studied. A state of the art concerning the renewable energies, DC microgrid, and wind power generation is done. As the mechanical sensor for this structure is relatively of high cost, various types of wind conversion system control are presented in order to choose an energy conversion active structure and a sensorless PMSM. Therefore, a speed/position estimator is required to control the system. Thus, different methods proposed in literatures are considered and classified to be studied in details, and then the most effective and widely used ones are to be verified in simulation and experimentally for the studied system. The methods which are chosen are: rotor flux estimation with phase locked loop (PLL), sliding mode observer (SMO), Luenberger observer of reduced order, and extended Kalman filter (EKF). Facing to other methods, the EKF model-based estimator allows sensorless drive control in a wide speed range and estimates the rotation speed with a rapid response. The EKF parameters tuning is the main problem to its implementation. Hence, to solve this problem, the thesis introduces an adaptive method, i.e. adaptive-tuning EKF. As a result and grace to this approach, the total cost of conversion system is reduced and the performance is guaranteed and optimized
Lien, Chien Yung, and 簡永烈. "Design of Blind Adaptive Beamformer Combined with Phase Lock Loop." Thesis, 2000. http://ndltd.ncl.edu.tw/handle/99394479721570467553.
Повний текст джерела國立海洋大學
電機工程學系
88
The conventional Frost beamformer is incapable of exacting desired signal in the multipath propagation environment. It is very sensitive to the position error among the sensors, and needs prior information about the direction of arrival (DOA) of the desired signal. To overcome the problems mentioned above, we propose a new method that exploits the cyclostationary property of communication signals, in the design of blind adaptive beamformer. The proposed beamformer uses the LMS algorithm to minimize the mean square error between the transformed array output signal and a complex exponential signal. In the case where DQPSK is the desired signal, the complex exponential signal, representing a spectral line at the carrier frequency of the DQPSK signal, is extracted from the transformed array output as a reference signal by the use of phase lock loop. To evaluate the performance of the proposed beamformer, computer simulations for the cases of Gaussian white noise, multiple interferences, and multipath propagation were carried out. Simulation results show that the proposed beamformer is rather effective to increase signal-to-noise ratio, cancel interferences, and remove intersymbol interference.
LUO, ZHI-TONG, and 羅治同. "An adaptive digital phase lock loop under sinusoidal interference conditions." Thesis, 1990. http://ndltd.ncl.edu.tw/handle/75058131604016916819.
Повний текст джерелаChen, Yan Hao, and 陳彥豪. "1.09375GHz Delta Sigma Phase Lock Loop." Thesis, 2015. http://ndltd.ncl.edu.tw/handle/5x857m.
Повний текст джерела國立清華大學
電機工程學系
103
There are two part in this paper. The first part in this paper is a discussion about delta sigma modulation phase lock loop circuit design and the second part in this pa- per is appendix about linear control oscillator circuit design . In delta sigma phase lock loop circuit design , the pur- pose and specific are described and overview of integer, fractional delta sigma phase lock loop . Final part of delta sigma phase lock loop is design and simulation. In linear control oscillator circuit design , the motive of design linear voltage control is described and intro- duce some knowledge about ring oscillator .Then , some linear voltage control oscillator introduction are pre- sent . Final part of linear control oscill- ator is design and simulation .
Chiang, Yu-Chen, and 江宇晟. "Jitter Performance Study For Phase-Lock Loop." Thesis, 2005. http://ndltd.ncl.edu.tw/handle/70476321354403064487.
Повний текст джерела國立清華大學
電機工程學系
93
In many circuits, PLL must provide an output clock to follow the input clock closely. Examples of applications that use PLL include clock and data recovery, clock synthesis, and synchronization, frequency synthesis and PLL modulator or de-modulator application. As environment clock speed rise up, the jitter performance for PLL is more and more important. The jitter source of PLL comes from many no ideal effect of PLL, such as power supply noise, substrate noise, VCO noise, and charge pump current mismatch. This thesis proposes the prediction method of jitter performance, for estimate the output jitter comes from each noise source. Initially, Hspice and Spectre are used to estimate the output phase noise of each noise source in coordinate with phase-noise-to-jitter transfer function and noise transfer function (NTF) to estimate the PLL output jitter. This thesis primary considered the noise created by phase-locked loop. Include thermal analysis and the phase noise created by each block in PLL. Thermal Analysis: This part primarily analysis the phase noise created by each block in PLL. Then use the phase noise to jitter equation to estimate the PLL output jitter. PLL Each Block Phase Noise: This park primarily consider VCO phase noise、current mismatch created by PFD/CP and input clock phase noise.
LIN, HONG-REN, and 林鴻任. "2.4-GHz Integer-N Phase-Lock Loop." Thesis, 2019. http://ndltd.ncl.edu.tw/handle/374833.
Повний текст джерела國立臺北科技大學
電子工程系
107
This paper presents a fully-integrated 2.4 GHz phase-locked loop (PLL) on standard 0.18-μm CMOS process. Utilizing the delay cell Ring Oscillator and high speed true single phase clock (TSPC) divider, the 2.4 GHz PLL achieves low power consumption of 9.45 mW. In addition, an inverter type buffer amplifier is incorporated between the VCO and TSPC divider chain to provide full voltage swing for TSPC input. The measured phase noise is −92.6 dBc/Hz at 1 MHz frequency offsets, and Reference Spur is 40.9 dBc, respectively. The output frequency is 2.18−2.91 GHz. The second section uses a multi-modulus frequency divider, and the 2.4 GHz PLL achieves a wide frequency output frequency at the same reference frequency. Using a reference frequency of 37.5 MHz, the multimode divider is controlled to operate 16 states with control voltage and output a frequency range of 2.4 GHz to 2.9625 GHz. The phase noise measured at 1 MHz frequency offset is -92.6 dBc / Hz and the reference glitch is 40.9 dBc.
Pitts, Wallace Shepherd. "Partially depleted silicon on insulator phase lock loop." 2005. http://www.lib.ncsu.edu/theses/available/etd-01042006-202434/unrestricted/etd.pdf.
Повний текст джерелаDzung-Li, Lin, and 林宗立. "Small DC Brushless Motor Phase Lock Loop Control." Thesis, 1994. http://ndltd.ncl.edu.tw/handle/30896957315215746420.
Повний текст джерелаChen, Ming-Jing, and 陳銘金. "5 GHz Phase Lock Loop with Auto Band Selection." Thesis, 2007. http://ndltd.ncl.edu.tw/handle/4m5s5u.
Повний текст джерела國立中山大學
資訊工程學系研究所
95
This thesis presents the CMOS integer-N frequency synthesizer for 5 GHz WCDMA applications with 1.8V power supply. The frequency synthesizer is fabricated in a TSMC 0.18μm CMOS 1P6M technology process. The frequency synthesizer consists of a phase-frequency detector, a charge pump, a low-pass loop filter, a voltage control oscillator, an auto-band selection, and a pulse-swallow divider. In pulse-swallow divider, this thesis use true single phase clock DFF proposed by Yuan and Svensson to work on high frequency region and to save the circuit area and power. This thesis also proposes an auto-band selection circuit to control the output frequency more precise and easier, and it can also reduce the frequency drift effect caused by technology process or temperature variation.
Tsai, Sheng-Chung, and 蔡勝中. "Design and Implementationof an All Digital Phase Lock Loop." Thesis, 2005. http://ndltd.ncl.edu.tw/handle/56679715727627733504.
Повний текст джерела國立臺灣大學
電子工程學研究所
93
ABSTRACT In this Thesis, we have presented the design of an all-digital phase-locked loop (ADPLL), which consists of a digitally controlled oscillator (DCO), a phase frequency detector (PFD), a control unit and some auxiliary logic circuits. A 16-bit digitally controlled CMOS oscillator uses a 4-stage ring of a modified differential delay cell. The DCO uses the even-stage skew dual-delay path scheme [11], which enables higher operating frequency. The frequency search and the phase tracking are major blocks in a control unit. We use a high sensitivity phase tracking and frequency search algorithm, which consists two D-type flip flop and some logical circuits. In our proposed ADPLL, we implement the DCO by full custom design style while the other circuits are implemented by cell-based design style. In order to rapidly evaluate the structures and algorithms, we model the DCO in Verilog construct, and verify the ADPLL system by Verilog simulator. The ADPLL is designed in the TSMC 0.18μm 1P6M technology. The supply voltage is 1.8V. The simulation results show that when DCO operates at 2.4GHz, the phase error is smaller than 100ps. The system dead zone is smaller than 30ps, and the lock in time is smaller than 30 reference clock cycles (algorithm). The lock-in range is 2.07GHz to 2.56GHz. The power consumption is 106.1mW at 2.4GHz.
Sheng-Chung, Tsai. "Design and Implementation of an All Digital Phase Lock Loop." 2005. http://www.cetd.com.tw/ec/thesisdetail.aspx?etdun=U0001-2607200513510400.
Повний текст джерелаLiu, Jen-Chieh, and 劉仁傑. "All Digital Phase Lock Loop Using Signal-Edge-Trigger DCO." Thesis, 2006. http://ndltd.ncl.edu.tw/handle/25730471276305357522.
Повний текст джерела輔仁大學
電子工程學系
94
An all-digital phase locked-loop (ADPLL) is presented to achieve fast lock, high resolution and process immunity. A novel digitally controlled varactor (DCV) is used in fine-tuning delay cell design. The proposed DCO architecture uses Single-Edge-Trigger DCO. Thus, it has the characteristics of, high resolution, flexible operating range, and easy design. The proposed ADPLL uses a novel digitally controlled oscillator (DCO) to achieve 1.6ps resolution and the proposed DCO can extend the controllable range easily. The ADPLL implemented in a 0.18um single-poly six-metal (1P6M) technology can operate from 150 to 450MHz and achieve worst case frequency acquisition in 32 reference clock cycles. The chip size was 850 850 um2 (core: 260 360 um2), and the power consumption was10mW at 400MHz.
Wu, Chia-Tsun, and 吳嘉村. "Portable Fast Locking All-Digital Phase-Lock Loop Circuit Design." Thesis, 2003. http://ndltd.ncl.edu.tw/handle/60872547279439026303.
Повний текст джерела國立臺灣大學
電子工程學研究所
91
PLL circuits become more and more popular in different System on Chip (SOC) applications, since most ICs need precise clocking schemes. An All-Digital Phase-Lock Loop can be easy transferred during process migration. However, most existing ADPLL circuits use in-house cell libraries or full-custom techniques to design ADPLL. In order to guarantee the shortest transfer period during process migration and minimum design efforts. We develop a new architecture that employs standard-cell library to design ADPLL. All cell libraries that are used in ADPLL design are provided from foundry. Also, we develop new tracking algorithm for fast phase and frequency locking. The new algorithms can lock input reference clock with two input cycles in any case. The core area is 0.1 mm2 (0.25um technique).
Chang, Chun-Chiang, and 張俊強. "A phase lock loop circuit design for thermal-actuated resonators." Thesis, 2013. http://ndltd.ncl.edu.tw/handle/56006568999845025894.
Повний текст джерела國立交通大學
機械工程系所
101
This study applied a thermal-actuated resonator by using a piezo-resistive sensor and designed the measurement circuits for micro-resonator. The resonator’s frequency will change when the plane adsorbs the material. To measure the change of resonator’s natural frequency we can know the mass of the material. The resonator was vibrated by the thermal actuator and designed a piezo- resistive sensor in the form of Wheatstone bridge circuits to measure the signal. The phase difference between the resonator input signal and output signal can be locked on -180° by the theory of Phase lock loop. According to the method, we can obtain the natural frequency of resonator. Besides, the resonator’s output signal will generate a Feed through noise. In order to reject the noise the study propose the idea by demodulating the frequency through the circuits of multiplier to reduce the noise. The resonator was a three order dynamic system, and the natural frequency located when the phase was on -180°. The phase cannot be locked by traditional Phase lock loop because the Phase lock loop usually locked the phase difference on 90°. The study used the analog RC filter to make phase delay on reference signal before passing the Phase detector. Making the phase difference between resonator output signal and reference signal on -90°. The phase and natural frequency can be locked. The circuit was simulated by Hspice 0.35um 2PM4 3.3V process, and using the MATLAB&;SIMULINK to make the model of the system. Through the software, we can combine and discuss the system’s performance and data. And then the resonator and measurement circuit can be expected to present.
Yeh, Nan-Liang, and 葉湳良. "Design of Phase Frequency Detector and Enhanced Lock-in for Phase-Locked Loop." Thesis, 2002. http://ndltd.ncl.edu.tw/handle/22819986223927581840.
Повний текст джерела長庚大學
半導體研究所
90
The two main directions of study in this thesis include both the design of phase/frequency detector and the enhanced lock-in for phase-locked loop. We systematically analyze existing phase/frequency detectors from aspects of theoretical analysis and circuit operation. We also propose a phase/frequency detector which has simple structure, no glitch output as well as better phase characteristics. Based on simulation results, the proposed phase/frequency detector shows satisfactory circuit performance with higher operation frequency, low phase jitter and smaller die size. Furthermore, we present a simple enhanced lock-in system for phase-locked loop. The proposed mechanism can reduce the lock-time effectively by using the reference clock signal only. Besides, the whole enhanced lock-in circuit performs its operation in one reference clock cycle.
吳育倫. "Study of Electromagnetic Interference Detection Using Embedded Phase-Lock Loop Microcontrollers." Thesis, 2013. http://ndltd.ncl.edu.tw/handle/22277794409092388371.
Повний текст джерела逢甲大學
電機與通訊工程博士學位學程
102
This thesis has two parts. First part is to design a multi-band bandstop filter and miniaturize the circuit by bending stubs. In chapter 3, a general design methodology of a multi-band bandstop filter with compact and controllable multi stopband response is proposed. Second part presents a combined hardware–software mechanism for the detection of electromagnetic interference of a microcontroller (μC) in daily usage. This detection mechanism is based on the instability of phase-lock loop embedded in the target μC. The statistic results of PLL locked time in normal environment and disturbance environment. We find the statistic results are significantly different in normal and disturbance environment. Therefore, the phenomenon is used to be a foundation to detect EMI. It can detect the presence of EMI with higher sensitivity than polling the hardware status of the μC internal registers and thus provides a better detection margin within the 10 kHz to 1 GHz EMI frequency range. Despite its relative slowness and its resource consumption, it is very robust and can be implemented in virtually application software, and does not require any electromagnetic compatibility test equipment.
LAI, WEI-JIE, and 賴暐傑. "The Circuits Design and Control of Phase Lock Loop On Servo Motor." Thesis, 2016. http://ndltd.ncl.edu.tw/handle/9xr435.
Повний текст джерела明志科技大學
電機工程系碩士班
104
In the promotion of industrial automation, the motor is the driving force of the majority productivities; it depends on the power electronic to enhance the key technology of motor control. To improve the industrial automation, motor control technology and related theories are crucial. Therefore, this study using phase locked loop design servo motor drive, the phase lock loop (PLL) is one of the basic structures of modern electronic technology, and they have been widely used in communication, multimedia and other multiple uses. In this thesis, the design of the servo motor drive is used a speed control method to control servo motor. It is similar to the accuracy invertor for AC motor, and belonging to a part of the servo system, by adopting thing a high precision positioning method. Besides, using a the IC HEF4046B designed by NXP Semiconductors and IGBT PS21965-T designed by Mitsubishi Electric Corporation, to store a set of three groups d2764a EPROM IC inside and a three-phase waveforms of stator currents then to fulfill the design to control the servo motor-system.
Tz-Cheng, Yang. "A 18.5GHz Fully Differential Phase Lock Loop for 40~48GHz UWB System." 2006. http://www.cetd.com.tw/ec/thesisdetail.aspx?etdun=U0001-2707200623454300.
Повний текст джерелаYang, Tz-Cheng, and 楊子承. "A 18.5GHz Fully Differential Phase Lock Loop for 40~48GHz UWB System." Thesis, 2006. http://ndltd.ncl.edu.tw/handle/20782977735775607780.
Повний текст джерела國立臺灣大學
電子工程學研究所
94
With the rapid growing of the wireless communication system, the demands of high precision phase-locked loops (PLLs) increase significantly. Besides, output phase noise of PLLs is very important for local oscillator. It is because that the quality of phase noise would influence bith transmitting and receiving chain seriously. This thesis will aim to implement an 18.5 GHz PLL with improved phase noise for 40~48 GHz UWB system. We will propose two architectures which are a common high speed phase-locked loop and an improved fully differential phase-locked loop. The performance of both architectures will be compared.
Luo, Ming-Chuang, and 羅銘銓. "A 3V, Fast lock-in Phase-locked Loop for High Speed System." Thesis, 1997. http://ndltd.ncl.edu.tw/handle/03909307916994524511.
Повний текст джерела國立清華大學
電機工程學系
85
In this thesis, we propose a 3V, fast lock-in phase-locked loop with wide frequency range for high speed data systems. This PLL, which is used as a frequency synthesizer for clock/data recovery, is realized by a charge-pump PLL. The PLL consists of several components, a phase detector, a charge pump, a voltage- controlled oscillator, a loop filter, and a frequency divider. For fast lock-in, the phase detector is implemented by a phase- frequency detector. Furthermore, path delay is taken into consideration for higher speed operation. By comparing the phase and frequency difference of it''s inputs, the PFD generates four outputs in response to the difference. Then, accompanying the PFD by a charge-pump the four logic values are converted as an analog signal for controlling the voltage-controlled oscillator. The charge pump has the advantage of having current matching property and being as simple as 8 transistors only. Since the PLL is to generate multi-phase outputs, a 5-stafe differential VCO is used to generate 10 outputs. Since being differential, the VCO has better noise rejection.In addition, the VCO has the property of being nearly full-swing and sensitive to controlling voltage variation.The PLL is realized by 0.6 m DPPM CMOS technology. The HSPICE post-layout simulation results justify the feasibility of out proposed PLL.
Nikkhoo, Nasim. "Phase-locked loop with adaptive supply noise cancellation." 2007. http://link.library.utoronto.ca/eir/EIRdetail.cfm?Resources__ID=452844&T=F.
Повний текст джерелаWei, Wang. "Portable All-Digital Phase-Lock Loop Circuit Design With Programmable Pulse Width Control." 2005. http://www.cetd.com.tw/ec/thesisdetail.aspx?etdun=U0001-1307200515550300.
Повний текст джерелаWANG, Yu-Chung, and 王裕忠. "The study of radio frequency voltage control oscillators for phase lock loop system." Thesis, 2005. http://ndltd.ncl.edu.tw/handle/74389854815678946061.
Повний текст джерела國立臺灣科技大學
電子工程系
93
Design of CMOS Voltage-Controlled Oscillator (VCO) will be investigated in this thesis. First, ring oscillator architecture is the complementary nMOS and pMOS cross-coupled pair to enhance the negative conductance with internal resonator. CMOS VCO’s are implemented using TSMC 0.35µm process with 3.3V supply voltage and frequency tuning range 1.7616GHz~2.466GHz. Otherwise, LC tank voltage control oscillator includes LC cross coupled VCO、dual band LC VCO、complementary Colpitts VCO and complementary Colpitts VCO with back gate coupling. The LC tank VCO is implemented using TSMC 0.18µm process with 1.8V supply voltage. The simulation results with Cadence Spectre RF aid the design of these VCO’s.