Добірка наукової літератури з теми "378.096:621.3"

Al3+-doped ZnO nano-powder was prepared by sol-gel process, using tin tetrachloride and titanium tetrachloride as starting materials. The crystallinity and purity of the powder were analyzed by X-ray diffraction spectrometer (XRD). And the size and distribution of Al3+-doped ZnO grains were studied using transmission electron microscope (TEM) and scanning electron microscope (SEM). The results showed that the Al3+ was successfully doped into the crystal lattice of tin oxide and that the electric conductivity of Al3+-doped ZnO sample was improved significantly.

Cryogenic MQL is a kind of green machining technology of the combination of cryogenic air and minimal quantity lubrication (MQL). The aim of this research is to determine if the cryogenic MQL technique in turning with Cutting tool with internal cooling structure gives some advantages in terms of tool life, surface roughness and cutting chip breaking. This paper reports the results obtained from turning tests, at one feed rates (0.12mm/r) and one depth of cut (0.4mm) and different cutting speeds (43m/min, 108m/min, 217m/min), and the results obtained show that using cryogenic MQL had some advantages in terms of tool wear, surface roughness and cutting chip breaking compared to using dry cutting and cryogenic air cutting. And the results obtained show that when cryogenic MQL and cryogenic air cutting were applied to high speed cutting, they had more advantages.

In this paper, the acoustic radiation mode’s amplitudes of laminated composite plates are studied. The layer wise finite element model is imposed to determine velocity distributions of laminated composite plates. Based on the acoustic radiation mode, the effects of the panel orientation angle on the first three orders acoustic radiation mode’s amplitude of the laminated composite plates are then discussed. A twelve-layer laminated plate was used as an example, and the numerical simulations results show that the effects of the panel orientation angle on the acoustic radiation amplitude of the laminated composite plates are significant.

ABSTRACT Objective To evaluate the vital capacity after two chest therapy techniques in patients undergoing abdominal surgical. Methods A prospective randomized study carried out with patients admitted to the Intensive Care Unit after abdominal surgery. We checked vital capacity, muscular strength using the Medical Research Council scale, and functionality with the Functional Independence Measure the first time the patient was breathing spontaneously (D1), and also upon discharge from the Intensive Care Unit (Ddis). Between D1 and Ddis, respiratory therapy was carried out according to the randomized group. Results We included 38 patients, 20 randomized to Positive Intermittent Pressure Group and 18 to Volumetric Incentive Spirometer Group. There was no significant gain related to vital capacity of D1 and Ddis of Positive Intermittent Pressure Group (mean 1,410mL±547.2 versus 1,809mL±692.3; p=0.979), as in the Volumetric Incentive Spirometer Group (1,408.3mL±419.1 versus 1,838.8mL±621.3; p=0.889). We observed a significant improvement in vital capacity in D1 (p<0.001) and Ddis (p<0.001) and in the Functional Independence Measure (p<0.001) after respiratory therapy. The vital capacity improvement was not associated with gain of muscle strength. Conclusion Chest therapy, with positive pressure and volumetric incentive spirometer, was effective in improving vital capacity of patients submitted to abdominal surgery.

The objectives of this work were to characterize fruits and seeds and evaluate seed germination and seedling vigor from fifteen parent plants of Parkia gigantocarpa Ducke. The fresh weight, length, width, and thickness of fruits and seeds were determined. The germination was tested in a sand substrate, with four replications of 25 seeds per treatment (parent plants). The number of days for emergence, emergence percentage, emergence speed index, germination percentage, and seedling dry weight were evaluated. The fruits presented means for fresh weight, length, width, and thickness of 115.0 g; 621.3 mm; 60.8 mm, and 9.8 mm, respectively. The seeds presented means for fresh weight, length, width, and thickness of 1.1 g, 22.8 mm, 11.2 mm, and 7.0 mm, respectively. The emergence was fast and uniform, which occurred from the fifth to the sixth day after seeding, reaching 91% germination for the parent HB9, but not differing from the parents HB2, HB3, and HB6. The seedlings from the parents HB2, HB3, HB6, and HB9 were more vigorous due to their higher dry matter accumulation. The results found showed that, even belonging to the same species, P. gigantocarpa seeds from different parent plants present variability in biometric characteristics of fruits and seeds. The seed collected from different parent plants showed differences in germination capacity and seedling vigor.

Дисертація на здобуття наукового ступеня кандидата педагогічних наук зі спеціальності 13.00.04 – теорія і методика професійної освіти. – Класичний приватний університет. – Запоріжжя, 2011. У дисертації розглянуто питання формування управлінської компетентності у вищому технічному закладі. Уточнено поняття "компетентність", "управлінська компетентність". Визначено основні структурні компоненти управлінської компетентності у майбутніх інженерів електромашинобудівного напряму. Виокремлено комплекс педагогічних умов формування управлінської компетентності. В результаті експериментальної перевірки педагогічних умов встановлено, що впровадження авторської моделі та певних педагогічних умов сприяє формуванню управлінської компетентності випускників електромашинобудівних спеціальностей технічних університетів.
The dissertation on gaining of a candidate’s scientific degree of pedagogical sciences on a speciality 13.00.04 – theory and method of professional education. – Classic Private University. – Zaporozhye, 2011. In the dissertation the issues of formation of the managerial competence in the higher technical establishment are considered. The concept of "competence", "managerial competence" are clarified. The basic structural components of the managerial competence of the future engineers of electromachinebuilding directions are covered. The complex of pedagogical conditions for the managerial competence formation is determined. In the course of the experimental validation of the pedagogical conditions it is established that the introduction of author’s model and certain pedagogical conditions leads to formation of the managerial competence of the graduates of electromachinebuilding specialties of technical universities.

A thorough review of the state of the art will reveal that most VANET applications rely on Public Key Infrastructure (PKI), which uses user certificates managed by a Certification Authority (CA) to handle security. By doing so, they constrain the ad-hoc nature of the VANET imposing a frequent connection to the CA to retrieve the Certificate Revocation List (CRL) and requiring some degree of roadside infrastructure to achieve that connection. Other solutions propose the usage of group signatures where users organize in groups and elect a group manager. The group manager will need to ensure that group members do not misbehave, i.e., do not spread false information, and if they do punish them, evict them from the group and report them to the CA; thus suffering from the same CRL retrieval problem. In this thesis we present a fourfold contribution to improve security in VANETs. First and foremost, Chains of Trust describes a reputation system where users disseminate Points of Interest (POIs) information over the network while their privacy remains protected. It uses asymmetric cryptography and users are responsible for the generation of their own pair of public and private keys. There is no central entity which stores the information users input into the system; instead, that information is kept distributed among the vehicles that make up the network. On top of that, this system requires no roadside infrastructure. Precisely, our main objective with Chains of Trust was to show that just by relying on people¿s driving habits and the sporadic nature of their encounters with other drivers a successful reputation system could be built. The second contribution of this thesis is the application simulator poiSim. Many¿s the time a new VANET application is presented and its authors back their findings using simulation results from renowned networks simulators like ns-2. The major issue with network simulators is that they were not designed with that purpose in mind and handling simulations with hundreds of nodes requires a massive processing power. As a result, authors run small simulations (between 50 and 100 nodes) with vehicles that move randomly in a squared area instead of using real maps, which rend unrealistic results. We show that by building tailored application simulators we can obtain more realistic results. The application simulator poiSim processes a realistic mobility trace produced by a Multi-agent Microscopic Traffic Simulator developed at ETH Zurich, which accurately describes the mobility patterns of 259,977 vehicles over regional maps of Switzerland for 24 hours. This simulation runs on a desktop PC and lasts approximately 120 minutes. In our third contribution we took Chains of Trust one step further in the protection of user privacy to develop Anonymous Chains of Trust. In this system users can temporarily exchange their identity with other users they trust, thus making it impossible for an attacker to know in all certainty who input a particular piece of information into the system. To the best of our knowledge, this is the first time this technique has been used in a reputation system. Finally, in our last contribution we explore a different form of communication for VANETs. The vast majority of VANET applications rely on the IEEE 802.11p/Wireless Access in Vehicular Environments (WAVE) standard or some other form of radio communication. This poses a security risk if we consider how vulnerable radio transmission is to intentional jamming and natural interferences: an attacker could easily block all radio communication in a certain area if his transmitter is powerful enough. Visual Light Communication (VLC), on the other hand, is resilient to jamming over a wide area because it relies on visible light to transmit information and ,unlike WAVE, it has no scalability problems. In this thesis we show that VLC is a secure and valuable form of communication in VANETs.

Electrowetting technology, known since more than 100 years, just recently was successfully applied for the fabrication of devices such as pixels, liquid lenses and µTas (micro total analysis systems). Some of those devices are already a market product and some others are expected to reach the maturity to be marketed in the short period, although some fundamental aspects of the electrowetting phenomenon are not yet clear, like the origin of the saturation and the driving forces that lead to a contact angle variation. In the dissertation are presented several contributions to the electrowetting technology. First, have been reported the preliminary evidences about the contactless variation of the contact angle. Furthermore, these phenomena have been studied deeply and rigorous experimental work has been performed. Experimental data have been cross checked with simulations results and theoretical calculations. Finally, the results of the contactless electrowetting experiments lead us to be able to state that the driving element of the contact angle variation is the charge. Contactless electrowetting method has also unlocked the possibility to experimentally measure the impact of surrounding humidity in electrowetting dynamics and the limitations that introduce in the saturation of contact angle. The relationship between relative humidity and saturation contact angle resulted to be directly proportional and in line with the Peek¿s law prediction, here applied to a system in the micro scale. Therefore the last part of the dissertation was dedicated to the study of the charge driving of an electrowetting device in order to be able to control and predict the contact angle dynamics. As additional results it has been found that charge injection rate affects the speed of the contact angle variation, with negligible effects on the contact angle saturation. Cross checking the experimental results with theoretical predictions it has been found that the approximation of a droplet to a spherical cap gives a very good result while no clear contributions could be given to the saturation problem, leaving it open and without any clear solution, so far. Additionally, in this work contains a comprehensive review of state of the art of electrowetting technology and a detailed description of the multiphysic simulation method used.
La tecnología "Electrowetting", conocida desde hace más de 100 años, solo recientemente ha podido ser aplicada con éxito a dispositivos como pixeles, lentes líquidas y µTas (sístemas integrados de análisis). Algunos de estos productos ya se encuentran en el mercado, otros estan a punto de llegar a la madurez necesaria para ser comercializados, aún así, muchos aspectos fundamentales del fenomeno del "electrowetting" no están del todo claros, por ejemplo, el origen de la saturación del ángulo de contacto y las fuerzas que inducen la variación de este ángulo. En este trabajo de investigación se presentan varias contribuciones para entender mejor la technología "electrowetting". Primero, se han presentado evidencias preliminares de la variación "sin contacto" de ángulo de contacto. A continuación, estas observaciones han sido estudiadas profunda y rigurosamente con trabajo experimental. Finalmente, los resultados experimentales del electrowetting sin contacto han permitido entender que lo que induce la variación del ángulo de contacto es la carga. El "electrowetting" sin contacto permite la medida experimental del impacto de la húmedad de la atmosfera en las dinámicas del "electrowetting" y las limitaciones que ésta induce en el ángulo de contacto final. La relación entre la húmedad relativa del átmosfera y la saturación del ángulo de contacto es directa: contra más húmedad, más alto es el ángulo en saturación, en linea con las predicciones de la ley de Peek, en este caso, aplicado a microescala. La última parte del trabajo se ha dedicado a estudiar el control en carga de un dispositivo electrowetting para poder predecir y controlar las dinámicas de variación del ángulo de contacto. Como resultado adicional, se ha visto que el control de inyección de carga afecta la velocidad de variación del ángulo de contacto, con efectos segundarios despreciables en el ángulo final en saturación. Cruzando los resultados experimentales con las predicciones teóricas ha sido verificado que la aproximación de la gota a un casquete esférico da buenos resultados teóricos mientras no se ha podido dar ninguna contribución clara para la resolución del problema del ángulo de contacto, dejando abierto el tema. En este trabajo contiene además una revisión del estado del arte de la tecnología electrowetting y una descripción detallada del método de simulación multifísica usado.

This work deals with the research on organic solar cells based on small-molecules semiconductors. In particular, organic solar cells of this thesis have been used tetraphenyldibenzoperiflanthene as donor material and fullerene C70 as acceptor material. In the first part of this thesis, we focus on the influence of the density of states of the donor layer on the characteristic parameters of solar cells. Further, organic solar cells with p-i-n structure are presented, where the intrinsic layer is obtained by coevaporation of donor and acceptor. The influence of the thickness of the intrinsic layer on the p-i-n solar cell characteristic is analysed. In the second part, an equivalent circuit for organic solar cells is presented. A new term is added to the standard model representing recombination losses in the active layer of the device. The analysis of the characteristics of current - voltage measured at different illumination intensities allows the estimation of the term recombination. The model clearly separates technological issues (series and parallel resistance) from effects related to the physics of the device (recombination losses). It also allows obtaining an effective mobility-lifetime product in the active layer of the device to be determined, characterising its state of degradation.
En aquesta tesi s’investiguen cèl·lules solars orgàniques basades en semiconductors de petita molècula. En particular, les cèl·lules solars orgàniques d’aquesta tesi han emprat tetraphenyldibenzoperiflanthene com material donador i ful·lerè C70 com material acceptador. En la primera part d'aquesta tesi, ens centrem en la influència de la densitat d'estats de la capa donadora en els paràmetres característics de les cèl·lules solars. Més endavant, es presenten cèl·lules solars orgàniques amb una estructura p-i-n, on la capa intrínseca s'obté per l'evaporació conjunta del donador i l’acceptador. S'analitza la influència del gruix de la capa intrínseca de la cèl·lula solar p-i-n en la característica de la cèl·lula solar. En la segona part, es presenta un circuit equivalent per a les cèl·lules solars orgàniques. S'afegeix un nou terme en el model estàndard que representa les pèrdues de recombinació a la capa activa del dispositiu. L’anàlisi de les característiques de corrent-tensió mesurades a diferents intensitats de llum permeten l'estimació del terme de recombinació. El model separa clarament les qüestions tecnològiques (resistències en sèrie i en paral·lel) dels efectes relacionats amb la física del dispositiu (pèrdues de recombinació). També permet l’obtenció d’un producte de la mobilitat - temps de vida efectiu a la capa activa del dispositiu a ser determinat, la caracterització del seu estat de degradació.

This PhD dissertation describes the research and development of a new low-cost medium wavelength infrared MWIR monolithic imager technology for high-speed uncooled industrial applications. It takes the baton on the latest technological advances in the field of vapour phase deposition (VPD) PbSe-based medium wavelength IR (MWIR) detection accomplished by the industrial partner NIT S.L., adding fundamental knowledge on the investigation of novel VLSI analog and mixed-signal design techniques at circuit and system levels for the development of the readout integrated device attached to the detector. The work supports on the hypothesis that, by the use of the preceding design techniques, current standard inexpensive CMOS technologies fulfill all operational requirements of the VPD PbSe detector in terms of connectivity, reliability, functionality and scalability to integrate the device. The resulting monolithic PbSe-CMOS camera must consume very low power, operate at kHz frequencies, exhibit good uniformity and fit the CMOS read-out active pixels in the compact pitch of the focal plane, all while addressing the particular characteristics of the MWIR detector: high dark-to-signal ratios, large input parasitic capacitance values and remarkable mismatching in PbSe integration. In order to achieve these demands, this thesis proposes null inter-pixel crosstalk vision sensor architectures based on a digital-only focal plane array (FPA) of configurable pixel sensors. Each digital pixel sensor (DPS) cell is equipped with fast communication modules, self-biasing, offset cancellation, analog-to-digital converter (ADC) and fixed pattern noise (FPN) correction. In-pixel power consumption is minimized by the use of comprehensive MOSFET subthreshold operation. The main aim is to potentiate the integration of PbSe-based infra-red (IR)-image sensing technologies so as to widen its use, not only in distinct scenarios, but also at different stages of PbSe-CMOS integration maturity. For this purpose, we posit to investigate a comprehensive set of functional blocks distributed in two parallel approaches: • Frame-based “Smart” MWIR imaging based on new DPS circuit topologies with gain and offset FPN correction capabilities. This research line exploits the detector pitch to offer fully-digital programmability at pixel level and complete functionality with input parasitic capacitance compensation and internal frame memory. • Frame-free “Compact”-pitch MWIR vision based on a novel DPS lossless analog integrator and configurable temporal difference, combined with asynchronous communication protocols inside the focal plane. This strategy is conceived to allow extensive pitch compaction and readout speed increase by the suppression of in-pixel digital filtering, and the use of dynamic bandwidth allocation in each pixel of the FPA. In order make the electrical validation of first prototypes independent of the expensive PbSe deposition processes at wafer level, investigation is extended as well to the development of affordable sensor emulation strategies and integrated test platforms specifically oriented to image read-out integrated circuits. DPS cells, imagers and test chips have been fabricated and characterized in standard 0.15μm 1P6M, 0.35μm 2P4M and 2.5μm 2P1M CMOS technologies, all as part of research projects with industrial partnership. The research has led to the first high-speed uncooled frame-based IR quantum imager monolithically fabricated in a standard VLSI CMOS technology, and has given rise to the Tachyon series [1], a new line of commercial IR cameras used in real-time industrial, environmental and transportation control systems. The frame-free architectures investigated in this work represent a firm step forward to push further pixel pitch and system bandwidth up to the limits imposed by the evolving PbSe detector in future generations of the device.
La present tesi doctoral descriu la recerca i el desenvolupament d'una nova tecnologia monolítica d'imatgeria infraroja de longitud d'ona mitja (MWIR), no refrigerada i de baix cost, per a usos industrials d'alta velocitat. El treball pren el relleu dels últims avenços assolits pel soci industrial NIT S.L. en el camp dels detectors MWIR de PbSe depositats en fase vapor (VPD), afegint-hi coneixement fonamental en la investigació de noves tècniques de disseny de circuits VLSI analògics i mixtes pel desenvolupament del dispositiu integrat de lectura unit al detector pixelat. Es parteix de la hipòtesi que, mitjançant l'ús de les esmentades tècniques de disseny, les tecnologies CMOS estàndard satisfan tots els requeriments operacionals del detector VPD PbSe respecte a connectivitat, fiabilitat, funcionalitat i escalabilitat per integrar de forma econòmica el dispositiu. La càmera PbSe-CMOS resultant ha de consumir molt baixa potència, operar a freqüències de kHz, exhibir bona uniformitat, i encabir els píxels actius CMOS de lectura en el pitch compacte del pla focal de la imatge, tot atenent a les particulars característiques del detector: altes relacions de corrent d'obscuritat a senyal, elevats valors de capacitat paràsita a l'entrada i dispersions importants en el procés de fabricació. Amb la finalitat de complir amb els requisits previs, es proposen arquitectures de sensors de visió de molt baix acoblament interpíxel basades en l'ús d'una matriu de pla focal (FPA) de píxels actius exclusivament digitals. Cada píxel sensor digital (DPS) està equipat amb mòduls de comunicació d'alta velocitat, autopolarització, cancel·lació de l'offset, conversió analògica-digital (ADC) i correcció del soroll de patró fixe (FPN). El consum en cada cel·la es minimitza fent un ús exhaustiu del MOSFET operant en subllindar. L'objectiu últim és potenciar la integració de les tecnologies de sensat d'imatge infraroja (IR) basades en PbSe per expandir-ne el seu ús, no només a diferents escenaris, sinó també en diferents estadis de maduresa de la integració PbSe-CMOS. En aquest sentit, es proposa investigar un conjunt complet de blocs funcionals distribuïts en dos enfocs paral·lels: - Dispositius d'imatgeria MWIR "Smart" basats en frames utilitzant noves topologies de circuit DPS amb correcció de l'FPN en guany i offset. Aquesta línia de recerca exprimeix el pitch del detector per oferir una programabilitat completament digital a nivell de píxel i plena funcionalitat amb compensació de la capacitat paràsita d'entrada i memòria interna de fotograma. - Dispositius de visió MWIR "Compact"-pitch "frame-free" en base a un novedós esquema d'integració analògica en el DPS i diferenciació temporal configurable, combinats amb protocols de comunicació asíncrons dins del pla focal. Aquesta estratègia es concep per permetre una alta compactació del pitch i un increment de la velocitat de lectura, mitjançant la supressió del filtrat digital intern i l'assignació dinàmica de l'ample de banda a cada píxel de l'FPA. Per tal d'independitzar la validació elèctrica dels primers prototips respecte a costosos processos de deposició del PbSe sensor a nivell d'oblia, la recerca s'amplia també al desenvolupament de noves estratègies d'emulació del detector d'IR i plataformes de test integrades especialment orientades a circuits integrats de lectura d'imatge. Cel·les DPS, dispositius d'imatge i xips de test s'han fabricat i caracteritzat, respectivament, en tecnologies CMOS estàndard 0.15 micres 1P6M, 0.35 micres 2P4M i 2.5 micres 2P1M, tots dins el marc de projectes de recerca amb socis industrials. Aquest treball ha conduït a la fabricació del primer dispositiu quàntic d'imatgeria IR d'alta velocitat, no refrigerat, basat en frames, i monolíticament fabricat en tecnologia VLSI CMOS estàndard, i ha donat lloc a Tachyon, una nova línia de càmeres IR comercials emprades en sistemes de control industrial, mediambiental i de transport en temps real.

Offshore wind is emerging as one of the future energy vectors. Offshore wind power plants locations provide more strong and constant wind speed that allows to extract more power compared to onshore locations. In addition, as wind turbine components transportation is less restricted to terrestrial infrastructure, bigger and more powerful wind turbines can be installed offshore. In Europe, 1,567 MW of offshore wind power was installed in 2013. It represents the 14\% of the total wind power installed in Europe. Offshore wind power plants near the shore can be connected to the main grid by means of conventional AC technology. However, if these wind farms are installed further than 80-100 km, the use of AC equipment is economically infeasible due to reactive power issues. In these applications, HVDC system based on static converters can be used. The projects build and commissioned nowadays are based on point-to-point connections, where, each wind farm or wind farm clusters are connected to the terrestrial grid individually. Consequently, these lines might be understood as an extension of the AC system. If different offshore wind farms are interconnected between them and connected at the same time to different AC systems, for example, different countries, the DC grid is created. This scenario creates one of the most important challenges in the electrical power system since its creation, more than 100 years ago. The most relevant challenges to be addressed are the stability and operation of the DC grid and the integration and interaction with the AC grid. This thesis addresses various aspects related to the future Multiterminal-HVDC systems for transmission of offshore wind power. First, the voltage control and the system operations are discussed and verified by means of emulations using an HVDC scaled experimental platform built for this purpose. Voltage stability might be endangered during contingencies due to the different inertia time constant of the AC and the DC system. DC systems only have the inertia of the capacitors compared to synchronous machines rotating masses of the AC systems. Therefore, in faulty conditions the power transmitted through the DC system must be reduced quickly and efficiently. For this reason, in this thesis a coordinated power reduction algorithm taking advantage of Dynamic Braking Resistors (DBR) connected to onshore converter stations and the ability of the power plants to reduce the generated power is presented. From the AC and DC grids integration point of view, the connection point between the offshore grid and the AC grid might be located remotely leading to a connection with a reduced Short Circuit Ratio (SCR). In the literature, several issues regarding the connection of transistor-based power converters to weak AC grid have been reported. In this thesis am advanced control for Voltage Source Converters connected to weak grids is presented and tested by means of simulations. From the AC and DC grids interactions, the voltage stability is not enough to operate a DC grid. Transport System Operators (TSO) operates the power flow through the cables and the power exchanged between by the power converters. In this thesis, a novel hierarchical power flow control method is presented. The aim of the proposed power flow control is to obtain the desired power flows changing the voltage control set-points while the system stability is ensured. Finally, a control procedure for offshore wind farms based on Squirrel Cage Induction Generators connected to a single power converter is introduced.
L'energia eòlica marina emergeix com un dels vectors energètics del futur. Les localitzacions eòliques marines proporcionen vens més forts i constants que les terrestres, cosa que permet extreure més potència. A més a més, els aerogeneradors marins poden ser més grans i més potents ja que es redueixen les limitacions de gàlib existent en les infraestructures terrestres. A tall d'exemple, l'any 2013 a Europa es van instal.lar 1.567 MW de potència eòlica marina, cosa que representa un 14\% de la potència eòlica instal.lada a Europa. Els parcs eòlics marins poden ser connectats a la xarxa elèctrica terrestre utilitzant emparamenta convencional de corrent alterna, però quan la distancia amb la costa excedeix els 80-100 km l'ús d'aquesta tecnologia es torna econòmicament inviable degut a l'energia reactiva generada en els conductors. Per solucionar aquest problema, s'emparen els sistemes en corrent continua basats en convertidors estàtics. Els projectes construïts o projectats a dia d'avui es basen en esquemes de connexió punt-a-punt, on, cada parc eòlic o agrupació de parcs eòlics es troba connectat a la xara terrestre individualment. En conseqüència, l'operació d'aquestes línies es pot considerar com una extensió de la xarxa d'alterna. Però, si s'interconnecten diferents parc eòlics amb diferents xarxes terrestres d'alterna (per exemple, diferents països) en corrent continua, s'obtenen xarxes en corrent continua. Aquest nou escenari crea un dels majors reptes des de la creació dels sistema elèctric de potencia, ara fa més de 100 anys. Entre aquests reptes hi ha l'estabilitat i l'operació dels sistemes en corrent contínua i la seva integració i coexistència amb les xarxes en corrent alterna. En la present tesis s'han estudiat diferents aspectes dels futurs sistemes multi terminal en alta tensió en corrent contínua (HVDC, en anglès) per la transmissió de potencia generada mitjançant parcs eòlics marins. Primerament, es descriu el control de tensió i els modes d'operació dels sistemes multi terminal i es verifiquen en una plataforma experimental construïda per aquest propòsit. L'estabilitat de tensió dels sistemes en corrent continua, es pot veure afectada durant una falta a la xarxa d'alterna degut a la reduïda inèrcia dels sistemes multi terminal, només formada pels condensadors dels convertidors i els cables. Així la potència que no pot injectar a la xarxa ha de ser reduïda de forma ràpida i eficient. Per això, en aquesta tesis es presenta un sistema coordinat de reducció de potència que utilitza la resistència de frenat dels convertidors de connexió a la xarxa i els mètodes de reducció de potència dels parcs eòlics. Des del punt de vista de la integració de les xarxes en continua i en alterna, el punt d'interconnexió pot estar localitzat llunys dels grans centres de generació, la qual cosa implica tenir una potència de curtcircuit molt reduïda. En la bibliografia científica s'han descrit diverses problemàtiques a l'hora de connectar un convertidor de commutació forçada a les xarxes dèbils. Per tal de pal.liar aquests inconvenients, en aquesta tesis es presenta un algorisme avançat de connexió de convertidors a xarxes dèbils basat en control vectorial. Des del punt de vista de les interaccions i interoperabilitat dels sistemes en corrent alterna i continua, no n'hi ha suficient en garantir l'estabilitat, ja que el propòsit finals dels operadors de xarxa és fer fluir una potencia a traves de la xarxa per tal de satisfer la demanda. Per aquest propòsit en aquesta tesis es presenta un control jeràrquic de control del flux de potència que fixa el flux de potència a traves d'una xarxa multi terminal canviant les consignes del control primari, tot assegurant l'estabilitat del sistema. Per tancar la tesis, es presenta un nou controlador per parcs eòlics basats en aerogeneradors de gàbia d'esquirol controlats per un sol convertidor.

The deployment delays for EUVL, forces IC design to continue using 193nm wavelength lithography with innovative and costly techniques in order to faithfully print sub-wavelength features and combat lithography induced process variations. The effect of the lithography gap in current and upcoming technologies is to cause severe distortions due to optical diffraction in the printed patterns and thus degrading manufacturing yield. Therefore, a paradigm shift in layout design is mandatory towards more regular litho-friendly cell designs in order to improve line pattern resolution. However, it is still unclear the amount of layout regularity that can be introduced and how to measure the benefits and weaknesses of regular layouts. This dissertation is focused on searching the degree of layout regularity necessary to combat lithography variability and outperform the layout quality of a design. The main contributions that have been addressed to accomplish this objective are: (1) the definition of several layout design guidelines to mitigate lithography variability; (2) the proposal of a parametric yield estimation model to evaluate the lithography impact on layout design; (3) the development of a global Layout Quality Metric (LQM) including a Regularity Metric (RM) to capture the degree of layout regularity of a layout implementation and; (4) the creation of different layout architectures exploiting the benefits of layout regularity to outperform line-pattern resolution, referred as Adaptive Lithography Aware Regular Cell Designs (ALARCs). The first part of this thesis provides several regular layout design guidelines derived from lithography simulations so that several important lithography related variation sources are minimized. Moreover, a design level methodology, referred as gate biasing, is proposed to overcome systematic layout dependent variations, across-field variations and the non-rectilinear gate effect (NRG) applied to regular fabrics by properly configuring the drawn transistor channel length. The second part of this dissertation proposes a lithography yield estimation model to predict the amount of lithography distortion expected in a printed layout due to lithography hotspots with a reduced set of lithography simulations. An efficient lithography hotspot framework to identify the different layout pattern configurations, simplify them to ease the pattern analysis and classify them according to the lithography degradation predicted using lithography simulations is presented. The yield model is calibrated with delay measurements of a reduced set of identical test circuits implemented in a CMOS 40nm technology and thus actual silicon data is utilized to obtain a more realistic yield estimation. The third part of this thesis presents a configurable Layout Quality Metric (LQM) that considering several layout aspects provides a global evaluation of a layout design with a single score. The LQM can be leveraged by assigning different weights to each evaluation metric or by modifying the parameters under analysis. The LQM is here configured following two different set of partial metrics. Note that the LQM provides a regularity metric (RM) in order to capture the degree of layout regularity applied in a layout design. Lastly, this thesis presents different ALARC designs for a 40nm technology using different degrees of layout regularity and different area overheads. The quality of the gridded regular templates is demonstrated by automatically creating a library containing 266 cells including combinational and sequential cells and synthesizing several ITC'99 benchmark circuits. Note that the regular cell libraries only presents a 9\% area penalty compared to the 2D standard cell designs used for comparison and thus providing area competitive designs. The layout evaluation of benchmark circuits considering the LQM shows that regular layouts can outperform other 2D standard cell designs depending on the layout implementation.
Los continuos retrasos en la implementación de la EUVL, fuerzan que el diseño de IC se realice mediante litografía de longitud de onda de 193 nm con innovadoras y costosas técnicas para poder combatir variaciones de proceso de litografía. La gran diferencia entre la longitud de onda y el tamaño de los patrones causa severas distorsiones debido a la difracción óptica en los patrones impresos y por lo tanto degradando el yield. En consecuencia, es necesario realizar un cambio en el diseño de layouts hacia diseños más regulares para poder mejorar la resolución de los patrones. Sin embargo, todavía no está claro el grado de regularidad que se debe introducir y como medir los beneficios y los perjuicios de los diseños regulares. El objetivo de esta tesis es buscar el grado de regularidad necesario para combatir las variaciones de litografía y mejorar la calidad del layout de un diseño. Las principales contribuciones para conseguirlo son: (1) la definición de diversas reglas de diseño de layout para mitigar las variaciones de litografía; (2) la propuesta de un modelo para estimar el yield paramétrico y así evaluar el impacto de la litografía en el diseño de layout; (3) el diseño de una métrica para analizar la calidad de un layout (LQM) incluyendo una métrica para capturar el grado de regularidad de un diseño (RM) y; (4) la creación de diferentes tipos de layout explotando los beneficios de la regularidad, referidos como Adaptative Lithography Aware Regular Cell Designs (ALARCs). La primera parte de la tesis, propone las diversas reglas de diseño para layouts regulares derivadas de simulaciones de litografía de tal manera que las fuentes de variación de litografía son minimizadas. Además, se propone una metodología de diseño para layouts regulares, referida como "gate biasing" para contrarrestar las variaciones sistemáticas dependientes del layout, las variaciones en la ventana de proceso del sistema litográfico y el efecto de puerta no rectilínea para configurar la longitud del canal del transistor correctamente. La segunda parte de la tesis, detalla el modelo de estimación del yield de litografía para predecir mediante un número reducido de simulaciones de litografía la cantidad de distorsión que se espera en un layout impreso debida a "hotspots". Se propone una eficiente metodología que identifica los distintos patrones de un layout, los simplifica para facilitar el análisis de los patrones y los clasifica en relación a la degradación predecida mediante simulaciones de litografía. El modelo de yield se calibra utilizando medidas de tiempo de un número reducido de idénticos circuitos de test implementados en una tecnología CMOS de 40nm y de esta manera, se utilizan datos de silicio para obtener una estimación realista del yield. La tercera parte de este trabajo, presenta una métrica para medir la calidad del layout (LQM), que considera diversos aspectos para dar una evaluación global de un diseño mediante un único valor. La LQM puede ajustarse mediante la asignación de diferentes pesos para cada métrica de evaluación o modificando los parámetros analizados. La LQM se configura mediante dos conjuntos de medidas diferentes. Además, ésta incluye una métrica de regularidad (RM) para capturar el grado de regularidad que se aplica en un diseño. Finalmente, esta disertación presenta los distintos diseños ALARC para una tecnología de 40nm utilizando diversos grados de regularidad y diferentes impactos en área. La calidad de estos diseños se demuestra creando automáticamente una librería de 266 celdas incluyendo celdas combinacionales y secuenciales y, sintetizando diversos circuitos ITC'99. Las librerías regulares solo presentan un 9% de impacto en área comparado con diseños de celdas estándar 2D y por tanto proponiendo diseños competitivos en área. La evaluación de los circuitos considerando la LQM muestra que los diseños regulares pueden mejorar otros diseños 2D dependiendo de la implementación del layout.

Fast and Complex Data Memory systems has become a necessity in modern computational units in today's integrated circuits. These memory systems are integrated in form of large embedded memory for data manipulation and storage. This goal has been achieved by the aggressive scaling of transistor dimensions to few nanometer (nm) sizes, though; such a progress comes with a drawback, making it critical to obtain high yields of the chips. Process variability, due to manufacturing imperfections, along with temporal aging, mainly induced by higher electric fields and temperature, are two of the more significant threats that can no longer be ignored in nano-scale embedded memory circuits, and can have high impact on their robustness. Static Random Access Memory (SRAM) is one of the most used embedded memories; generally implemented with the smallest device dimensions and therefore its robustness can be highly important in nanometer domain design paradigm. Their reliable operation needs to be considered and achieved both in cell and also in architectural SRAM array design. Recently, and with the approach to near/below 10nm design generations, novel non-FET devices such as Memristors are attracting high attention as a possible candidate to replace the conventional memory technologies. In spite of their favorable characteristics such as being low power and highly scalable, they also suffer with reliability challenges, such as process variability and endurance degradation, which needs to be mitigated at device and architectural level. This thesis work tackles such problem of reliability concerns in memories by utilizing advanced reconfiguration techniques. In both SRAM arrays and Memristive crossbar memories novel reconfiguration strategies are considered and analyzed, which can extend the memory lifetime. These techniques include monitoring circuits to check the reliability status of the memory units, and architectural implementations in order to reconfigure the memory system to a more reliable configuration before a fail happens.
Actualmente, el diseño de sistemas de memoria en circuitos integrados busca continuamente que sean más rápidos y complejos, lo cual se ha vuelto de gran necesidad para las unidades de computación modernas. Estos sistemas de memoria están integrados en forma de memoria embebida para una mejor manipulación de los datos y de su almacenamiento. Dicho objetivo ha sido conseguido gracias al agresivo escalado de las dimensiones del transistor, el cual está llegando a las dimensiones nanométricas. Ahora bien, tal progreso ha conllevado el inconveniente de una menor fiabilidad, dado que ha sido altamente difícil obtener elevados rendimientos de los chips. La variabilidad de proceso - debido a las imperfecciones de fabricación - junto con la degradación de los dispositivos - principalmente inducido por el elevado campo eléctrico y altas temperaturas - son dos de las más relevantes amenazas que no pueden ni deben ser ignoradas por más tiempo en los circuitos embebidos de memoria, echo que puede tener un elevado impacto en su robusteza final. Static Random Access Memory (SRAM) es una de las celdas de memoria más utilizadas en la actualidad. Generalmente, estas celdas son implementadas con las menores dimensiones de dispositivos, lo que conlleva que el estudio de su robusteza es de gran relevancia en el actual paradigma de diseño en el rango nanométrico. La fiabilidad de sus operaciones necesita ser considerada y conseguida tanto a nivel de celda de memoria como en el diseño de arquitecturas complejas basadas en celdas de memoria SRAM. Actualmente, con el diseño de sistemas basados en dispositivos de 10nm, dispositivos nuevos no-FET tales como los memristores están atrayendo una elevada atención como posibles candidatos para reemplazar las actuales tecnologías de memorias convencionales. A pesar de sus características favorables, tales como el bajo consumo como la alta escabilidad, ellos también padecen de relevantes retos de fiabilidad, como son la variabilidad de proceso y la degradación de la resistencia, la cual necesita ser mitigada tanto a nivel de dispositivo como a nivel arquitectural. Con todo esto, esta tesis doctoral afronta tales problemas de fiabilidad en memorias mediante la utilización de técnicas de reconfiguración avanzada. La consideración de nuevas estrategias de reconfiguración han resultado ser validas tanto para las memorias basadas en celdas SRAM como en `memristive crossbar¿, donde se ha observado una mejora significativa del tiempo de vida en ambos casos. Estas técnicas incluyen circuitos de monitorización para comprobar la fiabilidad de las unidades de memoria, y la implementación arquitectural con el objetivo de reconfigurar los sistemas de memoria hacia una configuración mucho más fiables antes de que el fallo suceda