Статті в журналах з теми "22-nm technology node"
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Ознайомтеся з топ-49 статей у журналах для дослідження на тему "22-nm technology node".
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Li, Zongru, Christopher Jarrett Elash, Chen Jin, Li Chen, Jiesi Xing, Zhiwu Yang, and Shuting Shi. "Comparison of Total Ionizing Dose Effects in 22-nm and 28-nm FD SOI Technologies." Electronics 11, no. 11 (June 1, 2022): 1757. http://dx.doi.org/10.3390/electronics11111757.
Повний текст джерелаXu, Peng, Yinghua Piao, Liang Ge, Cheng Hu, Lun Zhu, Zhiwei Zhu, David Wei Zhang, and Dongping Wu. "Investigation of Novel Junctionless MOSFETs for Technology Node Beyond 22 nm." ECS Transactions 44, no. 1 (December 15, 2019): 33–39. http://dx.doi.org/10.1149/1.3694293.
Повний текст джерелаHolmes, Steven. "22-nm-node technology active-layer patterning for planar transistor devices." Journal of Micro/Nanolithography, MEMS, and MOEMS 9, no. 1 (January 1, 2010): 013001. http://dx.doi.org/10.1117/1.3302125.
Повний текст джерелаBaklanov, Mikhail R., Evgeny A. Smirnov, and Larry Zhao. "Ultra Low Dielectric Constant Materials for 22 nm Technology Node and Beyond." ECS Transactions 35, no. 4 (December 16, 2019): 717–28. http://dx.doi.org/10.1149/1.3572315.
Повний текст джерелаSaxena, Shubhangi, and Kamsali Manjunathachari. "Novel Nanoelectronic Materials and Devices: For Future Technology Node." ECS Transactions 107, no. 1 (April 24, 2022): 15701–11. http://dx.doi.org/10.1149/10701.15701ecst.
Повний текст джерелаHuang, Zhengfeng, Yan Zhang, Wenhui Wu, Lanxi Duan, Huaguo Liang, Yiming Ouyang, Aibin Yan, and Tai Song. "A high-speed quadruple-node-upset-tolerant latch in 22 nm CMOS technology." Microelectronics Reliability 147 (August 2023): 115032. http://dx.doi.org/10.1016/j.microrel.2023.115032.
Повний текст джерелаLi, Zongru, Christopher Elash, Chen Jin, Li Chen, Shi-Jie Wen, Rita Fung, Jiesi Xing, Shuting Shi, Zhi Wu Yang, and Bharat L. Bhuva. "SEU performance of Schmitt-trigger-based flip-flops at the 22-nm FD SOI technology node." Microelectronics Reliability 146 (July 2023): 115033. http://dx.doi.org/10.1016/j.microrel.2023.115033.
Повний текст джерелаLu, Peng, Can Yang, Yifei Li, Bo Li, and Zhengsheng Han. "Three-Dimensional TID Hardening Design for 14 nm Node SOI FinFETs." Eng 2, no. 4 (December 3, 2021): 620–31. http://dx.doi.org/10.3390/eng2040039.
Повний текст джерелаChanghwan Shin, Min Hee Cho, Yasumasa Tsukamoto, Bich-Yen Nguyen, Carlos Mazuré, Borivoje Nikolić, and Tsu-Jae King Liu. "Performance and Area Scaling Benefits of FD-SOI Technology for 6-T SRAM Cells at the 22-nm Node." IEEE Transactions on Electron Devices 57, no. 6 (June 2010): 1301–9. http://dx.doi.org/10.1109/ted.2010.2046070.
Повний текст джерелаShin, Changhwan, Nattapol Damrongplasit, Xin Sun, Yasumasa Tsukamoto, Borivoje Nikolic, and Tsu-Jae King Liu. "Performance and Yield Benefits of Quasi-Planar Bulk CMOS Technology for 6-T SRAM at the 22-nm Node." IEEE Transactions on Electron Devices 58, no. 7 (July 2011): 1846–54. http://dx.doi.org/10.1109/ted.2011.2139213.
Повний текст джерелаMah, Siew Kien, Pin Jern Ker, Ibrahim Ahmad, Noor Faizah Zainul Abidin, and Mansur Mohammed Ali Gamel. "A Feasible Alternative to FDSOI and FinFET: Optimization of W/La2O3/Si Planar PMOS with 14 nm Gate-Length." Materials 14, no. 19 (September 30, 2021): 5721. http://dx.doi.org/10.3390/ma14195721.
Повний текст джерелаDuari, Chusen, Shilpi Birla, and Amit Kumar Singh. "A Dual Port 8T SRAM Cell Using FinFET & CMOS Logic for Leakage Reduction and Enhanced Read & Write Stability." Journal of Integrated Circuits and Systems 15, no. 2 (July 31, 2020): 1–7. http://dx.doi.org/10.29292/jics.v15i2.140.
Повний текст джерелаMazurier, J., O. Weber, F. Andrieu, A. Toffoli, O. Thomas, F. Allain, J. P. Noel, M. Belleville, O. Faynot, and T. Poiroux. "Ultra-Thin Body and Buried Oxide (UTBB) FDSOI Technology with Low Variability and Power Management Capability for 22 nm Node and Below." Journal of Low Power Electronics 8, no. 1 (February 1, 2012): 125–32. http://dx.doi.org/10.1166/jolpe.2012.1173.
Повний текст джерелаKarthikeyan, A., and P. S. Mallick. "Optimization Techniques for CNT Based VLSI Interconnects — A Review." Journal of Circuits, Systems and Computers 26, no. 03 (November 21, 2016): 1730002. http://dx.doi.org/10.1142/s0218126617300021.
Повний текст джерелаValasa, Sresta, Shubham Tayal, and Laxman Raju Thoutam. "Design Insights into Thermal Performance of Vertically Stacked JL-NSFET with High-k Gate Dielectric for Sub 5-nm Technology Node." ECS Journal of Solid State Science and Technology 11, no. 4 (April 1, 2022): 041008. http://dx.doi.org/10.1149/2162-8777/ac6627.
Повний текст джерелаVerbitskiy, V. G., S. V. Voevodin, V. V. Fedulov, G. V. Kalistyi, and D. O. Verbitskiy. "Manifestation of the channeling effect when manufacturing JFET transistors." Semiconductor Physics, Quantum Electronics and Optoelectronics 23, no. 04 (November 19, 2020): 379–84. http://dx.doi.org/10.15407/spqeo23.04.379.
Повний текст джерелаKwon, Ah-Young, Ju-Yeon Jeong, Hyun Park, Sohyun Hwang, Gwangil Kim, Haeyoun Kang, Jin-Hyung Heo, Hye Jin Lee, Tae-Heon Kim, and Hee Jung An. "miR-22-3p and miR-30e-5p Are Associated with Prognosis in Cervical Squamous Cell Carcinoma." International Journal of Molecular Sciences 23, no. 10 (May 17, 2022): 5623. http://dx.doi.org/10.3390/ijms23105623.
Повний текст джерелаKumar Rai, Mayank, Rajesh Khanna, and Sankar Sarkar. "Control of tube parameters on SWCNT bundle interconnect delay and power dissipation." Microelectronics International 31, no. 1 (December 20, 2013): 24–31. http://dx.doi.org/10.1108/mi-03-2013-0016.
Повний текст джерелаBoureau, Victor, Aurèle Durand, Patrice Gergaud, Delphine Le Cunff, Matthew Wormington, Denis Rouchon, Alain Claverie, Daniel Benoit, and Martin Hÿtch. "Dark-field electron holography as a recording of crystal diffraction in real space: a comparative study with high-resolution X-ray diffraction for strain analysis of MOSFETs." Journal of Applied Crystallography 53, no. 4 (June 18, 2020): 885–95. http://dx.doi.org/10.1107/s1600576720006020.
Повний текст джерелаMerad, Faiza, and Ahlam Guen-Bouazza. "DC performance analysis of a 20nm gate lenght n-type silicon GAA junctionless (Si JL-GAA) transistor." International Journal of Electrical and Computer Engineering (IJECE) 10, no. 4 (August 1, 2020): 4043. http://dx.doi.org/10.11591/ijece.v10i4.pp4043-4052.
Повний текст джерелаWu, Banqiu. "Next-generation lithography for 22 and 16 nm technology nodes and beyond." Science China Information Sciences 54, no. 5 (May 2011): 959–79. http://dx.doi.org/10.1007/s11432-011-4227-6.
Повний текст джерелаGanesh, Chokkakula, and Fazal Noorbasha. "Performance and Stability Analysis of Built-In Self-Read and Write Assist 10T SRAM Cell." Active and Passive Electronic Components 2023 (June 30, 2023): 1–17. http://dx.doi.org/10.1155/2023/3371599.
Повний текст джерелаMcCants, Carl E. "The IARPA Circuit Analysis Tools Program." EDFA Technical Articles 15, no. 4 (November 1, 2013): 52–54. http://dx.doi.org/10.31399/asm.edfa.2013-4.p052.
Повний текст джерелаSharma, Himanshu, and Karmjit Singh Sandha. "Impact of Intercalation Doping on the Conductivity of Multi-Layer Graphene Nanoribbon (MLGNR) in On-Chip Interconnects." Journal of Circuits, Systems and Computers 29, no. 12 (February 5, 2020): 2050185. http://dx.doi.org/10.1142/s0218126620501856.
Повний текст джерелаWang, Guilei, Qiang Xu, Tao Yang, Jinjuan Xiang, Jing Xu, Jianfeng Gao, Chunlong Li, et al. "Application of Atomic Layer Deposition Tungsten (ALD W) as Gate Filling Metal for 22 nm and Beyond Nodes CMOS Technology." ECS Journal of Solid State Science and Technology 3, no. 4 (2014): P82—P85. http://dx.doi.org/10.1149/2.015404jss.
Повний текст джерелаVeloso, Anabela, An De Keersgieter, Stephan Brus, Naoto Horiguchi, Philippe P. Absil, and Thomas Hoffmann. "Multi-Gate Fin Field-Effect Transistors Junctions Optimization by Conventional Ion Implantation for (Sub-)22 nm Technology Nodes Circuit Applications." Japanese Journal of Applied Physics 50, no. 4S (April 1, 2011): 04DC16. http://dx.doi.org/10.7567/jjap.50.04dc16.
Повний текст джерелаWang, G., Q. Xu, T. Yang, J. Luo, J. Xiang, J. Xu, G. Xu, et al. "Application of Atomic Layer Deposition Tungsten (ALD W) as Gate Filling Metal for 22 nm and Beyond Nodes CMOS Technology." ECS Transactions 58, no. 10 (August 31, 2013): 317–24. http://dx.doi.org/10.1149/05810.0317ecst.
Повний текст джерелаVeloso, Anabela, An De Keersgieter, Stephan Brus, Naoto Horiguchi, Philippe P. Absil, and Thomas Hoffmann. "Multi-Gate Fin Field-Effect Transistors Junctions Optimization by Conventional Ion Implantation for (Sub-)22 nm Technology Nodes Circuit Applications." Japanese Journal of Applied Physics 50, no. 4 (April 20, 2011): 04DC16. http://dx.doi.org/10.1143/jjap.50.04dc16.
Повний текст джерелаZhao, Chun, C. Z. Zhao, M. Werner, S. Taylor, and P. R. Chalker. "Advanced CMOS Gate Stack: Present Research Progress." ISRN Nanotechnology 2012 (February 9, 2012): 1–35. http://dx.doi.org/10.5402/2012/689023.
Повний текст джерелаCui, Hushan, Jun Luo, Jing Xu, Jianfeng Gao, Jinjuan Xiang, Zhaoyun Tang, Xiaolei Wang, et al. "Investigation of TaN as the wet etch stop layer for HKMG-last integration in the 22 nm and beyond nodes CMOS technology." Vacuum 119 (September 2015): 185–88. http://dx.doi.org/10.1016/j.vacuum.2015.05.021.
Повний текст джерелаVeloso, Anabela, Soon Aik Chew, Tom Schram, Harold Dekkers, Annemie Van Ammel, Thomas Witters, Hilde Tielens, et al. "W versus Co–Al as Gate Fill-Metal for Aggressively Scaled Replacement High-k/Metal Gate Devices for (Sub-)22 nm Technology Nodes." Japanese Journal of Applied Physics 52, no. 4S (April 1, 2013): 04CA03. http://dx.doi.org/10.7567/jjap.52.04ca03.
Повний текст джерелаDAOUD, HOUDA, SAMIR BENSELEM, SONIA ZOUARI, and MOURAD LOULOU. "USE OF ROBUST PREDICTIVE METHOD FOR NANO-CMOS PROCESS: APPLICATION TO BASIC BLOCK ANALOG CIRCUIT DESIGN." Journal of Circuits, Systems and Computers 21, no. 07 (November 2012): 1250061. http://dx.doi.org/10.1142/s0218126612500612.
Повний текст джерелаChiu, H. Y., Y. K. Fang, T. H. Chou, Y. T. Chiang, and C. I. Lin. "A novel STI etching technology to mitigate an inverse narrow width effect, and improve device performances for 90 nm node and beyond CMOS technology." Semiconductor Science and Technology 22, no. 10 (September 7, 2007): 1157–60. http://dx.doi.org/10.1088/0268-1242/22/10/013.
Повний текст джерела"Ultra Low Dielectric Constant Materials for 22 nm Technology Node and beyond." ECS Meeting Abstracts, 2011. http://dx.doi.org/10.1149/ma2011-01/22/1407.
Повний текст джерелаLi, Zongru, Christopher Elash, Jiesi Xing, Chen Jin, Li Chen, Shi-Jie Wen, Rita Fung, Shuting Shi, Zhi Wu Yang, and Bharat L. Bhuva. "SEU Performance of RHBD Flip-Flops Using Guard-Gates at 22-nm FDSOI Technology Node." IEEE Transactions on Nuclear Science, 2023, 1. http://dx.doi.org/10.1109/tns.2023.3284758.
Повний текст джерелаWang, Hanbin, Jinshun Bi, Jianhui Bu, Hainan Liu, Fazhan Zhao, Huajun Cao, and Chao Ai. "Characteristics of 22 nm UTBB-FDSOI technology with an ultra-wide temperature range." Semiconductor Science and Technology, August 4, 2022. http://dx.doi.org/10.1088/1361-6641/ac86ec.
Повний текст джерелаWang, Guilei, Jun Luo, Jinbiao Liu, Tao Yang, Yefeng Xu, Junfeng Li, Huaxiang Yin, et al. "pMOSFETs Featuring ALD W Filling Metal Using SiH4 and B2H6 Precursors in 22 nm Node CMOS Technology." Nanoscale Research Letters 12, no. 1 (April 26, 2017). http://dx.doi.org/10.1186/s11671-017-2080-2.
Повний текст джерелаSharma, Vijay Kumar. "A Survey on Low Power Design Approaches in nanoscale regime." Micro and Nanosystems 12 (June 23, 2020). http://dx.doi.org/10.2174/1876402912999200623120558.
Повний текст джерелаBarik, Rasmita, Rudra Sankar Dhar, Falah Awwad, and Mousa I. Hussein. "Evolution of type-II hetero-strain cylindrical-gate-all-around nanowire FET for exploration and analysis of enriched performances." Scientific Reports 13, no. 1 (July 14, 2023). http://dx.doi.org/10.1038/s41598-023-38239-x.
Повний текст джерелаYin, Zihan, Md Abdullah-Al Kaiser, Lamine Ousmane Camara, Mark Camarena, Maryam Parsa, Ajey Jacob, Gregory Schwartz, and Akhilesh Jaiswal. "IRIS: Integrated Retinal Functionality in Image Sensors." Frontiers in Neuroscience 17 (September 1, 2023). http://dx.doi.org/10.3389/fnins.2023.1241691.
Повний текст джерелаDobbie, Andy, Maksym Myronov, Xue-Chao Liu, Van Huy Nguyen, Evan Parker, and David Leadley. "Investigation of the Thermal Stability of Strained Ge Layers Grown at Low Temperature by Reduced-pressure Chemical Vapour Deposition on Si0.2Ge0.8 Relaxed Buffers." MRS Proceedings 1252 (2010). http://dx.doi.org/10.1557/proc-1252-i04-06.
Повний текст джерелаTang, Guangzhi, Kanishkan Vadivel, Yingfu Xu, Refik Bilgic, Kevin Shidqi, Paul Detterer, Stefano Traferro, et al. "SENECA: building a fully digital neuromorphic processor, design trade-offs and challenges." Frontiers in Neuroscience 17 (June 23, 2023). http://dx.doi.org/10.3389/fnins.2023.1187252.
Повний текст джерелаAyush, Poornima Mittal, and Rajesh Rohilla. "Modified Decoupled Sense Amplifier with Improved Sensing Speed for Low-Voltage Differential SRAM." ACM Transactions on Design Automation of Electronic Systems, August 2, 2023. http://dx.doi.org/10.1145/3611672.
Повний текст джерелаLetertre, Fabrice Jerome. "Formation of III-V Semiconductor Engineered Substrates Using Smart CutTM Layer Transfer Technology." MRS Proceedings 1068 (2008). http://dx.doi.org/10.1557/proc-1068-c01-01.
Повний текст джерелаMoreau, Stephane, Fré;déric Gaillard, Jean-Charles Barbé, Raphaël Gras, Gérard Passemard, and Joaquin Torres. "Mechanical Integrity Study of Air Gap Structures Assisted by FE Simulations." MRS Proceedings 1079 (2008). http://dx.doi.org/10.1557/proc-1079-n02-02.
Повний текст джерела"Application of Atomic Layer Deposition Tungsten (ALD W) as gate filling metal for 22 nm and beyond nodes CMOS technology." ECS Meeting Abstracts, 2013. http://dx.doi.org/10.1149/ma2013-02/24/1890.
Повний текст джерелаDhillon, Gurleen, and Karmjit Singh Sandha. "Stability- and Crosstalk-Based Performance of Multi- and Double-walled Mixed CNT Bundles as Interconnect for Next-Generation Technology Nodes." Journal of Circuits, Systems and Computers 31, no. 05 (November 10, 2021). http://dx.doi.org/10.1142/s0218126622500980.
Повний текст джерела"Two-Dimensional Chemical Delineation of Junction Profile with High Spatial Resolution and Application in Failure Analysis in 65 nm Technology Node." ECS Meeting Abstracts, 2009. http://dx.doi.org/10.1149/ma2009-02/22/1988.
Повний текст джерелаSmaani, Billel, Neha Paras, Shiromani Balmukund Rahi, Young Suh Song, Ramakant Yadav, and Shubham Tayal. "Impact of the Self-Heating Effect on Nanosheet Field Effect Transistor Performance." ECS Journal of Solid State Science and Technology, February 6, 2023. http://dx.doi.org/10.1149/2162-8777/acb96b.
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