Добірка наукової літератури з теми "22-nm technology node"
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Статті в журналах з теми "22-nm technology node"
Li, Zongru, Christopher Jarrett Elash, Chen Jin, Li Chen, Jiesi Xing, Zhiwu Yang, and Shuting Shi. "Comparison of Total Ionizing Dose Effects in 22-nm and 28-nm FD SOI Technologies." Electronics 11, no. 11 (June 1, 2022): 1757. http://dx.doi.org/10.3390/electronics11111757.
Повний текст джерелаXu, Peng, Yinghua Piao, Liang Ge, Cheng Hu, Lun Zhu, Zhiwei Zhu, David Wei Zhang, and Dongping Wu. "Investigation of Novel Junctionless MOSFETs for Technology Node Beyond 22 nm." ECS Transactions 44, no. 1 (December 15, 2019): 33–39. http://dx.doi.org/10.1149/1.3694293.
Повний текст джерелаHolmes, Steven. "22-nm-node technology active-layer patterning for planar transistor devices." Journal of Micro/Nanolithography, MEMS, and MOEMS 9, no. 1 (January 1, 2010): 013001. http://dx.doi.org/10.1117/1.3302125.
Повний текст джерелаBaklanov, Mikhail R., Evgeny A. Smirnov, and Larry Zhao. "Ultra Low Dielectric Constant Materials for 22 nm Technology Node and Beyond." ECS Transactions 35, no. 4 (December 16, 2019): 717–28. http://dx.doi.org/10.1149/1.3572315.
Повний текст джерелаSaxena, Shubhangi, and Kamsali Manjunathachari. "Novel Nanoelectronic Materials and Devices: For Future Technology Node." ECS Transactions 107, no. 1 (April 24, 2022): 15701–11. http://dx.doi.org/10.1149/10701.15701ecst.
Повний текст джерелаHuang, Zhengfeng, Yan Zhang, Wenhui Wu, Lanxi Duan, Huaguo Liang, Yiming Ouyang, Aibin Yan, and Tai Song. "A high-speed quadruple-node-upset-tolerant latch in 22 nm CMOS technology." Microelectronics Reliability 147 (August 2023): 115032. http://dx.doi.org/10.1016/j.microrel.2023.115032.
Повний текст джерелаLi, Zongru, Christopher Elash, Chen Jin, Li Chen, Shi-Jie Wen, Rita Fung, Jiesi Xing, Shuting Shi, Zhi Wu Yang, and Bharat L. Bhuva. "SEU performance of Schmitt-trigger-based flip-flops at the 22-nm FD SOI technology node." Microelectronics Reliability 146 (July 2023): 115033. http://dx.doi.org/10.1016/j.microrel.2023.115033.
Повний текст джерелаLu, Peng, Can Yang, Yifei Li, Bo Li, and Zhengsheng Han. "Three-Dimensional TID Hardening Design for 14 nm Node SOI FinFETs." Eng 2, no. 4 (December 3, 2021): 620–31. http://dx.doi.org/10.3390/eng2040039.
Повний текст джерелаChanghwan Shin, Min Hee Cho, Yasumasa Tsukamoto, Bich-Yen Nguyen, Carlos Mazuré, Borivoje Nikolić, and Tsu-Jae King Liu. "Performance and Area Scaling Benefits of FD-SOI Technology for 6-T SRAM Cells at the 22-nm Node." IEEE Transactions on Electron Devices 57, no. 6 (June 2010): 1301–9. http://dx.doi.org/10.1109/ted.2010.2046070.
Повний текст джерелаShin, Changhwan, Nattapol Damrongplasit, Xin Sun, Yasumasa Tsukamoto, Borivoje Nikolic, and Tsu-Jae King Liu. "Performance and Yield Benefits of Quasi-Planar Bulk CMOS Technology for 6-T SRAM at the 22-nm Node." IEEE Transactions on Electron Devices 58, no. 7 (July 2011): 1846–54. http://dx.doi.org/10.1109/ted.2011.2139213.
Повний текст джерелаДисертації з теми "22-nm technology node"
Bansal, Anil Kumar. "CMOS scaling considerations in sub 10-nm node multiple-gate FETS." Thesis, IIT Delhi, 2019. http://eprint.iitd.ac.in:80//handle/2074/8046.
Повний текст джерелаКниги з теми "22-nm technology node"
Wang, Guilei. Investigation on SiGe Selective Epitaxy for Source and Drain Engineering in 22 nm CMOS Technology Node and Beyond. Singapore: Springer Singapore, 2019. http://dx.doi.org/10.1007/978-981-15-0046-6.
Повний текст джерелаWang, Guilei. Investigation on Sige Selective Epitaxy for Source and Drain Engineering in 22 Nm CMOS Technology Node and Beyond. Springer Singapore Pte. Limited, 2020.
Знайти повний текст джерелаWang, Guilei. Investigation on SiGe Selective Epitaxy for Source and Drain Engineering in 22 nm CMOS Technology Node and Beyond. Springer, 2019.
Знайти повний текст джерелаBalasinski, Artur. Design for Manufacturability: From 1d to 4D for 90 22 NM Technology Nodes. Springer New York, 2016.
Знайти повний текст джерелаBalasinski, Artur. Design for Manufacturability: From 1D to 4D for 90–22 nm Technology Nodes. Springer, 2013.
Знайти повний текст джерелаBalasinski, Artur. Design for Manufacturability: From 1D to 4D for 90-22 Nm Technology Nodes. Springer London, Limited, 2013.
Знайти повний текст джерелаЧастини книг з теми "22-nm technology node"
Wang, Guilei. "Strained Silicon Technology." In Investigation on SiGe Selective Epitaxy for Source and Drain Engineering in 22 nm CMOS Technology Node and Beyond, 9–21. Singapore: Springer Singapore, 2019. http://dx.doi.org/10.1007/978-981-15-0046-6_2.
Повний текст джерелаKaur, Ravneet, Charu Madhu, and Deepti Singh. "Impact of Buried Oxide Layer Thickness on the Performance Parameters of SOI FinFET at 22 nm Node Technology." In Advances in Intelligent Systems and Computing, 537–44. Singapore: Springer Singapore, 2018. http://dx.doi.org/10.1007/978-981-10-5903-2_54.
Повний текст джерелаWang, Guilei. "Introduction." In Investigation on SiGe Selective Epitaxy for Source and Drain Engineering in 22 nm CMOS Technology Node and Beyond, 1–7. Singapore: Springer Singapore, 2019. http://dx.doi.org/10.1007/978-981-15-0046-6_1.
Повний текст джерелаWang, Guilei. "Epitaxial Growth of SiGe Thin Films." In Investigation on SiGe Selective Epitaxy for Source and Drain Engineering in 22 nm CMOS Technology Node and Beyond, 23–48. Singapore: Springer Singapore, 2019. http://dx.doi.org/10.1007/978-981-15-0046-6_3.
Повний текст джерелаWang, Guilei. "SiGe S/D Integration and Device Verification." In Investigation on SiGe Selective Epitaxy for Source and Drain Engineering in 22 nm CMOS Technology Node and Beyond, 49–92. Singapore: Springer Singapore, 2019. http://dx.doi.org/10.1007/978-981-15-0046-6_4.
Повний текст джерелаWang, Guilei. "Pattern Dependency of SiGe Layers Selective Epitaxy Growth." In Investigation on SiGe Selective Epitaxy for Source and Drain Engineering in 22 nm CMOS Technology Node and Beyond, 93–111. Singapore: Springer Singapore, 2019. http://dx.doi.org/10.1007/978-981-15-0046-6_5.
Повний текст джерелаWang, Guilei. "Conclusions and Prospects." In Investigation on SiGe Selective Epitaxy for Source and Drain Engineering in 22 nm CMOS Technology Node and Beyond, 113–15. Singapore: Springer Singapore, 2019. http://dx.doi.org/10.1007/978-981-15-0046-6_6.
Повний текст джерелаYin, Huaxiang, and Jiaxin Yao. "Advanced Transistor Process Technology from 22- to 14-nm Node." In Complementary Metal Oxide Semiconductor. InTech, 2018. http://dx.doi.org/10.5772/intechopen.78655.
Повний текст джерелаТези доповідей конференцій з теми "22-nm technology node"
Gambino, J. P. "Copper interconnect technology for the 22 nm node." In 2011 International Symposium on VLSI Technology, Systems and Application (VLSI-TSA). IEEE, 2011. http://dx.doi.org/10.1109/vtsa.2011.5872228.
Повний текст джерелаFinders, Jo, Mircea Dusa, Jan Mulkens, Yu Cao, and Maryana Escalante. "Solutions for 22-nm node patterning using ArFi technology." In SPIE Advanced Lithography. SPIE, 2011. http://dx.doi.org/10.1117/12.881598.
Повний текст джерелаKazuya Ohuchi, Christian Lavoie, Conal E. Murray, Chris P. D'Emic, Isaac Lauer, Jack O. Chu, Bin Yang, et al. "Extendibility of NiPt silicide to the 22-nm node CMOS technology." In 2008 International Workshop on Junction Technology (IWJT). IEEE, 2008. http://dx.doi.org/10.1109/iwjt.2008.4540037.
Повний текст джерелаKim, Ryoung-Han, Steven Holmes, Scott Halle, Vito Dai, Jason Meiring, Aasutosh Dave, Matthew E. Colburn, and Harry J. Levinson. "22 nm technology node active layer patterning for planar transistor devices." In SPIE Advanced Lithography, edited by Harry J. Levinson and Mircea V. Dusa. SPIE, 2009. http://dx.doi.org/10.1117/12.814277.
Повний текст джерелаZhou, Renjie, Gabriel Popescu, and Lynford L. Goddard. "Finding defects in a 22 nm node wafer with visible light." In CLEO: Applications and Technology. Washington, D.C.: OSA, 2013. http://dx.doi.org/10.1364/cleo_at.2013.af2j.2.
Повний текст джерелаAgarwal, Vivek Kumar, Manisha Guduri, and Aminul Islam. "Power and variability analysis of CMOS logic families @ 22-nm technology node." In 2014 3rd International Conference on Reliability, Infocom Technologies and Optimization (ICRITO) (Trends and Future Directions). IEEE, 2014. http://dx.doi.org/10.1109/icrito.2014.7014674.
Повний текст джерелаRoy, Chandaramauleshwar, and Aminul Islam. "Comparative analysis of various 9T SRAM cell at 22-nm technology node." In 2015 IEEE 2nd International Conference on Recent Trends in Information Systems (ReTIS). IEEE, 2015. http://dx.doi.org/10.1109/retis.2015.7232929.
Повний текст джерелаGallitre, M., L. G. Gosset, A. Farcy, B. Blampey, R. Gras, C. Bermond, B. Flechet, and J. Torres. "Performance predictions of prospective air gap architectures for the 22 nm node." In 2007 IEEE International Interconnect Technology Conferencee. IEEE, 2007. http://dx.doi.org/10.1109/iitc.2007.382374.
Повний текст джерелаLu, Hai-Jin, Zong-Yan Pan, Pei-Yu Chen, Zhi-Cheng Zhang, and Ming-Zhi Chen. "Optimization of contact W related processes for 28/22 nm HKMG technology node." In 2021 5th IEEE Electron Devices Technology & Manufacturing Conference (EDTM). IEEE, 2021. http://dx.doi.org/10.1109/edtm50988.2021.9420977.
Повний текст джерелаColombeau, B., T. Thanigaivelan, E. Arevalo, T. Toh, R. Miura, and H. Ito. "Ultra-shallow Carborane molecular implant for 22-nm node p-MOSFET performance boost." In 2009 International Workshop on Junction Technology (IWJT). IEEE, 2009. http://dx.doi.org/10.1109/iwjt.2009.5166211.
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