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Автор: Grafiati

Опубліковано: 11 вересня 2023

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Статті в журналах з теми "10T SRAM CELL"

Elangovan, M., and K. Gunavathi. "High Stable and Low Power 10T CNTFET SRAM Cell." Journal of Circuits, Systems and Computers 29, no. 10 (December 19, 2019): 2050158. http://dx.doi.org/10.1142/s0218126620501583.

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Анотація:

The ultimate aim of a memory designer is to design a memory cell which could consume low power with high data stability in the deep nanoscale range. The implementation of Very Large-Scale Integration (VLSI) circuits using MOSFETs in nanoscale range faces many issues such as increasing of leakage power and second-order effects that are easily affected by the PVT variation. Hence, it is essential to find the best alternative of MOSFET for deep submicron design. The Carbon Nanotube Field Effect Transistor (CNTFET) can eradicate all the demerits of MOSFET and be the best replacement of MOSFET for nanoscale range design. In this paper, a 10T CNTFET Static Random Access Memory (SRAM) cell is proposed. The power consumption and Static Noise Margin (SNM) are analyzed. The power consumption and stable performance of the proposed 10T CNTFET SRAM cell are compared with that of conventional 10T CNTFET SRAM cell. The power and stability analyses of the proposed 10T and conventional 10T CNTFET SRAM cells are carried out for the CNTFET parameters such as pitch and chiral vector ([Formula: see text]). The power and SNM analyses are carried out for [Formula: see text]20% variation of oxide thickness (Hox), different dielectric constant (Kox). The supply voltage varies from 0.9[Formula: see text]V to 0.6[Formula: see text]V and temperature varies from 27∘C to 125∘C. The simulation results show that the proposed 10T CNTFET SRAM cell consumes lesser power than conventional 10T CNTFET SRAM cell during the write, hold and read modes. The write, hold and read stability of the proposed 10T CNTFET SRAM cell are higher as compared with that of conventional 10T CNTFET SRAM. The conventional and proposed 10T SRAM cells are also implemented using MOSFET. The stability and power performance of proposed 10T SRAM cell is also as good as conventional 10T SRAM for MOSFET implementation. The proposed 10T SRAM cell consumes lesser power and gives higher stability than conventional 10T SRAM cell in both CNTFET and MOSFET implementation. The simulation is carried out using Stanford University 32[Formula: see text]nm CNTFET model in HSPICE simulation tool.

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Reddy Gujjula, Nagarjuna, and Rameshbabu Kellampalli. "Design and implementation of 10T-SRAM cell using Carbon Nano Tube Field Effect Transistor." International Journal of Scientific Methods in Engineering and Management 01, no. 01 (2023): 47–57. http://dx.doi.org/10.58599/ijsmem.2023.1105.

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Анотація:

SRAM is a key component in many VLSI circuits for efficient storage data. Various researches have been performed on implementation of SRAM using Conventional CMOS, FinFET and GNRFET technologies. But, these methodologies generating the more number of faults with high power and delay consumption, tosolve this problem proposed10T SRAM cell is implemented with the CNTFET respectively. Present research involving CNTFET SRAM deals with leakage analysis and dealt with the dual hilarity characteristics. Fault introduction and analysis of faults were limited with CMOS SRAM. The detection algorithms and circuits possess limitations in terms of detecting the current at nanoscales and restricted with CMOS SRAM. These limitations made us to pursue the research in these areas to bring novel ideas. The performance metrics evaluated and experimental analysis is made and it helps us to choose between various SRAMS. The simulation results shows that the proposed 10T SRAM consumes less delay and power compared to the 7T SRAM cell.

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Ganesh, Chokkakula, and Fazal Noorbasha. "Performance and Stability Analysis of Built-In Self-Read and Write Assist 10T SRAM Cell." Active and Passive Electronic Components 2023 (June 30, 2023): 1–17. http://dx.doi.org/10.1155/2023/3371599.

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This work presents the performance and stability analysis of the proposed built-in self-read and write assist 10T SRAM (BSRWA 10T) for better performance in terms of thermal stability and fast write access, which is suitable for military and aerospace applications. The performance of the proposed SRAM cell dominates the previous SRAM cells, i.e., conventional, fully differential 10T-ST (FD 10T-ST), single stacked disturbance-free 9T-ST (SSDF 9T-ST). The proposed SRAM cell dominates the SSDF 9T-ST SRAM cell in terms of write ability. The built-in self-read and write assist structure of the memory cell also dominates the improved write ability of SSDF 9T-ST SRAM by assist circuits such as negative bit line, ultra-dynamic voltage scaling (UDVS), write assist combining negative BL, and VDD collapse. The impact of assist circuits on write performance of memory cells is observed using Monte Carlo simulation for write margin (WM) parameter. WM of SSDF 9T-ST SRAM is improved by 15% and 25% by adding UDVS assist circuit and write assist combining negative BL and VDD collapse circuit. But BSRWA SRAM cell itself can improve WM by 32% without any assist circuit. The impact of temperature variation on the performance of memory cells is observed using Monte Carlo simulation for the HSNM parameter. The deviation of HSNM for 15°C to 55°C is 14%, 5%, 4%, and 1% in conventional SRAM cell, FD 10T SRAM cell, SSDF 9T SRAM cell, and proposed BSRWA 10T SRAM cell, respectively. The proposed SRAM cell is designed at a 22 nm CMOS technology node and verified in the Synopsys Custom compiler. MC simulation results are monitored on Synopsys Cosmo-scope wave viewer.

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Rao, M. V. Nageswara, Mamidipaka Hema, Ramakrishna Raghutu, Ramakrishna S. S. Nuvvula, Polamarasetty P. Kumar, Ilhami Colak, and Baseem Khan. "Design and Development of Efficient SRAM Cell Based on FinFET for Low Power Memory Applications." Journal of Electrical and Computer Engineering 2023 (June 7, 2023): 1–13. http://dx.doi.org/10.1155/2023/7069746.

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Анотація:

Stationary random-access memory (SRAM) undergoes an expansion stage, to repel advanced process variation and support ultra-low power operation. Memories occupy more than 80% of the surface in today’s microdevices, and this trend is expected to continue. Metal oxide semiconductor field effect transistor (MOSFET) face a set of difficulties, that results in higher leakage current (Ileakage) at lower strategy collisions. Fin field effect transistor (FinFET) is a highly effective substitute to complementary metal oxide semiconductor (CMOS) under the 45 nm variant due to advanced stability. Memory cells are significant in the large-scale computation system. SRAM is the most commonly used memory type; SRAMs are thought to utilize more than 60% of the chip area. The proposed SRAM cell is developed with FinFETs at 16 nm knot. Power, delay, power delay product (PDP), Ileakage, and stationary noise margin (SNM) are compared with traditional 6T SRAM cells. The designed cell decreases leakage power, current, and read access time. While comparing 6T SRAM and earlier low power SRAM cells, FinFET-based 10T SRAM provides significant SNM with reduced access time. The proposed 10T SRAM based on FinFET provides an 80.80% PDP reduction in write mode and a 50.65% PDP reduction in read mode compared to MOSEFET models. There is an improvement of 22.20% in terms of SNM and 25.53% in terms of Ileakage.

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Islam, A., and M. Hasan. "Leakage Characterization of 10T SRAM Cell." IEEE Transactions on Electron Devices 59, no. 3 (March 2012): 631–38. http://dx.doi.org/10.1109/ted.2011.2181387.

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Chaurasia, Ranu, Brijesh Kumar, Sudhanshu Verma, and Akhilesh Kumar. "Design and Performance Improvement of 10T SRAM Using Sleepy Keeper and Drain Gating Techniques." IOP Conference Series: Materials Science and Engineering 1272, no. 1 (December 1, 2022): 012007. http://dx.doi.org/10.1088/1757-899x/1272/1/012007.

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This paper presents the sleepy keeper and drain gating technique to improve the performance of 10T SRAM cell. The behavior of 10T SRAM cell is evaluated using benchmarked industry standard GPDK 45nm Technology Node of the Cadence Virtuoso EDA tool. The performance is analyzed in terms of dynamic and static parameters of 10T SRAM cell and compared with 6T SRAM, where find the reduction in dynamic power and static power dissipation. Besides this, observed the reduction in leakage current using sleepy keeper and drain gating technique. The proposed modified topology applicable in single-ended write and differential read operation. The read delay product and the write delay product is decreased by 36.7 % and 67.5 %, respectively. The major goal of the suggested architecture is to provide the improved stability, reduction in delay, as well as reduction in leakage current.

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Liu, Changjun, Hongxia Liu, and Jianye Yang. "A Novel Low-Power and Soft Error Recovery 10T SRAM Cell." Micromachines 14, no. 4 (April 13, 2023): 845. http://dx.doi.org/10.3390/mi14040845.

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In SRAM cells, as the size of transistors and the distance between transistors decrease rapidly, the critical charge of the sensitive node decreases, making SRAM cells more susceptible to soft errors. If radiation particles hit the sensitive nodes of a standard 6T SRAM cell, the data stored in the cell are flipped, resulting in a single event upset. Therefore, this paper proposes a low-power SRAM cell, called PP10T, for soft error recovery. To verify the performance of PP10T, the proposed cell is simulated by the 22 nm FDSOI process, and compared with the standard 6T cell and several 10T SRAM cells, such as Quatro-10T, PS10T, NS10T, and RHBD10T. The simulation results show that all of the sensitive nodes of PP10T can recover their data, even when S0 and S1 nodes flip at the same time. PP10T is also immune to read interference, because the change of the ‘0’ storage node, directly accessed by the bit line during the read operation, does not affect other nodes. In addition, PP10T consumes very low-holding power due to the smaller leakage current of the circuit.

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Zhou, Hong Gang, Qiang Song, Chun Yu Peng, and Shou Biao Tan. "A New 10T SRAM Cell with Improved Read/Write Margin and No Half Select Disturb for Bit-Interleaving Architecture." Applied Mechanics and Materials 263-266 (December 2012): 9–14. http://dx.doi.org/10.4028/www.scientific.net/amm.263-266.9.

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A new 10T SRAM cell is proposed in this paper for simultaneously addressing the half select problem and improving the read/write stability. Without the half select condition, the proposed 10T cell allows efficient bit-interleaving to provide soft error rate protection and the dynamic power is also decreased significantly due to the reduction in the number of bitlines discharged and charged during the read and write operation. In the new 10T SRAM cell, one side of the cross-coupled inverters cuts off the pull up path or pull down path through adding two gated transistors according to the write ‘0’ or ‘1’ operation. It brings a great improvement for write stability without considering the half select disturb during the write operation. The simulation results indicate that the RSNM and WM of the proposed SRAM cell are enhanced by 130% and 58%, respectively, as compared to the conventional 6T SRAM cell in SMIC 65nm CMOS technology.

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Singh, Arjun, and Sangeeta Nakhte. "Optimized High Performance 10T SRAM Cell Characterization." International Journal of Computer Applications 134, no. 5 (January 15, 2016): 29–33. http://dx.doi.org/10.5120/ijca2016907964.

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Gupta, Neha, Ambika Prasad Shah, Sajid Khan, Santosh Kumar Vishvakarma, Michael Waltl, and Patrick Girard. "Error-Tolerant Reconfigurable VDD 10T SRAM Architecture for IoT Applications." Electronics 10, no. 14 (July 17, 2021): 1718. http://dx.doi.org/10.3390/electronics10141718.

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Анотація:

This paper proposes an error-tolerant reconfigurable VDD (R-VDD) scaled SRAM architecture, which significantly reduces the read and hold power using the supply voltage scaling technique. The data-dependent low-power 10T (D2LP10T) SRAM cell is used for the R-VDD scaled architecture with the improved stability and lower power consumption. The R-VDD scaled SRAM architecture is developed to avoid unessential read and hold power using VDD scaling. In this work, the cells are implemented and analyzed considering a technologically relevant 65 nm CMOS node. We analyze the failure probability during read, write, and hold mode, which shows that the proposed D2LP10T cell exhibits the lowest failure rate compared to other existing cells. Furthermore, the D2LP10T cell design offers 1.66×, 4.0×, and 1.15× higher write, read, and hold stability, respectively, as compared to the 6T cell. Moreover, leakage power, write power-delay-product (PDP), and read PDP has been reduced by 89.96%, 80.52%, and 59.80%, respectively, compared to the 6T SRAM cell at 0.4 V supply voltage. The functional improvement becomes even more apparent when the quality factor (QF) is evaluated, which is 458× higher for the proposed design than the 6T SRAM cell at 0.4 V supply voltage. A significant improvement of power dissipation, i.e., 46.07% and 74.55%, can also be observed for the R-VDD scaled architecture compared to the conventional array for the respective read and hold operation at 0.4 V supply voltage.

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Більше джерел

Дисертації з теми "10T SRAM CELL"

Lo, Cheng-Hung, and 羅正鴻. "A PPN Based 10T Sub-threshold SRAM Cell with Low Leakage and Differential Sensing." Thesis, 2009. http://ndltd.ncl.edu.tw/handle/39470329821328407138.

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Анотація:

碩士
國立清華大學
電機工程學系
98
In this thesis, we propose a P-P-N inverter based differential 10T SRAM cell capable of providing low power operation. Since cell stability is especially vulnerable to noise at sub-threshold voltage, the proposed cell avoids read disturb, improving cell stability significantly. Without cell stability concern, we strengthen the access transistors to ensure cell writability by employing reverse short channel effect. As transistor leakage becomes more prominent in nanometer technology, we introduce VGND biasing scheme to reduce the impact of data-dependent leakage current. Without complicate wordline control, the proposed cell allows multi-word on a wordline to increase cell density and to enable efficient error correction code (ECC). To verify the proposed cell, a 16Kb array of the proposed cell is fabricated in 90nm CMOS technology. For comparison, we also fabricate 2Kb array of previous work in our chip. Supply voltage for array and peripheral is separated to enable periphery voltage boosting and to measure the cell array leakage. Applying higher peripheral voltage not only enhances the chip operating speed but also resolve the operating limitation at low voltage while the cell array still operates at lower voltage, reducing leakage power significantly. Measurement results show the 16Kb array of the proposed cell can work successfully down to 285mV. By boosting periphery voltage to 0.4V, the proposed cell can work at a lower (265mV) voltage and operate at a higher frequency. The entire 16Kb array consumes 2.6uW leakage power at 300mV. After normalization, our cell consumes only 0.2X leakage current compared to previous work.

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YADAV, PUNEET. "DESIGN AND ANALYSIS OF A LOW POWER AND HIGH PERFORMANCE 10T SRAM CELL AT 32 NM TECHNOLOGY NODE." Thesis, 2023. http://dspace.dtu.ac.in:8080/jspui/handle/repository/19835.

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Memory is known to be one of the most crucial parts of any electronic system. However, a class of memory called the cache memory is even more crucial among the type of memories since it is the one working closely in synchronization with the central processing unit. There are millions of SRAM cells inside cache memory. SRAM cells must therefore possess a few essential attributes for cache memory to be reliable, including low dynamic and static power consumption, high data stability, and low read latency. A comprehensive review of the design and analysis of SRAM cells are performed, focusing on the fundamental building block, the SRAM cell, and its critical performance parameters. The aim is to provide a concise overview of the key concepts and challenges involved in SRAM cell design, highlighting recent advancements and future directions. The review begins with an introduction to SRAM and its significance in various applications. It explores the basic structure and operation of an SRAM cell, emphasizing the importance of stability, read and write capabilities, and power consumption. The different SRAM cell topologies are discussed, along with their advantages and trade-offs. The critical design considerations of SRAM cells, including noise immunity, process variations, and leakage current. Various techniques for improving the stability of SRAM cells, such as the use of feedback and assist circuits, are examined. Moreover, the impact of scaling technologies, such as process technology nodes and transistor scaling, on SRAM cell performance is explored. Additionally, the analysis of SRAM cell performance metrics, including read and write access times, write margin, stability, and power dissipation have been studied. The influence of key parameters, such as supply voltage, transistor sizing, and load capacitance, on these metrics is discussed. Furthermore, the impact of process variations on yield and reliability is addressed, along with reliability-enhancement techniques. To successfully incorporate these qualities, a comparative analysis of different 10T and 11T SRAM cells has been performed. The performance of the conventional TG10T and 11T SRAM models are compared to the 10T SRAM to showcase enhancements obtained. TG10T SRAM cell deploys two transmission gates instead of two NMOS access vi transistors to strengthen writing ability. It also employs two additional buffer transistors so that read stability can be enhanced. The TG10T SRAM cell is proven to be more enhanced in almost every aspect but it consumes more power. The read SNM and write SNM are found to be the largest in the TG10T SRAM cell. The power dissipated by the TG10T cell (i.e., 233.69nW) is approximately two times as compared to the 10T SRAM cell (i.e., 108.65nW) and 11T SRAM cell (i.e., 88.491nW). The analysis also shows that both read and write delay is minimal in TG10T SRAM cells. The read delay is 343.3 psec and the write delay is 494 psec respectively. A 10T SRAM cell has been proposed and comparison between of different existing 10T and 11T SRAM cells has been performed. The power consumption and read-write behaviors of all the SRAM cells are studied. The power consumed by the TG10T cell (i.e., 233.69nW) is approximately two times in contrast to the 10T SRAM cell (i.e., 108.65nW) and five times when collated to the proposed 10T SRAM cell (i.e., 44.794nW). The analysis associated depicts that the read and write delay is minimum in the proposed 10T SRAM (i.e., 97.7psec & 154.3psec) respectively. All simulations are carried out using LTSPICE software operating at 0.5 Volt in 32 nm CMOS process technology. The proposed transmission gate based 10T SRAM cell consumes minimum power and has better overall read stability as compared to the other designs. The review concludes by highlighting emerging trends and challenges in SRAM cell design, including the exploration of novel device architectures, non-volatile SRAM, and low power designs for energy-efficient computing systems. It emphasizes the need for continued research and innovation to address the increasing demands for higher density, lower power consumption, and improved reliability in future SRAM cell designs. A comprehensive overview of the design and analysis of SRAM cells serves as a valuable resource for researchers, engineers, and students working in the field of digital integrated circuit design, offering insights into the current state of SRAM cell technology and potential future directions.

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Частини книг з теми "10T SRAM CELL"

Gupta, Vinay, Pratiksha Shukla, and Manisha Pattanaik. "Low Leakage Noise Tolerant 10T SRAM Cell." In Communications in Computer and Information Science, 538–50. Singapore: Springer Singapore, 2019. http://dx.doi.org/10.1007/978-981-13-5950-7_45.

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Sharma, Deepika, Shilpi Birla, and Neha Mathur. "Comparative Analysis of 10T SRAM Cell using Nanodevices." In Intelligent Computing Techniques for Smart Energy Systems, 133–41. Singapore: Springer Nature Singapore, 2022. http://dx.doi.org/10.1007/978-981-19-0252-9_13.

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Manoj Kumar, R., and P. V. Sridevi. "Design of Low Standby Power 10T SRAM Cell with Improved Write Margin." In Lecture Notes in Electrical Engineering, 507–14. Singapore: Springer Singapore, 2020. http://dx.doi.org/10.1007/978-981-15-3828-5_53.

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Singh, Anushka, Yash Sharma, Arvind Sharma, and Archana Pandey. "A Novel 20nm FinFET Based 10T SRAM Cell Design for Improved Performance." In Communications in Computer and Information Science, 523–31. Singapore: Springer Singapore, 2019. http://dx.doi.org/10.1007/978-981-32-9767-8_43.

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Aakansha, G. S. Namith, A. Dinesh, A. Sai Ram, Shashank Kumar Dubey, and Aminul Islam. "A Highly Reliable and Radiation-Hardened Majority PFET-Based 10T SRAM Cell." In Lecture Notes in Electrical Engineering, 113–22. Singapore: Springer Singapore, 2021. http://dx.doi.org/10.1007/978-981-16-1570-2_11.

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Joshi, Vinod Kumar, and Haniel Craig Lobo. "Comparative Study of 7T, 8T, 9T and 10T SRAM with Conventional 6T SRAM Cell Using 180 nm Technology." In Advanced Computing and Communication Technologies, 25–40. Singapore: Springer Singapore, 2016. http://dx.doi.org/10.1007/978-981-10-1023-1_3.

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Singh, Kamini, R. S. Gamad, and P. P. Bansod. "Design and Analysis for Power Reduction with High SNM of 10T SRAM Cell." In Communications in Computer and Information Science, 541–49. Singapore: Springer Singapore, 2019. http://dx.doi.org/10.1007/978-981-32-9767-8_45.

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Yadav, Vaishali, and V. K. Tomar. "A Low Leakage with Enhanced Write Margin 10T SRAM Cell for IoT Applications." In Lecture Notes in Electrical Engineering, 201–11. Singapore: Springer Singapore, 2021. http://dx.doi.org/10.1007/978-981-16-3767-4_19.

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Swaati and Bishnu Prasad Das. "A 10T Subthreshold SRAM Cell with Minimal Bitline Switching for Ultra-Low Power Applications." In Communications in Computer and Information Science, 487–95. Singapore: Springer Singapore, 2017. http://dx.doi.org/10.1007/978-981-10-7470-7_48.

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Ahlawat, Siddhant, Siddharth, Bhawna Rawat, and Poornima Mittal. "A Comparative Performance Analysis of Varied 10T SRAM Cell Topologies at 32 nm Technology Node." In Modeling, Simulation and Optimization, 63–75. Singapore: Springer Nature Singapore, 2022. http://dx.doi.org/10.1007/978-981-19-0836-1_5.

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Тези доповідей конференцій з теми "10T SRAM CELL"

Kaur, Navneet, Neha Gupta, Hitesh Pahuja, Balwinder Singh, and Sudhakar Panday. "Low Power FinFET based 10T SRAM cell." In 2016 Second International Innovative Applications of Computational Intelligence on Power, Energy and Controls with their Impact on Humanity (CIPECH). IEEE, 2016. http://dx.doi.org/10.1109/cipech.2016.7918772.

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Prasad, Govind. "Novel low power 10T SRAM cell on 90nm CMOS." In 2016 2nd International Conference on Advances in Electrical, Electronics, Information, Communication and Bio-Informatics (AEEICB). IEEE, 2016. http://dx.doi.org/10.1109/aeeicb.2016.7538408.

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Bansal, Manav, Ankur Kumar, Priyanka Singh, and R. K. Nagaria. "A Novel 10T SRAM cell for Low Power Applications." In 2018 5th IEEE Uttar Pradesh Section International Conference on Electrical, Electronics and Computer Engineering (UPCON). IEEE, 2018. http://dx.doi.org/10.1109/upcon.2018.8596829.

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Upadhyay, Prashant, Rajib Kar, Durbadal Mandal, and Sakti P. Ghoshal. "A novel 10T SRAM cell for low power circuits." In 2014 International Conference on Communications and Signal Processing (ICCSP). IEEE, 2014. http://dx.doi.org/10.1109/iccsp.2014.6949770.

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Mansore, S. R., and Amit Naik. "A Highly Stable 10T SRAM Cell for Low Power Applications." In 2022 OPJU International Technology Conference on Emerging Technologies for Sustainable Development (OTCON). IEEE, 2023. http://dx.doi.org/10.1109/otcon56053.2023.10113962.

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Sharma, Deepika, and Shilpi Birla. "Design and Analysis of 10T SRAM Cell with Stability Characterizations." In 2021 International Conference on Advances in Electrical, Computing, Communication and Sustainable Technologies (ICAECT). IEEE, 2021. http://dx.doi.org/10.1109/icaect49130.2021.9392517.

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Ahmad, Sayeed, Naushad Alam, and Mohd Hasan. "Radiation Hardened Area-Efficient 10T SRAM Cell for Space Applications." In 2021 25th International Symposium on VLSI Design and Test (VDAT). IEEE, 2021. http://dx.doi.org/10.1109/vdat53777.2021.9601130.

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Grace, P. Shiny, and N. M. Sivamangai. "Design of 10T SRAM cell for high SNM and low power." In 2016 3rd International Conference on Devices, Circuits and Systems (ICDCS). IEEE, 2016. http://dx.doi.org/10.1109/icdcsyst.2016.7570609.

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Kumar, Mukku Pavan, Rohit Lorenzo, Junjurampalli Khaja, and Avtar Singh. "A Highly Stable PNN-PPN-10T SRAM Cell With Improved Reliability." In 2023 3rd International conference on Artificial Intelligence and Signal Processing (AISP). IEEE, 2023. http://dx.doi.org/10.1109/aisp57993.2023.10135013.

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Zhang, Jiubai, Xiaoqing Wu, Xilin Yi, Jiaxun Lv, and Yajuan He. "A Subthreshold 10T SRAM Cell with Enhanced Read and Write Operations." In 2019 IEEE International Symposium on Circuits and Systems (ISCAS). IEEE, 2019. http://dx.doi.org/10.1109/iscas.2019.8702371.

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