Artigos de revistas sobre o tema "Triple gate transistor"
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Grossl Bade, Tamiris, Hassan Hamad, Adrien Lambert, Hervé Morel e Dominique Planson. "Threshold Voltage Measurement Protocol “Triple Sense” Applied to GaN HEMTs". Electronics 12, n.º 11 (3 de junho de 2023): 2529. http://dx.doi.org/10.3390/electronics12112529.
Texto completo da fonteCho, Seong-Kun, e Won-Ju Cho. "Highly Sensitive and Transparent Urea-EnFET Based Point-of-Care Diagnostic Test Sensor with a Triple-Gate a-IGZO TFT". Sensors 21, n.º 14 (12 de julho de 2021): 4748. http://dx.doi.org/10.3390/s21144748.
Texto completo da fonteConde, Jorge E., Antonio Cereira e M. Estrada. "Distortion Analysis of Triple-Gate Transistor in Saturation". ECS Transactions 9, n.º 1 (19 de dezembro de 2019): 67–73. http://dx.doi.org/10.1149/1.2766875.
Texto completo da fonteGay, R., V. Della Marca, H. Aziza, P. Laine, A. Regnier, S. Niel e A. Marzaki. "Gate stress reliability of a novel trench-based Triple Gate Transistor". Microelectronics Reliability 126 (novembro de 2021): 114233. http://dx.doi.org/10.1016/j.microrel.2021.114233.
Texto completo da fonteSHAHHOSEINI, ALI, KAMYAR SAGHAFI, MOHAMMAD KAZEM MORAVVEJ-FARSHI e RAHIM FAEZ. "TRIPLE-TUNNEL JUNCTION SINGLE ELECTRON TRANSISTOR (TTJ-SET)". Modern Physics Letters B 25, n.º 17 (10 de julho de 2011): 1487–501. http://dx.doi.org/10.1142/s0217984911026346.
Texto completo da fontePandey, Neeta, Kirti Gupta e Bharat Choudhary. "New Proposal for MCML Based Three-Input Logic Implementation". VLSI Design 2016 (19 de setembro de 2016): 1–10. http://dx.doi.org/10.1155/2016/8712768.
Texto completo da fonteManikandan, S., P. Suveetha Dhanaselvam e M. Karthigai Pandian. "A Quasi 2-D Electrostatic Potential and Threshold Voltage Model for Junctionless Triple Material Cylindrical Surrounding Gate Si Nanowire Transistor". Journal of Nanoelectronics and Optoelectronics 16, n.º 2 (1 de fevereiro de 2021): 318–23. http://dx.doi.org/10.1166/jno.2021.2951.
Texto completo da fontede Araujo, Gustavo Vinicius, Joao Martino e Paula Agopian. "Operational Transconductance Amplifier Designed with Experimental Omega-Gate Nanowire SOI MOSFETs". ECS Meeting Abstracts MA2023-01, n.º 33 (28 de agosto de 2023): 1861. http://dx.doi.org/10.1149/ma2023-01331861mtgabs.
Texto completo da fonteMüller, M. R., A. Gumprich, F. Schütte, K. Kallis, U. Künzelmann, S. Engels, C. Stampfer, N. Wilck e J. Knoch. "Buried triple-gate structures for advanced field-effect transistor devices". Microelectronic Engineering 119 (maio de 2014): 95–99. http://dx.doi.org/10.1016/j.mee.2014.02.001.
Texto completo da fonteFui, Tan Chun, Ajay Kumar Singh e Lim Way Soong. "Performance Characterization of Dual-Metal Triple- Gate-Dielectric (DM_TGD) Tunnel Field Effect Transistor (TFET)". International Journal of Robotics and Automation Technology 8 (31 de dezembro de 2021): 83–89. http://dx.doi.org/10.31875/2409-9694.2021.08.8.
Texto completo da fonteDarwin, S., e T. S. Arun Samuel. "Mathematical Modeling of Junctionless Triple Material Double Gate MOSFET for Low Power Applications". Journal of Nano Research 56 (fevereiro de 2019): 71–79. http://dx.doi.org/10.4028/www.scientific.net/jnanor.56.71.
Texto completo da fonteGowthami, Yadala, Bukya Balaji e Karumuri Srinivasa Rao. "Design and performance analysis of front and back Pi 6 nm gate with high K dielectric passivated high electron mobility transistor". International Journal of Electrical and Computer Engineering (IJECE) 13, n.º 4 (1 de agosto de 2023): 3788. http://dx.doi.org/10.11591/ijece.v13i4.pp3788-3795.
Texto completo da fonteGay, R., V. Della Marca, H. Aziza, M. Mantelli, F. Trenteseaux, F. La Rosa, A. Regnier, S. Niel e A. Marzaki. "A Novel Trench-Based Triple Gate Transistor With Enhanced Driving Capability". IEEE Electron Device Letters 42, n.º 6 (junho de 2021): 832–34. http://dx.doi.org/10.1109/led.2021.3076609.
Texto completo da fonteLim, Sang Woo, e Brian Winstead. "Surface Preparation for Transistor Performance Improvement in Triple Gate Oxide Integration". Journal of The Electrochemical Society 152, n.º 9 (2005): G714. http://dx.doi.org/10.1149/1.1973245.
Texto completo da fonteMolaei Imen Abadi, Rouzbeh, e Seyed Ali Sedigh Ziabari. "A Comparative Numerical Study of Junctionless and p-i-n Tunneling Carbon Nanotube Field Effect Transistor". Journal of Nano Research 45 (janeiro de 2017): 55–75. http://dx.doi.org/10.4028/www.scientific.net/jnanor.45.55.
Texto completo da fonteZakarya, Kourdi, e Abdelkhader Hamdoun. "A modeling and performance of the triple field plate HEMT". International Journal of Power Electronics and Drive Systems (IJPEDS) 10, n.º 1 (1 de março de 2019): 398. http://dx.doi.org/10.11591/ijpeds.v10.i1.pp398-405.
Texto completo da fonteGowthami, Y., B.Balaji e K. Srinivasa Rao. "Qualitative Analysis & Advancement of Asymmetric Recessed Gates with Dual Floating Material GaN HEMT for Quantum Electronics". Journal of Integrated Circuits and Systems 18, n.º 1 (22 de maio de 2023): 1–8. http://dx.doi.org/10.29292/jics.v18i1.657.
Texto completo da fonteDubey, Shashank Kumar, e Aminul Islam. "Al0.30Ga0.70N /GaN MODFET with triple-teeth metal for RF and high-power applications". Physica Scripta 97, n.º 3 (10 de fevereiro de 2022): 034003. http://dx.doi.org/10.1088/1402-4896/ac50c3.
Texto completo da fonteSamuel, T. S. Arun, e S. Komalavalli. "Analytical Modelling and Simulation of Triple Material Quadruple Gate Tunnel Field Effect Transistors". Journal of Nano Research 54 (agosto de 2018): 146–57. http://dx.doi.org/10.4028/www.scientific.net/jnanor.54.146.
Texto completo da fontePizzanelli, Riccardo, Rhaycen Prates, Marcelo Antonio Pavanello e Michelly de Souza. "(Digital Presentation) Comparison of Width and Temperature Influence on DIBL Effect in Junctionless and Inversion Mode Nanowire MOSFETs". ECS Meeting Abstracts MA2023-01, n.º 33 (28 de agosto de 2023): 1872. http://dx.doi.org/10.1149/ma2023-01331872mtgabs.
Texto completo da fonteLiu, Fayong, Kouta Ibukuro, Muhammad Khaled Husain, Zuo Li, Joseph Hillier, Isao Tomita, Yoshishige Tsuchiya, Harvey Rutt e Shinichi Saito. "Manipulation of random telegraph signals in a silicon nanowire transistor with a triple gate". Nanotechnology 29, n.º 47 (25 de setembro de 2018): 475201. http://dx.doi.org/10.1088/1361-6528/aadfa6.
Texto completo da fonteEt.al, R. Jeyarohini. "A performance Analysis of DM-DG and TM-DG TFETs Analytical Models for Low Power Applications". Turkish Journal of Computer and Mathematics Education (TURCOMAT) 12, n.º 3 (10 de abril de 2021): 4642–51. http://dx.doi.org/10.17762/turcomat.v12i3.1874.
Texto completo da fonteVenkatesh, M., e N. B. Balamurugan. "New subthreshold performance analysis of germanium based dual halo gate stacked triple material surrounding gate tunnel field effect transistor". Superlattices and Microstructures 130 (junho de 2019): 485–98. http://dx.doi.org/10.1016/j.spmi.2019.05.016.
Texto completo da fonteLima, Vitor Gonçalves, Guilherme Paim, Rodrigo Wuerdig, Leandro Mateus Giacomini Rocha, Leomar Da Rosa Júnior, Felipe Marques, Vinicius Valduga, Eduardo Costa, Rafael Soares e Sergio Bampi. "Enhancing Side Channel Attack-Resistance of the STTL Combining Multi-Vt Transistors with Capacitance and Current Paths Counterbalancing". Journal of Integrated Circuits and Systems 15, n.º 1 (26 de maio de 2020): 1–11. http://dx.doi.org/10.29292/jics.v15i1.100.
Texto completo da fonteKumar, A., A. Chaudhry, V. Kumar e V. Sharma. "A Two Dimensional Surface Potential Model for Triple Material Double Gate Junctionless Field Effect Transistor". Journal of Nano- and Electronic Physics 8, n.º 4(1) (2016): 04042–1. http://dx.doi.org/10.21272/jnep.8(4(1)).04042.
Texto completo da fonteChien, Feng-Tso, Zhi-Zhe Wang, Cheng-Li Lin, Tsung-Kuei Kang, Chii-Wen Chen e Hsien-Chin Chiu. "150–200 V Split-Gate Trench Power MOSFETs with Multiple Epitaxial Layers". Micromachines 11, n.º 5 (15 de maio de 2020): 504. http://dx.doi.org/10.3390/mi11050504.
Texto completo da fonteKoide, Yasuo. "(Invited) Leading-Edge Diamond FET, MEMS, and Photodetector Devices". ECS Meeting Abstracts MA2023-02, n.º 30 (22 de dezembro de 2023): 1541. http://dx.doi.org/10.1149/ma2023-02301541mtgabs.
Texto completo da fonteKashem, Md Tashfiq Bin, e Samia Subrina. "Computational Analysis of Joule Heating Effect in Triple Material Gate AlGaN/GaN High Electron Mobility Transistor". ECS Transactions 102, n.º 3 (7 de maio de 2021): 43–52. http://dx.doi.org/10.1149/10203.0043ecst.
Texto completo da fonteChawla, Tulika, Mamta Khosla e Balwinder Raj. "Design and simulation of triple metal double-gate germanium on insulator vertical tunnel field effect transistor". Microelectronics Journal 114 (agosto de 2021): 105125. http://dx.doi.org/10.1016/j.mejo.2021.105125.
Texto completo da fonteKashem, Md Tashfiq Bin, e Samia Subrina. "Computational Analysis of Joule Heating Effect in Triple Material Gate AlGaN/GaN High Electron Mobility Transistor". ECS Meeting Abstracts MA2021-01, n.º 33 (30 de maio de 2021): 1074. http://dx.doi.org/10.1149/ma2021-01331074mtgabs.
Texto completo da fonteMahdia, Marjana, e Quazi Deen Mohd Khosru. "Analytical modeling of transport phenomena in heterojunction triple metal gate all around tunneling field effect transistor". AIP Advances 10, n.º 9 (1 de setembro de 2020): 095125. http://dx.doi.org/10.1063/5.0024864.
Texto completo da fonteJeon, Jin-Hyeok, e Won-Ju Cho. "Triple Gate Polycrystalline-Silicon-Based Ion-Sensitive Field-Effect Transistor for High-Performance Aqueous Chemical Application". IEEE Electron Device Letters 40, n.º 2 (fevereiro de 2019): 318–20. http://dx.doi.org/10.1109/led.2018.2890741.
Texto completo da fonteMushtaq, Umar, Leo Raj Solay, S. Intekhab Amin e Sunny Anand. "Design and Analog Performance Analysis of Triple Material Gate Based Doping-Less Tunnel Field Effect Transistor". Journal of Nanoelectronics and Optoelectronics 14, n.º 8 (1 de agosto de 2019): 1177–82. http://dx.doi.org/10.1166/jno.2019.2662.
Texto completo da fonteBoukortt, Nour El Islam, Baghdad Hadri, Alina Caddemi, Giovanni Crupi e Salvatore Patane. "Temperature Dependence of Electrical Parameters of Silicon-on-Insulator Triple Gate n-Channel Fin Field Effect Transistor". Transactions on Electrical and Electronic Materials 17, n.º 6 (25 de dezembro de 2016): 329–34. http://dx.doi.org/10.4313/teem.2016.17.6.329.
Texto completo da fonteShringi, Shivangi, Ashish Raman, Sarabdeep Singh e Naveen Kumar. "Design and Analysis of Source Engineered with High Electron Mobility Material Triple Gate Junctionless Field Effect Transistor". Journal of Nanoelectronics and Optoelectronics 14, n.º 6 (1 de junho de 2019): 825–32. http://dx.doi.org/10.1166/jno.2019.2558.
Texto completo da fonteSaha, Priyanka, Rudra Sankar Dhar, Swagat Nanda, Kuleen Kumar e Moath Alathbah. "The Optimization and Analysis of a Triple-Fin Heterostructure-on-Insulator Fin Field-Effect Transistor with a Stacked High-k Configuration and 10 nm Channel Length". Nanomaterials 13, n.º 23 (23 de novembro de 2023): 3008. http://dx.doi.org/10.3390/nano13233008.
Texto completo da fonteBaral, Biswajit, Aloke Kumar Das, Debashis De e Angsuman Sarkar. "An analytical model of triple-material double-gate metal-oxide-semiconductor field-effect transistor to suppress short-channel effects". International Journal of Numerical Modelling: Electronic Networks, Devices and Fields 29, n.º 1 (9 de janeiro de 2015): 47–62. http://dx.doi.org/10.1002/jnm.2044.
Texto completo da fonteChoudhury, Sagarika, Krishna Lal Baishnab, Koushik Guha, Zoran Jakšić, Olga Jakšić e Jacopo Iannacci. "Modeling and Simulation of a TFET-Based Label-Free Biosensor with Enhanced Sensitivity". Chemosensors 11, n.º 5 (22 de maio de 2023): 312. http://dx.doi.org/10.3390/chemosensors11050312.
Texto completo da fonteSharma, Dheeraj, Bhagwan Ram Raad, Dharmendra Singh Yadav, Pravin Kondekar e Kaushal Nigam. "Two‐dimensional potential, electric field and drain current model of source pocket hetero gate dielectric triple work function tunnel field‐effect transistor". Micro & Nano Letters 12, n.º 1 (janeiro de 2017): 11–16. http://dx.doi.org/10.1049/mnl.2016.0351.
Texto completo da fonteVenkatesh, M., M. Suguna e N. B. Balamurugan. "Subthreshold Performance Analysis of Germanium Source Dual Halo Dual Dielectric Triple Material Surrounding Gate Tunnel Field Effect Transistor for Ultra Low Power Applications". Journal of Electronic Materials 48, n.º 10 (6 de agosto de 2019): 6724–34. http://dx.doi.org/10.1007/s11664-019-07492-0.
Texto completo da fontePopov, Vladimir P., Valentin A. Antonov, Andrey V. Miakonkikh e Konstantin V. Rudenko. "Ion Drift and Polarization in Thin SiO2 and HfO2 Layers Inserted in Silicon on Sapphire". Nanomaterials 12, n.º 19 (28 de setembro de 2022): 3394. http://dx.doi.org/10.3390/nano12193394.
Texto completo da fonteBorghei, Moein, e Mona Ghassemi. "Characterization of Partial Discharge Activities in WBG Power Converters under Low-Pressure Condition". Energies 14, n.º 17 (30 de agosto de 2021): 5394. http://dx.doi.org/10.3390/en14175394.
Texto completo da fonteChoi, Sung-Hwan, Hee-Sun Shin e Min-Koo Han. "Novel F-Shaped Triple-Gate Structure for Suppression of Kink Effect and Improvement of Hot Carrier Reliability in Low-Temperature Polycrystalline Silicon Thin-Film Transistor". Japanese Journal of Applied Physics 48, n.º 4 (20 de abril de 2009): 04C155. http://dx.doi.org/10.1143/jjap.48.04c155.
Texto completo da fonteTsutsumi, Toshiyuki. "Very low and broad threshold voltage fluctuation caused by ion implantation to silicon-on-insulator triple-gate fin-type field effect transistor using three-dimensional process and device simulations". Japanese Journal of Applied Physics 56, n.º 6S1 (16 de maio de 2017): 06GF12. http://dx.doi.org/10.7567/jjap.56.06gf12.
Texto completo da fonteNA, KYOUNG-IL, JUNG-HEE LEE, SORIN CRISTOLOVEANU, YOUNG-HO BAE, PAUL PATRUNO e WADE XIONG. "SHORT CHANNEL, FLOATING BODY, AND 3D COUPLING EFFECTS IN TRIPLE-GATE MOSFET". International Journal of High Speed Electronics and Systems 18, n.º 04 (dezembro de 2008): 773–82. http://dx.doi.org/10.1142/s0129156408005758.
Texto completo da fonteYang, J. W., e J. G. Fossum. "On the Feasibility of Nanoscale Triple-Gate CMOS Transistors". IEEE Transactions on Electron Devices 52, n.º 6 (junho de 2005): 1159–64. http://dx.doi.org/10.1109/ted.2005.848109.
Texto completo da fonteCRISTOLOVEANU, SORIN, ROMAIN RITZENTHALER, AKIKO OHATA e OLIVIER FAYNOT. "3D Size Effects in Advanced SOI Devices". International Journal of High Speed Electronics and Systems 16, n.º 01 (março de 2006): 9–30. http://dx.doi.org/10.1142/s0129156406003515.
Texto completo da fonteTeixeira, Fernando F., Caio C. M. Bordallo, Marcilei A. Guazzelli, Paula Ghedini Der Agopian, João Antonio Martino, Eddy Simoen e Cor Clayes. "Parasitic Conduction Response to X-ray Radiation in Unstrained and Strained Triple-Gate SOI MuGFETs". Journal of Integrated Circuits and Systems 9, n.º 2 (28 de dezembro de 2014): 97–102. http://dx.doi.org/10.29292/jics.v9i2.394.
Texto completo da fonteDoria, Rodrigo T., Renan D. Trevisoli, Michelly De Souza e Marcelo Antonio Pavanello. "Impact of the Series Resistance in the I-V Characteristics of Junctionless Nanowire Transistors and its dependence on the Temperature". Journal of Integrated Circuits and Systems 7, n.º 2 (27 de dezembro de 2012): 121–29. http://dx.doi.org/10.29292/jics.v7i2.364.
Texto completo da fontePark, Taeho, Kyoungah Cho e Sangsig Kim. "Temperature-Dependent Feedback Operations of Triple-Gate Field-Effect Transistors". Nanomaterials 14, n.º 6 (9 de março de 2024): 493. http://dx.doi.org/10.3390/nano14060493.
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