Literatura científica selecionada sobre o tema "Transistor en tranchée"
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Artigos de revistas sobre o assunto "Transistor en tranchée"
Morancho, F., P. Rossel e H. Tranduc. "Propriétés statiques et dynamiques du transistor MOS de puissance à tranchées (UMOS) “basse-tension”". Journal de Physique III 6, n.º 2 (fevereiro de 1996): 301–22. http://dx.doi.org/10.1051/jp3:1996124.
Texto completo da fonteTeses / dissertações sobre o assunto "Transistor en tranchée"
Gay, Roméric. "Développement de composants analogiques embarqués dans des microcontrôleurs destinés à l'Internet des Objets (loT)". Electronic Thesis or Diss., Aix-Marseille, 2022. http://www.theses.fr/2022AIXM0218.
Texto completo da fonteThe aim of this work is to improve the performance, cost and area of a microcontroller manufactured in a 40 nm CMOS embedded memory technology (eNVM), by developing new transistor architectures suitable for the IoT market. The context is first presented with a focus on the technological and economical limitations of the CMOS technology. In a second part, the eNVM manufacturing process as well as the architecture and operation mode of a new component called triple gate transistor are presented. Based on this new architecture which provides independent control gates, various multigate transistors are manufactured and their electrical behaviour is analysed. Reliability studies are then carried out, to assess the reliability of the gate’s oxides. The objective is to study the impact of an electrical stress applied to one transistor gate on the gates not subject to this same stress. Electrical characterizations and TCAD simulations are also conducted to improve the understanding. Finally, the structure of the triple gate transistor is modelled using a compact PSP transistor model. The aim is to evaluate the behaviour but also the electrical performance of this transistor at the circuit level
Ramadout, Benoit. "Capteurs d’images CMOS à haute résolution à Tranchées Profondes Capacitives". Thesis, Lyon 1, 2010. http://www.theses.fr/2010LYO10068.
Texto completo da fonteCMOS image sensors showed in the last few years a dramatic reduction of pixel pitch. However pitch shrinking is increasingly facing crosstalk and reduction of pixel signal, and new architectures are now needed to overcome those limitations. Our pixel with Capacitive Deep Trench Isolation and Vertical Transfer Gate (CDTI+VTG) has been developed in this context. Innovative integration of polysilicon-filled deep trenches allows high-quality pixel isolation, vertically extended photodiode and deep vertical transfer ability. First, specific process steps have been developed. In parallel, a thorough study of pixel MOS transistors has been carried out. We showed that capacitive trenches can be also operated as extra lateral gates, which opens promising applications for a multi-gate transistor compatible with CMOS-bulk technology. Finally, a 3MPixel demonstrator integrating 1.75*1.75 μm² pixels has been realized in a CMOS 120 nm technology. Pixel performances could be measured and exploited. In particular, a low dark current level could be obtained thanks to electrostatic effect of capacitive isolation trenches
Morancho, Frédéric. "Le transistor MOS de puissance à tranchées : modélisation et limites de performances". Phd thesis, Université Paul Sabatier - Toulouse III, 1996. http://tel.archives-ouvertes.fr/tel-00165581.
Texto completo da fonteTavernier, Aurélien. "Développement d'un procédé innovant pour le remplissage des tranchées d'isolation entre transistors des technologies CMOS avancées". Phd thesis, Université de Grenoble, 2014. http://tel.archives-ouvertes.fr/tel-00987019.
Texto completo da fonteMarron, Dominique. "Etude des transistors à grille flottante et application à la conception d'une mémoire reconfigurable intégrée sur tranche". Grenoble 1, 1989. http://www.theses.fr/1989GRE10080.
Texto completo da fonteTheolier, Loïc. "Conception de transistor MOS haute tension (1200 volts) pour l'électronique de puissance". Phd thesis, Université Paul Sabatier - Toulouse III, 2008. http://tel.archives-ouvertes.fr/tel-00377784.
Texto completo da fonteCarbonero, Jean-Louis. "Développement des méthodes de mesures en hyperfréquences sur tranches de silicium et application à la caractérisation des technologies CMOS et BICMOS sub-microniques". Grenoble INPG, 1996. http://www.theses.fr/1996INPG0051.
Texto completo da fonteLetourneau, Pascal. "Etude et réalisation du transistor à base perméable en technologie microélectronique silicium et évaluation en hyperfréquence". Grenoble 1, 1990. http://www.theses.fr/1990GRE10039.
Texto completo da fonteMelul, Franck. "Développement d'une nouvelle génération de point mémoire de type EEPROM pour les applications à forte densité d'intégration". Electronic Thesis or Diss., Aix-Marseille, 2022. http://www.theses.fr/2022AIXM0266.
Texto completo da fonteThe objective of this thesis was to develop a new generation of EEPROM memory for high reliability and high density applications. First, an innovative memory cell developed by STMicroelectronics - eSTM (Split-gate charge storage memory with buried vertical selection transistor) - was studied as a reference cell. In a second part, to improve the reliability of the eSTM cell and to allow a more aggressive miniaturization of the EEPROM cell, a new memory architecture has been proposed: the BitErasable cell. It showed an excellent reliability and allowed to bring elements of under-standing on the degradation mechanisms present in these memory devices with buried selection transistor. This new architecture also offers the possibility to individually erase cells in a memory array: bit by bit. Aware of the great interest of bit-by-bit erasing, a new erasing mechanism by hot hole injection has been proposed for the eSTM cell. It has shown performances and a level of reliability perfectly compatible with the industrial requirements of Flash-NOR applications
Théolier, Loïc. "Conception de transistors MOS haute tension (1200 Volts) pour l'électronique de puissance". Toulouse 3, 2008. http://thesesups.ups-tlse.fr/539/.
Texto completo da fonteIGBTs are currently used in rail train 1200 Volts power converter. These are disabled by important switch losses and thermal surge. Substitute IGBTs by power MOSFETs would enable to overcome these drawbacks. However, in this voltage range, MOSFETs are penalized by the "Breakdown voltage / On-state resistance" trade-off. As part of this thesis works, we have studied many principles to invent a new powerful MOSFET structure. We have chosen a Superjunction structure, made by deep trench etching and boron diffusion. Theoretically, this structure exhibits 13 m?. Cm2 for 1200 V. The main part of the work was to optimize this structure. For this, we have studied many technological parameter's influence on "Breakdown voltage / On-state resistance" the trade-off. We have developed a new innovated junction termination in order to sustain the desired breakdown voltage. It was necessary to identify the process critical steps. From this point, we have fabricated a 1200 V diode which enabled to validate some of these steps