Artigos de revistas sobre o tema "Systems on chip (SoCs)"
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Piguet, Christian. "Power consumption reduction in systems on Chip (SoCs)". Annales Des Télécommunications 59, n.º 7-8 (julho de 2004): 884–902. http://dx.doi.org/10.1007/bf03180026.
Texto completo da fonteHansson, Andreas, Kees Goossens e Andrei Rădulescu. "Avoiding Message-Dependent Deadlock in Network-Based Systems on Chip". VLSI Design 2007 (30 de abril de 2007): 1–10. http://dx.doi.org/10.1155/2007/95859.
Texto completo da fonteBoutekkouk, Fateh, Mohammed Benmohammed, Sebastien Bilavarn e Michel Auguin. "UML2.0 Profiles for Embedded Systems and Systems On a Chip (SOCs)." Journal of Object Technology 8, n.º 1 (2009): 135. http://dx.doi.org/10.5381/jot.2009.8.1.a1.
Texto completo da fonteMaity, Srijeeta, Anirban Ghose, Soumyajit Dey e Swarnendu Biswas. "Thermal-aware Adaptive Platform Management for Heterogeneous Embedded Systems". ACM Transactions on Embedded Computing Systems 20, n.º 5s (31 de outubro de 2021): 1–28. http://dx.doi.org/10.1145/3477028.
Texto completo da fonteBogdan, Paul, Tudor Dumitraş e Radu Marculescu. "Stochastic Communication: A New Paradigm for Fault-Tolerant Networks-on-Chip". VLSI Design 2007 (22 de abril de 2007): 1–17. http://dx.doi.org/10.1155/2007/95348.
Texto completo da fonteSi, Qilin, Santosh Shetty e Benjamin Carrion Schaefer. "Building Complete Heterogeneous Systems-on-Chip in C: From Hardware Accelerators to CPUs". Electronics 10, n.º 14 (20 de julho de 2021): 1746. http://dx.doi.org/10.3390/electronics10141746.
Texto completo da fonteTouati, Djallel Eddine, Aziz Oukaira, Ahmad Hassan, Mohamed Ali, Ahmed Lakhssassi e Yvon Savaria. "Accurate On-Chip Thermal Peak Detection Based on Heuristic Algorithms and Embedded Temperature Sensors". Electronics 12, n.º 13 (6 de julho de 2023): 2978. http://dx.doi.org/10.3390/electronics12132978.
Texto completo da fonteTong, Huyan. "An Overview on On-chip Network Routing Optimisation". Applied and Computational Engineering 8, n.º 1 (1 de agosto de 2023): 191–95. http://dx.doi.org/10.54254/2755-2721/8/20230123.
Texto completo da fonteLu, Jian, Hongwei Jia, Andres Arias, Xun Gong e Z. John Shen. "On-Chip Bondwire Magnetics with Ferrite-Epoxy Glob Coating for Power Systems on Chip". International Journal of Power Management Electronics 2008 (16 de julho de 2008): 1–9. http://dx.doi.org/10.1155/2008/678415.
Texto completo da fonteNandi, Purab, K. R. Anupama, Himanish Agarwal, Arav Jain e Siddharth Paliwal. "Use of the k-nearest neighbour and its analysis for fall detection on Systems on a Chip for multiple datasets". Acta IMEKO 12, n.º 3 (18 de setembro de 2023): 1–11. http://dx.doi.org/10.21014/actaimeko.v12i3.1489.
Texto completo da fonteGonzalez-Martinez, Guillermo, Remberto Sandoval-Arechiga, Luis Octavio Solis-Sanchez, Laura Garcia-Luciano, Salvador Ibarra-Delgado, Juan Ramon Solis-Escobedo, Jose Ricardo Gomez-Rodriguez e Viktor Ivan Rodriguez-Abdala. "A Survey of MPSoC Management toward Self-Awareness". Micromachines 15, n.º 5 (26 de abril de 2024): 577. http://dx.doi.org/10.3390/mi15050577.
Texto completo da fonteWegner, Tim, Martin Gag e Dirk Timmermann. "Performance Analysis of Temperature Management Approaches in Networks-on-Chip". International Journal of Embedded and Real-Time Communication Systems 3, n.º 4 (outubro de 2012): 19–41. http://dx.doi.org/10.4018/jertcs.2012100102.
Texto completo da fonteR, Anala M., Amit N. Subrahmanya e Allbright D’Souza. "Performance Analysis of Mesh-based NoC’s on Routing Algorithms". International Journal of Electrical and Computer Engineering (IJECE) 8, n.º 5 (1 de outubro de 2018): 3368. http://dx.doi.org/10.11591/ijece.v8i5.pp3368-3373.
Texto completo da fonteGomez-Rodriguez, Jose Ricardo, Remberto Sandoval-Arechiga, Salvador Ibarra-Delgado, Viktor Ivan Rodriguez-Abdala, Jose Luis Vazquez-Avila e Ramon Parra-Michel. "A Survey of Software-Defined Networks-on-Chip: Motivations, Challenges and Opportunities". Micromachines 12, n.º 2 (12 de fevereiro de 2021): 183. http://dx.doi.org/10.3390/mi12020183.
Texto completo da fonteZhang, Wei, Zihao Jiang, Zhiguang Chen, Nong Xiao e Yang Ou. "NUMA-Aware DGEMM Based on 64-Bit ARMv8 Multicore Processors Architecture". Electronics 10, n.º 16 (17 de agosto de 2021): 1984. http://dx.doi.org/10.3390/electronics10161984.
Texto completo da fonteAmoretti, Michele. "Modeling and Simulation of Network-on-Chip Systems with DEVS and DEUS". Scientific World Journal 2014 (2014): 1–9. http://dx.doi.org/10.1155/2014/982569.
Texto completo da fonteELRABAA, MUHAMMAD E. S., e ABDELHAFID BOUHRAOUA. "BUFFER ENGINEERING FOR MODIFIED FAT TREE NoCs FOR MANY-CORE SYSTEMS-ON-CHIP". Journal of Circuits, Systems and Computers 23, n.º 07 (2 de junho de 2014): 1450105. http://dx.doi.org/10.1142/s0218126614501059.
Texto completo da fonteZhou, Xinbing, Peng Hao e Dake Liu. "PCCNoC: Packet Connected Circuit as Network on Chip for High Throughput and Low Latency SoCs". Micromachines 14, n.º 3 (21 de fevereiro de 2023): 501. http://dx.doi.org/10.3390/mi14030501.
Texto completo da fonteNesrine, Toubaline, Bennouar Djamel e Mahdoum Ali. "A Classification and Evaluation Framework for NoC Mapping Strategies". Journal of Circuits, Systems and Computers 26, n.º 02 (3 de novembro de 2016): 1730001. http://dx.doi.org/10.1142/s021812661730001x.
Texto completo da fonteSHI, ZAIFENG, TAO LUO, YUANQING LI, YAN XU e SUYING YAO. "AN ON-CHIP BUS MODELING AND PARAMETER SIMULATION METHOD BASED ON UTILIZATION ANALYSIS". Journal of Circuits, Systems and Computers 22, n.º 10 (dezembro de 2013): 1340031. http://dx.doi.org/10.1142/s0218126613400318.
Texto completo da fonteMelo, Douglas R., Cesar A. Zeferino, Luigi Dilillo e Eduardo A. Bezerra. "Maximizing the Inner Resilience of a Network-on-Chip through Router Controllers Design". Sensors 19, n.º 24 (9 de dezembro de 2019): 5416. http://dx.doi.org/10.3390/s19245416.
Texto completo da fonteClair, Judicael, Guy Eichler e Luca P. Carloni. "SpikeHard: Efficiency-Driven Neuromorphic Hardware for Heterogeneous Systems-on-Chip". ACM Transactions on Embedded Computing Systems 22, n.º 5s (9 de setembro de 2023): 1–22. http://dx.doi.org/10.1145/3609101.
Texto completo da fonteParmar, Harikrishna, e Usha Mehta. "ILP Based Power-Aware Test Time Reduction Using On-Chip Clocking in NoC Based SoC". Journal of Low Power Electronics and Applications 9, n.º 2 (17 de junho de 2019): 19. http://dx.doi.org/10.3390/jlpea9020019.
Texto completo da fonteBhat, Ganapati, Sumit K. Mandal, Sai T. Manchukonda, Sai V. Vadlamudi, Ayushi Agarwal, Jun Wang e Umit Y. Ogras. "Per-Core Power Modeling for Heterogenous SoCs". Electronics 10, n.º 19 (7 de outubro de 2021): 2428. http://dx.doi.org/10.3390/electronics10192428.
Texto completo da fonteA., Rahul, e Shripriyadarshini J. "Environmental Impact Assessment of Chiplet-Based VLSI". International Research Journal of Computer Science 11, n.º 04 (5 de abril de 2024): 364–70. http://dx.doi.org/10.26562/irjcs.2024.v1104.44.
Texto completo da fonteRuaro, Marcelo, Anderson Sant’ana, Axel Jantsch e Fernando Gehm Moraes. "Modular and Distributed Management of Many-Core SoCs". ACM Transactions on Computer Systems 38, n.º 1-2 (julho de 2021): 1–16. http://dx.doi.org/10.1145/3458511.
Texto completo da fonteKordzadeh, Atefeh, Dominik Holzmann, Alfred Binder, Thomas Moldaschl, Johannes Sturm e Ali Roshanghias. "Miniaturized On-Chip NFC Antenna versus Screen-Printed Antenna for the Flexible Disposable Sensor Strips". IoT 1, n.º 2 (28 de outubro de 2020): 309–19. http://dx.doi.org/10.3390/iot1020018.
Texto completo da fonteZhang, Zhun, Xiang Wang, Qiang Hao, Dongdong Xu, Jinlei Zhang, Jiakang Liu e Jinhui Ma. "High-Efficiency Parallel Cryptographic Accelerator for Real-Time Guaranteeing Dynamic Data Security in Embedded Systems". Micromachines 12, n.º 5 (15 de maio de 2021): 560. http://dx.doi.org/10.3390/mi12050560.
Texto completo da fonteMalik, Arsalan Ali, Anees Ullah, Ali Zahir, Affaq Qamar, Shadan Khan Khattak e Pedro Reviriego. "Isolation Design Flow Effectiveness Evaluation Methodology for Zynq SoCs". Electronics 9, n.º 5 (15 de maio de 2020): 814. http://dx.doi.org/10.3390/electronics9050814.
Texto completo da fonteAyachi, Riadh, Ayoub Mhaouch e Abdessalem Ben Abdelali. "Lightweight Cryptography for Network-on-Chip Data Encryption". Security and Communication Networks 2021 (19 de maio de 2021): 1–10. http://dx.doi.org/10.1155/2021/9943713.
Texto completo da fonteBHAGAVAT, MILIND. "Packaging Renaissance with Chiplets". International Symposium on Microelectronics 2019, S1 (1 de outubro de 2019): S1—S17. http://dx.doi.org/10.4071/2380-4505-2019.1.keynote000001.
Texto completo da fonteCirstea, Marcian, Khaled Benkrid, Andrei Dinu, Romeo Ghiriti e Dorin Petreus. "Digital Electronic System-on-Chip Design: Methodologies, Tools, Evolution, and Trends". Micromachines 15, n.º 2 (7 de fevereiro de 2024): 247. http://dx.doi.org/10.3390/mi15020247.
Texto completo da fonteShahane, Priti, e Rakhi Kurup. "Design of fault tolerant algorithm for network on chip router using field programmable gate array". International Journal of Reconfigurable and Embedded Systems (IJRES) 13, n.º 1 (1 de março de 2024): 1. http://dx.doi.org/10.11591/ijres.v13.i1.pp1-8.
Texto completo da fonteDondo Gazzano, Julio, Fernando Rincon, Carlos Vaderrama, Felix Villanueva, Julian Caba e Juan Carlos Lopez. "Facilitating Preemptive Hardware System Design Using Partial Reconfiguration Techniques". Scientific World Journal 2014 (2014): 1–15. http://dx.doi.org/10.1155/2014/164059.
Texto completo da fonteNeuenhahn, M. C., H. Blume e T. G. Noll. "Quantitative design space exploration of routing-switches for Network-on-Chip". Advances in Radio Science 6 (26 de maio de 2008): 145–50. http://dx.doi.org/10.5194/ars-6-145-2008.
Texto completo da fonteRamos, Alberto, Honorio Martín, Carmen Cámara e Pedro Peris-Lopez. "Stimulated Microcontroller Dataset for New IoT Device Identification Schemes through On-Chip Sensor Monitoring". Data 9, n.º 5 (28 de abril de 2024): 62. http://dx.doi.org/10.3390/data9050062.
Texto completo da fontePitre, Boisy, e Martin Margala. "A Novel Approach to Managing System-on-Chip Sub-Blocks Using a 16-Bit Real-Time Operating System". Electronics 13, n.º 10 (18 de maio de 2024): 1978. http://dx.doi.org/10.3390/electronics13101978.
Texto completo da fonteCesini, Daniele, Elena Corni, Antonio Falabella, Andrea Ferraro, Lucia Morganti, Enrico Calore, Sebastiano Fabio Schifano et al. "Power-Efficient Computing: Experiences from the COSA Project". Scientific Programming 2017 (2017): 1–14. http://dx.doi.org/10.1155/2017/7206595.
Texto completo da fontePrasad Acharya, Gobinda, Muddapu Asha Rani, Ganjikunta Ganesh Kumar e Lavanya Poluboyina. "Adaptation of of March-SS algorithm to word-oriented memory built-in self-test and repair". Indonesian Journal of Electrical Engineering and Computer Science 26, n.º 1 (1 de abril de 2022): 96. http://dx.doi.org/10.11591/ijeecs.v26.i1.pp96-104.
Texto completo da fonteLi, Peng, Wei Xi, Xianggen Yin, Hao Yao e Huafeng Chen. "Design of a CMOS Lineal Hall Sensor Front-End Working in Current Mode with Programmable Gain Stage for Power Specific Chip". Journal of Sensors 2021 (1 de fevereiro de 2021): 1–5. http://dx.doi.org/10.1155/2021/6618206.
Texto completo da fonteOhmura, Itta, Gentaro Morimoto, Yousuke Ohno, Aki Hasegawa e Makoto Taiji. "MDGRAPE-4: a special-purpose computer system for molecular dynamics simulations". Philosophical Transactions of the Royal Society A: Mathematical, Physical and Engineering Sciences 372, n.º 2021 (6 de agosto de 2014): 20130387. http://dx.doi.org/10.1098/rsta.2013.0387.
Texto completo da fonteAlraho, Senan, Qummar Zaman, Hamam Abd e Andreas König. "Integrated Sensor Electronic Front-Ends with Self-X Capabilities". Chips 1, n.º 2 (12 de agosto de 2022): 83–120. http://dx.doi.org/10.3390/chips1020008.
Texto completo da fonteBernardi, Paolo, Augusto Maria Guerriero, Giorgio Insinga, Giovanni Paganini, Giambattista Carnevale, Matteo Coppetta, Walter Mischo e Rudolf Ullmann. "Built-In Self-Test Architecture Enabling Diagnosis for Massive Embedded Memory Banks in Large SoCs". Electronics 13, n.º 2 (10 de janeiro de 2024): 303. http://dx.doi.org/10.3390/electronics13020303.
Texto completo da fonteKrishna, Banoth, Sandeep Singh Gill e Amod Kumar. "Design of Low-Power High-Speed 8 Bit CMOS Current Steering DAC for AI Applications". International Journal of Software Science and Computational Intelligence 14, n.º 1 (1 de janeiro de 2022): 1–18. http://dx.doi.org/10.4018/ijssci.304801.
Texto completo da fonteKumar, N. Ashok, G. Shyni, Geno Peter, Albert Alexander Stonier e Vivekananda Ganji. "Architecture of Network-on-Chip (NoC) for Secure Data Routing Using 4-H Function of Improved TACIT Security Algorithm". Wireless Communications and Mobile Computing 2022 (9 de março de 2022): 1–9. http://dx.doi.org/10.1155/2022/4737569.
Texto completo da fonteSharma, Dimple, e Lev Kirischian. "A Decision-Making Method Providing Sustainability to FPGA-Based SoCs by Run-Time Structural Adaptation to Mode of Operation, Power Budget, and Die Temperature Variations". International Journal of Reconfigurable Computing 2021 (1 de setembro de 2021): 1–29. http://dx.doi.org/10.1155/2021/5512938.
Texto completo da fonteGalatenko, V. A., e K. A. Kostyukhin. "Hardware Debugging: an Overview of Modern Approaches". Programmnaya Ingeneria 13, n.º 9 (7 de novembro de 2022): 415–24. http://dx.doi.org/10.17587/prin.13.415-424.
Texto completo da fonteIyer (Subu), Subramanian S. "Packaging without the Package - A More Holistic Moore's Law". International Symposium on Microelectronics 2017, S1 (1 de outubro de 2017): 1–40. http://dx.doi.org/10.4071/isom-2017-slide-2.
Texto completo da fonteNawaz, Gareeb, e Chhagan Charan. "The Design of An LDO Regulator". ITM Web of Conferences 54 (2023): 02010. http://dx.doi.org/10.1051/itmconf/20235402010.
Texto completo da fonteAhmed, Mohammed Altaf, e Suleman Alnatheer. "Deep Q-Learning with Bit-Swapping-Based Linear Feedback Shift Register fostered Built-In Self-Test and Built-In Self-Repair for SRAM". Micromachines 13, n.º 6 (19 de junho de 2022): 971. http://dx.doi.org/10.3390/mi13060971.
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