Teses / dissertações sobre o tema "Self-test and reliability"
Crie uma referência precisa em APA, MLA, Chicago, Harvard, e outros estilos
Veja os 16 melhores trabalhos (teses / dissertações) para estudos sobre o assunto "Self-test and reliability".
Ao lado de cada fonte na lista de referências, há um botão "Adicionar à bibliografia". Clique e geraremos automaticamente a citação bibliográfica do trabalho escolhido no estilo de citação de que você precisa: APA, MLA, Harvard, Chicago, Vancouver, etc.
Você também pode baixar o texto completo da publicação científica em formato .pdf e ler o resumo do trabalho online se estiver presente nos metadados.
Veja as teses / dissertações das mais diversas áreas científicas e compile uma bibliografia correta.
Lee, Catharine H. "The Parenting Styles Self-Test, reliability and construct validity". Thesis, National Library of Canada = Bibliothèque nationale du Canada, 1999. http://www.collectionscanada.ca/obj/s4/f2/dsk1/tape10/PQDD_0029/MQ62237.pdf.
Texto completo da fonteXIONG, XINGGUO. "BUILT-IN SELF-TEST AND SELF-REPAIR FOR CAPACITIVE MEMS DEVICES". University of Cincinnati / OhioLINK, 2005. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1123038236.
Texto completo da fonteHamidzadeh, Mahnaz. "Reliability of patient self-measure physical performance test among mixed cancer patients (stage I-IV)". Thesis, McGill University, 2011. http://digitool.Library.McGill.CA:80/R/?func=dbin-jump-full&object_id=96761.
Texto completo da fonteLa performance physique constitue une méthode utile et complémentaire pour le suivi du cancer et de son impact. Dans ce contexte, l'auto-évaluation de la performance physique par le patient serait très utile. L'étude a évalué la fiabilité de la batterie de tests de Simmonds pour l'auto-évaluation de la performance physique (SPPT) chez un groupe mixte de patients cancéreux (stade I–IV). Quatre-vingt-six patients adultes y ont pris part. La performance selon la batterie SPPT a été mesurée simultanément par le patient et le praticien. La procédure a ensuite été répétée une semaine plus tard. Les coefficients de corrélation intraclasse (ICC) ont démontré que la fiabilité test-retest et inter-examinateur de la performance auto-évaluée à l'égard des sept tâches de la batterie SPPT était de bonne à excellente (ICC1,1= 0,87– 0,963 et ICC1,2= 0,93–0,97, respectivement). Sauf pour la marche de six minutes, les scores moyens de performance se sont révélés systématiquement plus élevés chez les patients comparativement aux mesures du praticien (p<,0005). L'auto-évaluation est donc fiable et on devrait donner comme consigne aux patients de mesurer et de suivre leur performance physique en tant qu'indicateur de l'état pathologique. Toutefois, les méthodes de mesure – celle du patient et celle du praticien – ne peuvent être utilisées de manière interchangeable.
Patel, Darayus Adil. "Test and characterization methodologies for advanced technology nodes". Thesis, Montpellier, 2016. http://www.theses.fr/2016MONTT285/document.
Texto completo da fonteThe introduction of nanometer technologies, has allowed the semiconductor industry to create nanoscale devices in combination with gigascale complexity. However, new technologies bring with them new challenges. In the era of large systems embedded in a single System-On-Chip and fabricated in continuously shrinking technologies, it is important to test and ensure fault-free operation of the whole system. The cost involved in semiconductor test has been steadily growing and testing techniques for integrated circuits are today facing many exciting and complex challenges. Although important advances have been made, existing test solutions are still unable to exhaustively cover all types of defects in advanced technology nodes. Consequently, innovative solutions are required to cope with new failure mechanisms under the constraints of higher density and complexity, cost and time to market pressure, product quality level and usage of low cost test equipment.The work of this thesis is focused on the development of silicon test and characterization methodologies that aid in the accurate detection and resolution of issues that may arise due to variability, manufacturing defects, wear-out or interference. A wide spectrum of these challenges has been addressed from a test perspective to ensure that the availability of effective test solutions does not become a bottleneck in the path towards further scaling. Additionally the advances and innovations introduced in the myriad domains of electronic design, reliability management, manufacturing process improvements etc. that call for the development of advanced, modular and agile test methodologies have been effectively covered within the scope of this work.This thesis presents the significant contributions made for enabling resolution of state of the art industrial test challenges via the design and implementation of novel test strategies (targeting the 28nm FDSOI technology node) for:•Detection & diagnosis of timing faults in standard cells.•Analysis of Setup and Hold margins within silicon.•Verification & reliability analysis of innovative test structures.•Analysis of on-chip self heating.•Enabling characterization and performance evaluation of high speed digital IPs
Adelsköld, Signe, e Hanna Thalin. "Reliabilitets- och validitetsprövning av Modifierad Self-efficacy Scale för patienter med långvarig smärta". Thesis, Uppsala University, Physiotheraphy, 2010. http://urn.kb.se/resolve?urn=urn:nbn:se:uu:diva-129693.
Texto completo da fonteSyfte: Studiens syfte var att reliabilitetspröva stabiliteten för M-SES för patienter med långvarig smärta genom test-retest metoden. Syftet var även att undersöka samtidig validitet för M-SES, genom att utföra M-SES och SES mätt vid samma tillfälle.
Metod: I studien undersöktes self-efficacy instrumentet M-SES på Uppsala Akademiska sjukhus, på avdelningarna för Smärtcentrum och Smärtrehabilitering. Frågeställningarna berörde vilken stabilitets reliabilitet mätt med test-retest som förelåg hos M-SES, samt vilken grad av samtidig validitet som förelåg för M-SES korrelerat med SES. Den slutliga undersökningsgruppen bestod i frågeställningen om stabilitets reliabilitet av 29 patienter (23 kvinnor, sex män), och i frågeställning om samtidig validitet av 22 patienter (17 kvinnor, fem män).
Resultat: Vid prövning av stabilitets reliabilitet för M-SES visade resultatet en stark korrelation, med korrelationskoefficient 0,92 och p<0,05. Det förelåg även en god överrensstämmelse för test-retest undersökningen. Prövningen av samtidig validitet för M-SES visade en stark korrelation, med koefficienten 0,88 och p<0,05.
Konklusion: Studiens resultat visade att det förelåg en stark stabilitets reliabilitet och samtidig validitet för M-SES för patienter med långvarig smärta. Då studien genomfördes med få deltagare bör resultatet tolkas med försiktighet.
Rucker, Paul D. "A reliability comparison of recessed-gate and self-aligned gate small signal GaAs MESFETS utilizing an accelerated life test set designed for large scale automated testing". Thesis, Virginia Polytechnic Institute and State University, 1987. http://hdl.handle.net/10919/71231.
Texto completo da fonteMaster of Science
Lubaszewski, Marcelo. "Le test unifié de cartes appliqué à la conception de systèmes fiables". Grenoble INPG, 1994. http://www.theses.fr/1994INPG0055.
Texto completo da fonteOn one hand, if the goal is to ensure that the design validation, the manufacturing and the maintenance testing, along with the concurrent error detection are efficiently performed in electronic systems, one is led to integrate the off-line and the on-line testing into circuits. Then, for complex systems to make profit of these two types of tests, such unification must be extended from the circuit to the board and module levels. On the other hand, although the unification of off-line and on-line testing techniques makes possible the design of systems suiting any safety application, the hardware added for increasing the application safety also decreases the system availability and reliability, since the probability of occurrence of faults increases. Faced to these two antagonist aspects, this thesis aims at finding a compromise between the safety and the reliability of complex electronic systems. Thus, firstly we propose a solution to the off-line test and diagnosis problems found in the intermediate steps in the evolution towards boards which are 100% compliant with the IEEE standard for boundary scan testing. An approach for the BIST (Built-In Self-Test) of boundary scan circuits and interconnects then illustrates the ultimate step in the board off-line testing. Next, the UBIST (Unified BIST) scheme - merging BIST and self-checking capabilities for circuit on-line testing, is combined with the IEEE standard for boundary scan testing, in order to obtain a design strategy for unifying the tests of interconnects and circuits populating boards and modules. Finally, we propose a fault-tolerant scheme based on the duplication of these kind of modules which ensures the competitivity of the resulting system in terms of reliability at the same time as preserving the inherent module safety
Cota, Erika Fernandes. "ATPG para teste de circuitos analogicos e mistos". reponame:Biblioteca Digital de Teses e Dissertações da UFRGS, 1997. http://hdl.handle.net/10183/117097.
Texto completo da fonteThis work aims at studying the testing problems related to analog and mixedsignal circuits. This kind of research is very useful nowadays, since there is a great demand for circuits that need some kind of interaction between analog and digital blocks. This document presents a method and an automatic test pattern generation tool aplicable to the detection of soft, large and hard fault in linear and non-linear circuits. This method considers, also, interaction faults and computes diagnose vectors that garantee maximal fault coverage. At first. a brief review of methods. approaches and related works is presented. Then. the fault model used and the test methodology are defined. and an ATPG tool is proposed. Next, the ATPG algorithm is applied to a linear and to a non-linear circuit. The test vector generation process and the test vectors computed are then shown. After that a way to automatize the ATPG tool is discussed under the light of those commercial tools that were used in this work. Finally. the conclusions and results are presented.
Small, Nicola. "Patient empowerment in long-term conditions : development and validation of a new measure". Thesis, University of Manchester, 2012. https://www.research.manchester.ac.uk/portal/en/theses/patient-empowerment-in-longterm-conditions-development-and-validation-of-a-new-measure(b85db41b-5898-4c51-a180-78439eb94ea7).html.
Texto completo da fonteButhelezi, Colette Lesego. "Test-retest reliability of the Picture My Participation Instrument". Diss., University of Pretoria, 2018. http://hdl.handle.net/2263/73565.
Texto completo da fonteMini Dissertation (MAAC)--University of Pretoria, 2018.
This research forms part of an international project jointly funded by the National Research Foundation (NRF)/ STINT. Opinions expressed and conclusions arrived at are those of the author and are not necessarily to be attributed to the NRF/ STINT.
Centre for Augmentative and Alternative Communication (CAAC)
MAAC
Unrestricted
Sutton, James Eric. "A Test of the Reliability and Validity of the Life-Events Calendar Method Using Ohio Prisoners". The Ohio State University, 2008. http://rave.ohiolink.edu/etdc/view?acc_num=osu1222139932.
Texto completo da fonteAli, Elsayed Sarah. "Fault Tolerance in Hardware Spiking Neural Networks". Electronic Thesis or Diss., Sorbonne université, 2021. http://www.theses.fr/2021SORUS310.
Texto completo da fonteArtificial Intelligence (AI) and machine learning algorithms are taking up the lion's share of the technology market nowadays, and hardware AI accelerators are foreseen to play an increasing role in numerous applications, many of which are mission-critical and safety-critical. This requires assessing their reliability and developing cost-effective fault tolerance techniques; an issue that remains largely unexplored for neuromorphic chips and Spiking Neural Networks (SNNs). A tacit assumption is often made that reliability and error-resiliency in Artificial Neural Networks (ANNs) are inherently achieved thanks to the high parallelism, structural redundancy, and the resemblance to their biological counterparts. However, prior work in the literature unraveled the falsity of this assumption and exposed the vulnerability of ANNs to faults. This requires assessing their reliability and developing cost-effective fault tolerance techniques; an issue that remains largely unexplored for neuromorphic chips and Spiking Neural Networks (SNNs). In this thesis, we tackle the subject of testing and fault tolerance in hardware SNNs. We start by addressing the issue of post-manufacturing test and behavior-oriented self-test of hardware neurons. Then we move on towards a global solution for the acceleration of testing and resiliency analysis of SNNs against hardware-level faults. We also propose a neuron fault tolerance strategy for SNNs, optimized for low area and power overhead. Finally, we present a hardware case-study which would be used as a platform for demonstrating fault-injection experiments and fault-tolerance capabilities
Lahrach, Farid. "Tolérance aux pannes des circuits FPGAs à base de mémoire SRAM". Thesis, Troyes, 2016. http://www.theses.fr/2016TROY0028.
Texto completo da fonteNowadays, SRAM-based FPGAs are omnipresent for embedded electronic applications. Consequently, these circuits became the key player of the overall System-On-Chip (SoC) yield enhancement. However, faults are increasingly pronounced in these emergent technologies, from permanent faults arising from circuit processing at nanometer scales to transient soft errors arising from high-energy particle hits. So fault-tolerance of SRAM-based FPGA is an important system metric to ensure the dependability of embedded applications. The first part of this thesis exposes a comprehensive technique to cope with multiple faults in applications implemented in SRAM-based FPGA without incurring substantial area, power, or performance penalties. This approach has three main benefits compared to redundancy-based fault-tolerance: it’s very low overhead, the option for runtime management, and its complete flexibility. Run-time management can be a very valuable feature of a system, particularly for mission-critical applications. This fault-tolerance approach handles runtime problems on-line, minimizing the amount of system downtime and eliminating the need for outside intervention. The last part of this thesis is oriented toward configuration memory array of SRAM-based FPGA test and diagnostic. New fault models in configuration frames and March algorithms are proposed. These tests have the advantage to benefit from a fast implementation and achieving high fault coverage
Lubaszewski, Marcelo Soares. "Le test unifié de cartes appliqué à la conception de systèmes fiables". reponame:Biblioteca Digital de Teses e Dissertações da UFRGS, 1994. http://hdl.handle.net/10183/26862.
Texto completo da fonteOn one hand, if the goal is to ensure that the design validation, the manufacturing and the maintenance testing, along with the concurrent error detection are efficiently performed in electronic systems, one is led to integrate the off-line and the on-line testing into circuits. Then, for complex systems to make profit of these two types of tests, such unification must be extended from the circuit to the board and module levels. On the other hand, although the unification of off-line and on-line testing techniques makes possible the design of systems suiting any safety application, the hardware added for increasing the application safety also decreases the system reliability, since the probability of occurrence of faults increases. Faced to these two antagonist aspects, this thesis aims at finding a compromise between the safety and the reliability of complex electronic systems. Thus, firstly we propose a solution to the off-line test and diagnosis problems found in the intermediate steps in the evolution towards boards which are 100% compliant with the IEEE standard 1149.1 for boundary scan testing. An approach for the BIST (Built-In Self-Test) of boundary scan circuits and interconnects then illustrates the ultimate step in the board off-line testing. Next, the UBIST (Unified BIST) scheme - merging BIST and self-checking capabilities for circuit on-line testing, is combined with the IEEE standard 1149.1, in order to obtain a design strategy for unifying the tests of interconnects and circuits populating boards and modules. Finally, we propose a fault-tolerant scheme based on the duplication of these kind of modules which ensures the competitivity of the resulting system in terms of reliability at the same time as preserving the inherent module safety.
Mei, Wen, e 梅文. "Reliability Test of Our Self Design Actigraphy on Autonomic Sleep/Wake Scoring in Human". Thesis, 2014. http://ndltd.ncl.edu.tw/handle/62351206860233346667.
Texto completo da fonte國立陽明大學
腦科學研究所
103
Background: Sleep disorders have become a common disease in recent years and we pay more attention on sleep detecting gradually. Polysomnography (PSG) is the gold standard for assessing sleep quality, but it needs high cost and long set-up time which is not suitable for public. Actigraphy, is low cost, small size, set up fast, and long-term recording, can be used to distinguish sleep and detect activities. As we known, detecting sleep/wake pattern by using actigraphy is more convenient and less-cost than traditional sleep detecting tool, also can long-term recording. However, because of low accuracy, using actigraphy on sleep scoring and physical activity detecting is still not well-estimated. Aim: To raise the accuracy of actigraphy in distinguishing sleep/wake patterns and application for long-distance health care, we develop sleep/wake discrimination algorithm by laboratory actigraphy, and the comparison with polysomnography (PSG) by using sleep scoring and commercial actiwatch to confirm sleep/wake analysis function. Methods: Each participant carried a laboratory actigraphy with the function of sleep/wake pattern analysis (KY9, K&;Y lab, Taiwan, size: 3.5 x 3.5 x 0.6 cm3, weight: 16 g), a commercial actigraphy (Actiwatch, Actigraph, wActiSleep-BT Monitor, Pensacola) as well as a miniature PSG (TD1, Taiwan Telemedicine Device Company, Taiwan) for 24 hours recording. We compared the results which from the laboratory sleep/wake patterns analysis, standard sleep/wake scoring system and commercial actiwatch. Results: The correlation between TD1 and KY9 by the Pearson linear regression was higher than the correlation between TD1 and commercial actiwatch in total sleep time (r = 0.98, p < 0.001). The Bland-Altman plot used to calculate the variation of KY9 and Actiwatch between TD1 showed that KY9 was better than commercial actiwatch in stability (p = 0.02). Moreover, the similarity between KY9 and TD1 of the sleep parameters, including sleep efficiency (SE) and wakening time after sleep onset (WASO) was higher than commercial actiwatch (p < 0.01). Conclusion: The laboratory-made actigraphy with our developed sleep/wake discrimination analysis have higher accuracy for sleep/wake scoring than the commercial actiwatch, especially in total sleep time. This can provide low power and more convenient sleep monitoring technique with great stability and consistency; even combine cloud computing technique to raise the life quality for general population.
Murphy, Angela. "Defining the boundaries between trait emotional intelligence and ability emotional intelligence : an assessment of the relationship between emotional intelligence and cognitive thinking styles within the occupational environment". Thesis, 2008. http://hdl.handle.net/10500/2701.
Texto completo da fontePsychology
D. Litt. et Phil. (Psychology)