Artigos de revistas sobre o tema "Pipeline datapath"
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Veja os 33 melhores artigos de revistas para estudos sobre o assunto "Pipeline datapath".
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Ravikumar, C. P., e V. Saxena. "TOGAPS: A Testability Oriented Genetic Algorithm For Pipeline Synthesis". VLSI Design 5, n.º 1 (1 de janeiro de 1996): 77–87. http://dx.doi.org/10.1155/1996/65320.
Texto completo da fonteKingyens, Jeffrey, e J. Gregory Steffan. "The Potential for a GPU-Like Overlay Architecture for FPGAs". International Journal of Reconfigurable Computing 2011 (2011): 1–15. http://dx.doi.org/10.1155/2011/514581.
Texto completo da fonteLee, Y. H., M. Khalil-Hani e M. N. Marsono. "An FPGA-Based Quantum Computing Emulation Framework Based on Serial-Parallel Architecture". International Journal of Reconfigurable Computing 2016 (2016): 1–18. http://dx.doi.org/10.1155/2016/5718124.
Texto completo da fonteKashima, Ryota, Ikki Nagaoka, Masamitsu Tanaka, Taro Yamashita e Akira Fujimaki. "64-GHz Datapath Demonstration for Bit-Parallel SFQ Microprocessors Based on a Gate-Level-Pipeline Structure". IEEE Transactions on Applied Superconductivity 31, n.º 5 (agosto de 2021): 1–6. http://dx.doi.org/10.1109/tasc.2021.3061353.
Texto completo da fonteAlachiotis, Nikolaos, e Alexandros Stamatakis. "A Vector-Like Reconfigurable Floating-Point Unit for the Logarithm". International Journal of Reconfigurable Computing 2011 (2011): 1–12. http://dx.doi.org/10.1155/2011/341510.
Texto completo da fonteTitus, Dr Anita. "Datapath Optimization in AES using Pipelined Architecture". International Journal for Research in Applied Science and Engineering Technology 8, n.º 8 (31 de agosto de 2020): 940–44. http://dx.doi.org/10.22214/ijraset.2020.31056.
Texto completo da fonteCekli, Serap, e Ali Akman. "Enhanced SPIHT Algorithm with Pipelined Datapath Architecture Design". Electrica 19, n.º 1 (5 de março de 2019): 29–36. http://dx.doi.org/10.26650/electrica.2018.15101.
Texto completo da fonteNabi, Syed Waqar, e Wim Vanderbauwhede. "Automatic Pipelining and Vectorization of Scientific Code for FPGAs". International Journal of Reconfigurable Computing 2019 (18 de novembro de 2019): 1–12. http://dx.doi.org/10.1155/2019/7348013.
Texto completo da fonteCappuccino, G., G. Cocorullo, P. Corsonello e S. Perri. "High speed self-timed pipelined datapath for square rooting". IEE Proceedings - Circuits, Devices and Systems 146, n.º 1 (1999): 16. http://dx.doi.org/10.1049/ip-cds:19990271.
Texto completo da fonteArató, Péter, lstván Béres, Andrzej Rucinski, Robert Davis e Roy Torbert. "A high-level datapath synthesis method for pipelined structures". Microelectronics Journal 25, n.º 3 (maio de 1994): 237–47. http://dx.doi.org/10.1016/0026-2692(94)90015-9.
Texto completo da fonteXianwu Xing e Ching Chuen Jong. "Multivoltage Multifrequency Low-Energy Synthesis for Functionally Pipelined Datapath". IEEE Transactions on Very Large Scale Integration (VLSI) Systems 17, n.º 9 (setembro de 2009): 1348–52. http://dx.doi.org/10.1109/tvlsi.2008.2002684.
Texto completo da fonteSergiyenko, A. M., V. A. Romankevich e A. A. Serhienko. "Genetic Programming of Application-Specific Pipelined Datapaths". Èlektronnoe modelirovanie 42, n.º 2 (9 de abril de 2020): 25–40. http://dx.doi.org/10.15407/emodel.42.02.025.
Texto completo da fonteArató, Péter, Zoltán Ádám Mann e András Orbán. "Time-constrained scheduling of large pipelined datapaths". Journal of Systems Architecture 51, n.º 12 (dezembro de 2005): 665–87. http://dx.doi.org/10.1016/j.sysarc.2005.02.001.
Texto completo da fonteHong-Shin Jun e Sun-Young Hwang. "Design of a pipelined datapath synthesis system for digital signal processing". IEEE Transactions on Very Large Scale Integration (VLSI) Systems 2, n.º 3 (setembro de 1994): 292–303. http://dx.doi.org/10.1109/92.311638.
Texto completo da fonteSergiyenko, A. M., e I. V. Mozghovyi. "Hardware Decompressor Design". Èlektronnoe modelirovanie 45, n.º 5 (10 de outubro de 2023): 113–28. http://dx.doi.org/10.15407/emodel.45.05.113.
Texto completo da fonteJin, Zheming, e Jason D. Bakos. "A Heuristic Scheduler for Port-Constrained Floating-Point Pipelines". International Journal of Reconfigurable Computing 2013 (2013): 1–9. http://dx.doi.org/10.1155/2013/849545.
Texto completo da fonteKoch, Andreas. "Efficient Integration of Pipelined IP Blocks into Automatically Compiled Datapaths". EURASIP Journal on Embedded Systems 2007 (2007): 1–9. http://dx.doi.org/10.1155/2007/65173.
Texto completo da fonteKoch, Andreas. "Efficient Integration of Pipelined IP Blocks into Automatically Compiled Datapaths". EURASIP Journal on Embedded Systems 2007, n.º 1 (2007): 065173. http://dx.doi.org/10.1186/1687-3963-2007-065173.
Texto completo da fonteHan, Liang, Jie Chen e Xiaodong Chen. "Power optimization for the datapath of a 32-bit reconfigurable pipelined DSP processor". Journal of Electronics (China) 22, n.º 6 (novembro de 2005): 650–57. http://dx.doi.org/10.1007/bf02687846.
Texto completo da fonteYoo, Hee-Jin, Ju-Young Oh, Jun-Yong Lee e Do-Soon Park. "A Scheduling Approach using Gradual Mobility Reduction for Synthesizing Pipelined Datapaths". KIPS Transactions:PartA 9A, n.º 3 (1 de setembro de 2002): 379–86. http://dx.doi.org/10.3745/kipsta.2002.9a.3.379.
Texto completo da fonteJin, Seunghun, Dongkyun Kim, Thuy Tuong Nguyen, Daijin Kim, Munsang Kim e Jae Wook Jeon. "Design and Implementation of a Pipelined Datapath for High-Speed Face Detection Using FPGA". IEEE Transactions on Industrial Informatics 8, n.º 1 (fevereiro de 2012): 158–67. http://dx.doi.org/10.1109/tii.2011.2173943.
Texto completo da fonteGuo, Wei, KwangHyok Ri, Luping Cui e Jizeng Wei. "An Area-Efficient Unified Architecture for Multi-Functional Double-Precision Floating-Point Computation". Journal of Circuits, Systems and Computers 24, n.º 10 (25 de outubro de 2015): 1550151. http://dx.doi.org/10.1142/s0218126615501510.
Texto completo da fonteNummer, Muhammad, e Manoj Sachdev. "Experimental Results for Slow-speed Timing Characterization of High-speed Pipelined Datapaths". Journal of Electronic Testing 27, n.º 1 (3 de novembro de 2010): 9–17. http://dx.doi.org/10.1007/s10836-010-5186-3.
Texto completo da fonteChowdhury, Shubhajit Roy, Dipankar Chakrabarti e Hiranmay Saha. "FPGA realization of a smart processing system for clinical diagnostic applications using pipelined datapath architectures". Microprocessors and Microsystems 32, n.º 2 (março de 2008): 107–20. http://dx.doi.org/10.1016/j.micpro.2007.12.001.
Texto completo da fonteSalehi, Sayed Ahmad, Rasoul Amirfattahi e Keshab K. Parhi. "Pipelined Architectures for Real-Valued FFT and Hermitian-Symmetric IFFT With Real Datapaths". IEEE Transactions on Circuits and Systems II: Express Briefs 60, n.º 8 (agosto de 2013): 507–11. http://dx.doi.org/10.1109/tcsii.2013.2268411.
Texto completo da fonteYin, Xiao-Bo, Feng Yu e Zhen-Guo Ma. "Resource-Efficient Pipelined Architectures for Radix-2 Real-Valued FFT With Real Datapaths". IEEE Transactions on Circuits and Systems II: Express Briefs 63, n.º 8 (agosto de 2016): 803–7. http://dx.doi.org/10.1109/tcsii.2016.2530862.
Texto completo da fonteWilson, T. C., N. Mukherjee, M. K. Garg e D. K. Banerji. "An ILP Solution for Optimum Scheduling, Module and Register Allocation, and Operation Binding in Datapath Synthesis". VLSI Design 3, n.º 1 (1 de janeiro de 1995): 21–36. http://dx.doi.org/10.1155/1995/23249.
Texto completo da fonteLivramento, Vinícius Dos S., Bruno G. Moraes, Brunno A. Machado, Eduardo Boabaid e José Luiz Güntzel. "Evaluating the Impact of Architectural Decisions on the Energy Efficiency of FDCT/IDCT Configurable IP Cores". Journal of Integrated Circuits and Systems 7, n.º 1 (27 de dezembro de 2012): 23–36. http://dx.doi.org/10.29292/jics.v7i1.353.
Texto completo da fonteJosipović, Lana, Shabnam Sheikhha, Andrea Guerrieri, Paolo Ienne e Jordi Cortadella. "Buffer Placement and Sizing for High-Performance Dataflow Circuits". ACM Transactions on Reconfigurable Technology and Systems 15, n.º 1 (31 de março de 2022): 1–32. http://dx.doi.org/10.1145/3477053.
Texto completo da fonteSoliman, Mostafa I., e Elsayed A. Elsayed. "Simultaneous Multithreaded Matrix Processor". Journal of Circuits, Systems and Computers 24, n.º 08 (12 de agosto de 2015): 1550114. http://dx.doi.org/10.1142/s0218126615501145.
Texto completo da fonteJohn, Elwyn G., Z. Ghassemlooy, Malcolm Woolfson, Steve Harrold, M. Fleury, Mike Barnes e Math Bollen. "Book Reviews: A Guide to Microsoft Excel for Scientists and Engineers, Fiber Bragg Gratings, Signal Detection Theory, Analog BiCMOS Design: Practices and Pitfalls, High Level Synthesis of Pipelined Datapaths, Electronic Control of Switched Reluctance Machines, Power Quality Primer". International Journal of Electrical Engineering & Education 39, n.º 2 (abril de 2002): 175–80. http://dx.doi.org/10.7227/ijeee.39.2.9.
Texto completo da fonteKashima, Ryota, Ikki Nagaoka, Tomoki Nakano, Masamitsu Tanaka, Taro Yamashita e Akira Fujimaki. "Lowering Latency in a High-Speed Gate-Level-Pipelined Single Flux Quantum Datapath Using an Interleaved Register File". IEEE Transactions on Applied Superconductivity, 2023, 1–6. http://dx.doi.org/10.1109/tasc.2023.3249131.
Texto completo da fonte"Energy-Efficient and High-throughput Implementations of Lightweight Block Cipher". International Journal of Innovative Technology and Exploring Engineering 9, n.º 2S (31 de dezembro de 2019): 35–41. http://dx.doi.org/10.35940/ijitee.b1022.1292s19.
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