Literatura científica selecionada sobre o tema "Optimisation mémoire"
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Artigos de revistas sobre o assunto "Optimisation mémoire"
Piarristeguy, Andrea, Pierre Noé e Françoise Hippert. "Verres de chalcogénures pour le stockage de l’information". Reflets de la physique, n.º 74 (dezembro de 2022): 58–63. http://dx.doi.org/10.1051/refdp/202274058.
Texto completo da fonteAbid, Fatma, Abdelkhalak El Hami, Tarek Merzouki, Hassen Trabelsi, Lassaad Walha e Mohamed Haddar. "Optimisation fiabiliste d’une structure en alliage à mémoire de forme". MATEC Web of Conferences 261 (2019): 02001. http://dx.doi.org/10.1051/matecconf/201926102001.
Texto completo da fonteBen Fradj, Hanene, Sébastien Icart, Cécile Belleudy e Michel Auguin. "Optimisation de la consommation mémoire multibanc pour un système multitâches". Techniques et sciences informatiques 26, n.º 5 (5 de junho de 2007): 567–94. http://dx.doi.org/10.3166/tsi.26.567-594.
Texto completo da fontePatoor, E., M. O. Bensalah, A. Eberhardt e M. Berveiller. "Détermination du comportement thermomécanique des alliages à mémoire de forme par optimisation d'un potentiel thermodynamique". Revue de Métallurgie 90, n.º 12 (dezembro de 1993): 1587–92. http://dx.doi.org/10.1051/metal/199390121587.
Texto completo da fonteCorre, Gwenolé, Eric Senn, Nathalie Julien e Eric Martin. "Estimation et optimisation de la consommation des mémoires". Techniques et sciences informatiques 27, n.º 1-2 (19 de março de 2008): 235–54. http://dx.doi.org/10.3166/tsi.27.235-254.
Texto completo da fonteAdmin - JAIM. "Résumés des conférences JRANF 2021". Journal Africain d'Imagerie Médicale (J Afr Imag Méd). Journal Officiel de la Société de Radiologie d’Afrique Noire Francophone (SRANF). 13, n.º 3 (17 de novembro de 2021). http://dx.doi.org/10.55715/jaim.v13i3.240.
Texto completo da fonteTeses / dissertações sobre o assunto "Optimisation mémoire"
Julié-Mollo, Catherine. "Optimisation de l'espace mémoire pour l'évaluation de grammaires attribuées". Orléans, 1989. http://www.theses.fr/1989ORLE2013.
Texto completo da fontePapaix, Caroline. "Optimisation des performances des mémoires EEPROM embarquées". Montpellier 2, 2002. http://www.theses.fr/2002MON20098.
Texto completo da fonteHabhab, Radouane. "Optimisation d'architectures mémoires non-volatiles à piégeage de charges pour les applications microcontrôleur et mémoire autonome". Electronic Thesis or Diss., Université Côte d'Azur, 2023. http://www.theses.fr/2023COAZ4102.
Texto completo da fonteThe aim of this thesis work is to evaluate the performance in programming/cycling/retention of a SONOS memory cell based on a highly innovative split-gate architecture developed by STMicroelectronics, the eSTM™ (embedded Select in Trench Memory). Firstly, we explain the realization of this SONOS memory, which is based on a process step modification of the floating gate eSTM™ memory, with this modification carried out without additional cost.Secondly, we investigate the most efficient program and erase mechanisms for this memory, which also leads us to propose a new SONOS memory architecture. Thirdly, we electrically characterize the P/E activations of the SONOS eSTM™ cell for the two available architectures: dual gate and overlap. For dual gate memory, both memory cells on either side of the selection transistor have their own "ONO/control gate" stack. For overlap memory, the ONO layer is common to both memory cells. Even though this layer is shared, the information storage in ONO is localized only under the relevant control gate due to the discrete nature of charge trapping. The mechanism implemented for write and erase operations is carrier hot injection, and we detail the optimization of biases (different for the two available architectures) of the drain and select gate, which define the written and erased threshold voltages. We then perform endurance tests up to one million cycles for both architectures. Finally, we conduct a study on retention and charge pumping to assess the oxide quality at the interface of our cells. In a fourth phase, we seek to better understand the operation of the memory transistor and the variability of eSTM™ using TCAD simulations and electrical measurements on structures with various geometries
Le, Bouder Gabriel. "Optimisation de la mémoire pour les algorithmes distribués auto-stabilisants". Electronic Thesis or Diss., Sorbonne université, 2023. http://www.theses.fr/2023SORUS002.
Texto completo da fonteSelf-stabilization is a suitable paradigm for distributed systems, particularly prone to transient faults. Errors such as memory or messages corruption, break of a communication link, can put the system in an inconsistent state. A protocol is self-stabilizing if, whatever the initial state of the system, it guarantees that it will return a normal behavior in finite time. Several constraints concern algorithms designed for distributed systems. Asynchrony is one emblematic example. With the development of networks of connected, autonomous devices, it also becomes crucial to design algorithms with a low energy consumption, and not requiring much in terms of resources. One way to address these problems is to aim at reducing the size of the messages exchanged between the nodes of the network. This thesis focuses on the memory optimization of the communication for self-stabilizing distributed algorithms. We establish in this thesis several negative results, which prove the impossibility to solve some problems under a certain limit on the size of the exchanged messages, by showing an impossibility to fully use the presence of unique identifiers in the network below that minimal size. Those results are generic, and may apply to numerous distributed problems. Secondly, we propose particularly efficient algorithms in terms of memory for two fundamental problems in distributed systems: the termination detection, and the token circulation
Fraboulet, Antoine. "Optimisation de la mémoire et de la consommation des systèmes multimédia embarqués". Lyon, INSA, 2001. http://theses.insa-lyon.fr/publication/2001ISAL0054/these.pdf.
Texto completo da fonteThe development in technologies and tool for software compilation and automatic hardware synthesis now makes it possible to conceive in a joint way (Co design) the electronic systems integrated on only one silicon chip, called "System on Chip". These systems in their embedded versions must answer specific constrain s of place, speed and consumption. Moreover, the unceasingly increasing capacities of these systems make it possible today to develop complex applications like multimedia ones. These multimedia applications work, amongst other things, on images and signals of big size; they generate large memory requirements and data transfers handled by nested loops. It is thus necessary to concentrate on memory optimizations when designing such applications in the embedded world. Two means of action are generally used: the choice of a dedicated memory architecture (memory hierarchy and caches) and adequacy of the code describing the application with the generated architecture. We will develop this second axis of memory optimization and how to transform automatically the implementation code, particularly nested loops, to minimize data transfers (large consumer of energy) and memory size (large consumer of surface and energy)
Ninin, Jordan. "Optimisation Globale basée sur l'Analyse d'Intervalles : Relaxation Affine et Limitation de la Mémoire". Phd thesis, Institut National Polytechnique de Toulouse - INPT, 2010. http://tel.archives-ouvertes.fr/tel-00580651.
Texto completo da fonteGamoudi, Oussama. "Optimisation adaptative appliquée au préchargement de données". Paris 6, 2012. http://www.theses.fr/2012PA066192.
Texto completo da fonteData prefetching is an effective way to bridge the increasing performance gap between processor and memory. Prefetching can improve performance but it has some side effects which may lead to no performance improvement while increasing memory pressure or to performance degradation. Adaptive prefetching aims at reducing negative effects of prefetching while keeping its advantages. This paper proposes an adaptive prefetching method based on runtime activity, which corresponds to the processor and memory activities retrieved by hardware counters, to predict the prefetch efficiency. Our approach highlights and relies on the correlation between the prefetch effects and runtime activity. Our method learns all along the execution this correlation to predict the prefetch efficiency in order to filter out predicted inefficient prefetches. Experimental results show that the proposed filter is able to cancel thenegative impact of prefetching when it is unprofitable while keeping the performance improvement due to prefetching when it is beneficial. Our filter works similarly well when several threads are running simultane-ously which shows that runtime activity enables an efficient adaptation of prefetch by providing information on running-applications behaviors and interactions
Barreteau, Michel. "Optimisation du placement des scans et des réductions pour machines parallèles à mémoire répartie". Versailles-St Quentin en Yvelines, 1998. http://www.theses.fr/1998VERS0001.
Texto completo da fonteNovytskyi, Dimitri. "Méthodes géométriques pour la mémoire et l'apprentissage". Phd thesis, Université Paul Sabatier - Toulouse III, 2007. http://tel.archives-ouvertes.fr/tel-00285602.
Texto completo da fonteZuckerman, Stéphane. "Méthodologie de mesure et optimisation de l'utilisation des hiérarchies mémoire dans les systèmes multicoeur". Versailles-St Quentin en Yvelines, 2010. http://www.theses.fr/2010VERS0063.
Texto completo da fonteMicroprocessors embedding multicore technology are nowadays the new building blocks of computation nodes for supercomputers. To the classic instruction-level parallelism found in every modern microprocessor, task-level parallelism is now added. The most critical shared ressource – memory – becomes even more critical with the advent of shared caches between multiple cores. This dissertation proposes to give methodological leads to determine where the bottlenecks are situated in a system built on multicores chips, as well as caracterize some problems specific to multicore. Among them, one can find in particular the contention in cache hierarchies : RAM, and last level of cache. The presence of prefetch mechanisms can also lead to cacheline stealing. It can deeply hurt performance in compute- and memory-intensive applications manipulating complex data structures such as multidimensional arrays. Finally, based on optimized building blocks for unicore execution in matrix computations, we propose a methodology to determine the best partitioning to get acceptable performance in a multicore environment
Livros sobre o assunto "Optimisation mémoire"
Oracle 10g: Optimisation d'une base de données, ressources adaptées, mémoire ajustée, performances accrues, requêtes optimisées. Nantes: Editions Eni, 2006.
Encontre o texto completo da fonteGhoche, François. MS-DOS 5. Synthèse: Version 5.0 ; quoi de neuf?, installation et optimisation, disques et fichiers, organisation de la mémoire, les commandes de toutes les versions. Paris: Eyrolles, 1992.
Encontre o texto completo da fonte