Teses / dissertações: "NPC Design"

1

Gaudl, Swen. "Design and refinement of NPC rules in digital board games". [Ilmenau] [Univ.-Bibliothek], 2009. http://d-nb.info/995970564/34.

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2

Washburn, Megan E. "Dynamic Procedural Music Generation from NPC Attributes". DigitalCommons@CalPoly, 2020. https://digitalcommons.calpoly.edu/theses/2193.

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Procedural content generation for video games (PCGG) has seen a steep increase in the past decade, aiming to foster emergent gameplay as well as to address the challenge of producing large amounts of engaging content quickly. Most work in PCGG has been focused on generating art and assets such as levels, textures, and models, or on narrative design to generate storylines and progression paths. Given the difficulty of generating harmonically pleasing and interesting music, procedural music generation for games (PMGG) has not seen as much attention during this time. Music in video games is essential for establishing developers' intended mood and environment. Given the deficit of PMGG content, this paper aims to address the demand for high-quality PMGG. This paper describes the system developed to solve this problem, which generates thematic music for non-player characters (NPCs) based on developer-defined attributes in real time and responds to the dynamic relationship between the player and target NPC. The system was evaluated by means of user study: participants confront four NPC bosses each with their own uniquely generated dynamic track based on their varying attributes in relation to the player's. The survey gathered information on the perceived quality, dynamism, and helpfulness to gameplay of the generated music. Results showed that the generated music was generally pleasing and harmonious, and that while players could not detect the details of how, they were able to detect a general relationship between themselves and the NPCs as reflected by the music.

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3

Graff, Lukas. "How narrative techniques affect players' engagement in action RPG Dark Souls II". Thesis, Uppsala universitet, Institutionen för speldesign, 2018. http://urn.kb.se/resolve?urn=urn:nbn:se:uu:diva-355846.

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The purpose of the study was to get a better understanding of how players’ engagement is affected by the narrative techniques which are used in the game Dark Souls II. The four most prominent narrative techniques that were analyzed in Dark souls II were cutscenes, item descriptions, NPC’s and environmental storytelling. Qualitative and Quantitative data was collected in a questionnaire that was posted on the forum/ “subreddit” Dark souls II. The answers from 100 questionnaires were analyzed using content analysis methodology. It could be concluded in this thesis that narrative techniques that interfere with the players sense of freedom will reduce their engagement within the game. An example in Dark souls II is when the player is forced to summon NPC’s to boss fights in order to progress in the NPC’s storyline. This also works the other way around: i.e. the player experiences increased engagement if the narrative techniques allow the player to decide over their own actions. An example in Dark Souls II is when the player is given the opportunity to kill friendly NPC’s.
Syftet med denna studie var att få en bättre förståelse för hur spelarens engagemang påverkas av de narrativa tekniker som används i spelet Dark Souls II. De fyra mest framstående narrativa tekniker som identifierades i Dark Souls II var Cutscenes, föremålsbeskrivningar, NPC’s och miljöberättande. Kvalitativ och kvantitativa data samlades genom en enkät som lades upp på Dark Souls II forum/ ”subreddit”. Svaren från 100 deltagare tolkades med koder samt kategorier genom metodologin innehållsanalys. I denna studie kunde det konstateras att narrativa tekniker som negativt påverkar spelarens frihet, kommer reducera deras engagemang i spelet. Detta noterades bland annat när spelare var tvungna att kalla på NPC’s till bossfighter för att kunna fortsätta denna NPC’s uppdrag. Det angavs även att detta fungerade åt andra hållet, när spelarens förmåga att kunna ta egna beslut tilläts så ökade även spelarens engagemang i spelet. Detta noterades i spelmekaniken att spelaren bland annat tilläts döda fredliga NPC’s.

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4

Marzouk, Mounir. "Développement de chargeurs intégrés pour véhicules hybrides plug-in". Thesis, Université Grenoble Alpes (ComUE), 2015. http://www.theses.fr/2015GREAT088/document.

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Ces travaux de thèse consistent en la conception et la réalisation d’une chaîne de tractionintégrée pour véhicule hybride plug-in. L’étude s’oriente vers une solution de convertisseur mutualisé,dans l’objectif de partager la traction et les modes chargeurs de batteries, la structure en NPC à 3niveaux est retenue. Le chargeur monophasé se base une topologie de redresseur à MLI monophaséavec trois bras entrelacés, avec l’utilisation des enroulements du moteur pour le filtrage. En chargeurtriphasé nous adaptons la topologie pour réaliser un montage en double boost triphasé. Pour chaqueconfiguration, les passifs sont dimensionnés pour répondre aux contraintes en courant BF et HF. Lecontrôle adopté se base sur les correcteurs résonants. Enfin, un prototype de 5 kW a été réalisé pourvalider les différents modes de l’application.Dans une seconde partie, nous proposons une solution de chargeur isolé sans étage continu auprimaire à double ponts actifs (DAB). La topologie est modélisée au premier harmonique et unecommande assurant l’absorption sinusoïdale est étudiée. Une configuration isolée triphasée permetl’accès aux puissances plus élevées ainsi que la réduction des ondulations de courant BF en sortie
This thesis consists on the design and realization of a plug-in hybrid vehicle integrated tractiondrive supply. The work turns to a solution of a mutualized converter, in the objective to imagine asolution which shared drive and battery chargers modes, the three-level NPC topology has beenretained. The single phase charger is based on an interleaved PWM rectifier, and motor windings areused as smoothing inductors. A double-boost PFC configuration is introduced to ensure the threephasecharger. Passives are sized in each configuration in order to take in account the whole currentconstraints (LF and HF). The PFC behavior is based on the resonant controllers. Then, a 5 kWprototype has been realized to validate the different application modes.In a second part, a single-stage isolated charger based on a Dual-Active-Bridge (DAB) isproposed. The topology is modeled to the fundamental and the PFC control law is studied. A threephaseconfiguration is simulated in order to achieve higher charging powers and to reduce batterycurrent low-frequency ripple

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5

Roca, Pérez Antoni. "Floorplan-Aware High Performance NoC Design". Doctoral thesis, Universitat Politècnica de València, 2012. http://hdl.handle.net/10251/17844.

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Las actuales arquitecturas de m�ltiples n�cleos como los chip multiprocesadores (CMP) y soluciones multiprocesador para sistemas dentro del chip (MPSoCs) han adoptado a las redes dentro del chip (NoC) como elemento -ptimo para la inter-conexi-n de los diversos elementos de dichos sistemas. En este sentido, fabricantes de CMPs y MPSoCs han adoptado NoCs sencillas, generalmente con una topolog'a en malla o anillo, ya que son suficientes para satisfacer las necesidades de los sistemas actuales. Sin embargo a medida que los requerimientos del sistema -- baja latencia y alto rendimiento -- se hacen m�s exigentes, estas redes tan simples dejan de ser una soluci-n real. As', la comunidad investigadora ha propuesto y analizado NoCs m�s complejas. No obstante, estas soluciones son m�s dif'ciles de implementar -- especialmente los enlaces largos -- haciendo que este tipo de topolog'as complejas sean demasiado costosas o incluso inviables. En esta tesis, presentamos una metodolog'a de dise-o que minimiza la p�rdida de prestaciones de la red debido a su implementaci-n real. Los principales problemas que se encuentran al implementar una NoC son los conmutadores y los enlaces largos. En esta tesis, el conmutador se ha hecho modular, es decir, formado como uni-n de m-dulos m�s peque-os. En nuestro caso, los m-dulos son id�nticos, donde cada m-dulo es capaz de arbitrar, conmutar, y almacenar los mensajes que le llegan. Posteriormente, flexibilizamos la colocaci-n de estos m-dulos en el chip, permitiendo que m-dulos de un mismo conmutador est�n distribuidos por el chip. Esta metodolog'a de dise-o la hemos aplicado a diferentes escenarios. Primeramente, hemos introducido nuestro conmutador modular en NoCs con topolog'as conocidas como la malla 2D. Los resultados muestran como la modularidad y la distribuci-n del conmutador reducen la latencia y el consumo de potencia de la red. En segundo lugar, hemos utilizado nuestra metodolog'a de dise-o para implementar un crossbar distribuid
Roca Pérez, A. (2012). Floorplan-Aware High Performance NoC Design [Tesis doctoral no publicada]. Universitat Politècnica de València. https://doi.org/10.4995/Thesis/10251/17844
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6

Hua, Yin. "NFC-Enable System Design in Wireless SensorNetwork". Thesis, KTH, Skolan för informations- och kommunikationsteknik (ICT), 2013. http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-120075.

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Wireless Sensor Network (WSN) have the potential to greatly affect every part of industrial and people’s lifestyle. For this reason, iPack VINN Excellence Center contributes to wireless tracking platform for fresh food and lifestyle. Every new idea or technology is attempted to integrate to the WSN for more efficient, better user experience and lower power consumption. Meanwhile Near Field Communication (NFC), a short-range wireless connectivity technology, which can make communication easily,safety and intuitively arousing iPack interest. So this master thesis focus on integrating NFC technology into existing systems to build a NFC-enable Wireless Sensor Network system. And with thissystem, only one simple touch, data from sensor node can be transmitted to mobile phone or tablet. Furthermore parameters of sensor node also can be configured easily by using above devices. So basically the NFC peer-to-peer communication protocol is mainly used. To implement and test the functions of the demonstration, a sets of hardware is needed to chosen and bought. How to design the system without changing old WSN is very tricky. To design a NFC adapter which can connect existing WSN with NFC part is thesolution of this thesis. So the main task was designing a NFC adapter which could be connected with either mobile phone/tablet or sensor node. It was the NFC adapter that makes mobile phone/tablet or sensor node NFC enabled. For the connection method, the high speed UART interface was chosen to connect with sensor node. The architecture of NFC adapter includes two main parts, A NFC chip (PN532) from NXP and a MCU(VNC2) from FTDI. The PN532 uses its antenna to send or receive data with different NFC protocols. The VNC2 is used to store sensor collected data and sends command though UART to control the PN532. Learning to use the PN532 was a tough task during the thesis work. Both official manuals and demo application are helpful for understanding the PN532 controlling. In addition, We analysed the sniffer data from demo application and code from NXP software design kit (SDK). which helped us to know the process of the PN532 peer-to-peer communication. After learning from official application, user manual and monitoring software/hardware design kid applications, we began to design our own hardware suitable SDK for the NFC adapter. At first we connected the hardware parts. When hardware connection was ready, we wrote and tested the firmware for VNC2 platform. Then due to the reason that Windows is more stable than our build VNC2 platform system at that moment, we wrote our own software design kid for NFC adapter under Windows OS first. The basic idea of software design kid is easy to use, modify and integrate into any other platforms. At the end of the thesis project, we integrated our own SDK into VNC2. When integration was done, a lot of stability and performance validation were done. Based on the result of testing, we optimized and modified our SDK and tested it again. This thesis project basically handles out a new ideal of integrating NFC to existing wireless sensor network to make WSN NFC enable. To prove the idea, we made a demo to show the enhanced sensor node and the results are satisfied. However there still has a lot of works and a lot of improvement should can be done in the future.

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7

Ellrick, Daniel A. "An antenna design for PANSAT using NEC". Thesis, Monterey, California. Naval Postgraduate School, 1991. http://hdl.handle.net/10945/27985.

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8

Hamwi, Khawla. "Low Power Design Methodology and Photonics Networks on Chip for Multiprocessor System on Chip". Thesis, Brest, 2013. http://www.theses.fr/2013BRES0029.

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Les systèmes multiprocesseurs sur puce (MPSoC)s sont fortement émergent comme principaux composants dans les systèmes embarqués à hautes performances. La principale complexité dans la conception et l’implémentation des MPSoC est la communication entre les cœurs. Les réseaux sur puce (NoC) sont considérés comme la solution pour cet effet. ITRS prédit que des centaines de cœurs seront utilisées dans la génération future de système sur puce (SoC), ce qui va donc augmenter les coûts de l’évolutivité, de bande passante et de l’implémentation des réseaux sur puce (NoC)s. Ces problèmes sont présents dans diverses tendances technologiques dans le domaine des semiconducteurs et de la photonique. Cette thèse préconise l'utilisation de la synthèse NoC comme l'approche la plus appropriée pour exploiter ces tendances technologiques et rattraper les exigences des applications. A partir de plusieurs méthodologies de conception basées sur la technologie FPGA et des techniques d'estimation basse énergie (HLS) pour plusieurs IPs, nous proposons une implémentation ASIC basée sur la technologie 3D Tezzaron. Multi-FPGA technologie est utilisée pour valider la conception MPSoC avec 64 processeurs Butterfly NoC. La synthèse NoC est basée sur le regroupement de maîtres et d’esclaves générant des architectures asymétriques avec un soutien approprié pour les demandes très haut débit par optique NoC (ONoC), tandis que les demandes de bande passante inférieure sont traitées par électronique NoC. Une programmation linéaire est proposée comme une solution pour la synthèse NoC
Multiprocessor systems on chip (MPSoC)s are strongly emerging as main components in high performance embedded systems. Several challenges can be determined in MPSoC design like the challenge which comes from interconnect infrastructure. Network-on-Chip (NOC) with multiple constraints to be satisfied is a promising solution for these challenges. ITRS predicts that hundreds of cores will be used in future generation system on chip (SoC) and thus raises the issue of scalability, bandwidth and implementation costs for NoCs. These issues are raised within the various technological trends in semiconductors and photonics. This PhD thesis advocates the use of NoC synthesis as the most appropriate approach to exploit these technological trends catch up with the applications requirements. Starting with several design methodologies based on FPGA technology and low power estimation techniques (HLS) for several IPs, we propose an ASIC implementation based on 3D Tezzaron technology. Multi-FPGA technology is used to validate MPSoC design with up to 64 processors with Butterfly NoC. NoC synthesis is based on a clustering of masters and slaves generating asymmetric architectures with appropriate support for very high bandwidth requests through Optical NoC (ONoC) while lower bandwidth requests are processed by electronic NoC. A linear programming is proposed as a solution to the NoC synthesis

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9

Dasgupta, Mitul. "Design Against Stress: Design's methodological approach of dealing with the issue of stress". University of Cincinnati / OhioLINK, 2010. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1282317515.

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10

Renangi, Karteek. "Analysis of Cache Networking by NoC and Segmented Bus". University of Cincinnati / OhioLINK, 2008. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1226862238.

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11

Silva, Gustavo Girão Barreto da. "Resource-aware clustering design for NoC-based MPSoCs". reponame:Biblioteca Digital de Teses e Dissertações da UFRGS, 2014. http://hdl.handle.net/10183/95984.

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Atualmente, o paradigma multicore é uma tendência fortemente estabelecida também na área de sistemas embarcados. O grau de paralelismo provido por tal arquitetura tem sido a principal causa de avanços de performance na área além de economia de energia e potência. Entretanto, para obter paralelismo eficiente desta arquitetura não é uma tarefa simples. Assim, desenvolvedores propuseram diversos modelos de ambientes de programação tentando prover o máximo de transparência possível. No nível do hardware, este crescente aumento no número de componentes dentro chip cria um problema de gerenciamento a ser tratado. No contexto deste cenário complexo, esta tese propõe o uso de abordagens de gerenciamento de recursos para aumentar a eficiência, levando em consideração tanto performance quanto consumo de energia, de ambientes MPSoC em diferentes níveis. Além disso, estas abordagens tem em comum a noção de clusterização, a qual tenta agregar recursos logicamente de acordo com as demandas da aplicação. Primeiramente no nível do processador/aplicação, é proposto um hardware dinamicamente adaptável para suportar modelos de programação paralelos distintos sem nenhum sobrecusto computacional uma vez que todo o processo é completamente transparente para o programador. Ainda neste ambiente, onde aplicações distintas podem ser executadas, é proposto um mecanismo de escalonamento visando gerenciamento de recursos para aumentar a performance chamado Processor Clustering. São propostas quatro diferentes políticas de mapeamento de recursos que tiram vantagem de aspectos distintos da natureza paralela das aplicações e das restrições arquiteturais do sistema. Entretanto, algumas aplicações tem demandas de memória mais altas do que demandas computacionais. Logo, uma abordagem similar pode ser utilizada no nível da hierarquia de memória. Neste caso, o objetivo é redistribuir recursos de memória de acordo com as demandas da aplicação. Redistribuição de memória é explorada tanto em tempo de projeto quanto em tempo de execução. Um mecanismo de mapeamento de distribuição é proposto baseado na quantidade de requisições de acesso à memória externa. Finalmente, é proposto um mecanismo de tolerância à falhas baseado em gerenciamento de recursos para memórias distribuídas dentro do chip em NoCs. É introduzido um modelo de Reliability Clustering que tira proveito da infraestrutura da NoC. Neste caso, os roteadores tem conhecimento dos blocos com falhas e blocos redundantes. Baseado neste conhecimento, o mecanismo é capaz evitar altas latências de acesso à memória.
The multicore paradigm is a solid trend nowadays, also in the field of embedded systems. The degree of parallelism provided by such architecture has been the foundation of performance advancements in the field as well as for power and energy savings. However, to obtain efficient parallelism of such architecture is not an easy task. Therefore, developers come up with several proposals of programming environments trying to provide as much transparency as possible. On the hardware side, this increasing number of on-chip components creates a management issue to be handled. In the context of this complex scenario this thesis proposes the use of resource management approaches to improve the efficiency, regarding both performance and energy consumption, of MPSoC environments at different levels. Also, these approaches have in common the notion of clustering, which tries to logically aggregate resources according to application demands. First, at the processor/application level, we propose a dynamically adaptable hardware to support distinct parallel programming models at no computational overhead, since the entire process is completely transparent to the programmer. Also, in this environment, where distinct applications can be executed, we propose a resource-aware scheduling mechanism to improve performance named Processor Clustering. We propose four different resource mapping policies that leverage on distinct aspects of the parallel nature of the applications and on architecture constraints. However, some applications have higher memory demands than computational demands. Therefore, a similar approach can be used at the memory level. In this case, we aim at redistributing memory resources according to application demands. We explore memory redistribution at both design time and runtime and propose a distribution mapping mechanism based on the amount of off-chip memory requests. Finally, we propose a resource-aware fault-tolerance mechanism for distributed on-chip memories in NoCs. We introduce a Reliability Clustering model that leverages on the NoC infrastructure. In this case, the routers have knowledge of faulty blocks and redundancy blocks and, based on that, they are able to avoid higher memory access latency.

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12

Hamwi, Khawla. "Low Power Design Methodology and Photonics Networks on Chip for Multiprocessor System on Chip". Electronic Thesis or Diss., Brest, 2013. http://www.theses.fr/2013BRES0029.

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Les systèmes multiprocesseurs sur puce (MPSoC)s sont fortement émergent comme principaux composants dans les systèmes embarqués à hautes performances. La principale complexité dans la conception et l’implémentation des MPSoC est la communication entre les cœurs. Les réseaux sur puce (NoC) sont considérés comme la solution pour cet effet. ITRS prédit que des centaines de cœurs seront utilisées dans la génération future de système sur puce (SoC), ce qui va donc augmenter les coûts de l’évolutivité, de bande passante et de l’implémentation des réseaux sur puce (NoC)s. Ces problèmes sont présents dans diverses tendances technologiques dans le domaine des semiconducteurs et de la photonique. Cette thèse préconise l'utilisation de la synthèse NoC comme l'approche la plus appropriée pour exploiter ces tendances technologiques et rattraper les exigences des applications. A partir de plusieurs méthodologies de conception basées sur la technologie FPGA et des techniques d'estimation basse énergie (HLS) pour plusieurs IPs, nous proposons une implémentation ASIC basée sur la technologie 3D Tezzaron. Multi-FPGA technologie est utilisée pour valider la conception MPSoC avec 64 processeurs Butterfly NoC. La synthèse NoC est basée sur le regroupement de maîtres et d’esclaves générant des architectures asymétriques avec un soutien approprié pour les demandes très haut débit par optique NoC (ONoC), tandis que les demandes de bande passante inférieure sont traitées par électronique NoC. Une programmation linéaire est proposée comme une solution pour la synthèse NoC
Multiprocessor systems on chip (MPSoC)s are strongly emerging as main components in high performance embedded systems. Several challenges can be determined in MPSoC design like the challenge which comes from interconnect infrastructure. Network-on-Chip (NOC) with multiple constraints to be satisfied is a promising solution for these challenges. ITRS predicts that hundreds of cores will be used in future generation system on chip (SoC) and thus raises the issue of scalability, bandwidth and implementation costs for NoCs. These issues are raised within the various technological trends in semiconductors and photonics. This PhD thesis advocates the use of NoC synthesis as the most appropriate approach to exploit these technological trends catch up with the applications requirements. Starting with several design methodologies based on FPGA technology and low power estimation techniques (HLS) for several IPs, we propose an ASIC implementation based on 3D Tezzaron technology. Multi-FPGA technology is used to validate MPSoC design with up to 64 processors with Butterfly NoC. NoC synthesis is based on a clustering of masters and slaves generating asymmetric architectures with appropriate support for very high bandwidth requests through Optical NoC (ONoC) while lower bandwidth requests are processed by electronic NoC. A linear programming is proposed as a solution to the NoC synthesis

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13

Noronha, Eduardo Jorge Henriques. "Integração vertical do design na indústria: redesenho do produto, da comunicação e do serviço da NCP". Doctoral thesis, Universidade de Aveiro, 2017. http://hdl.handle.net/10773/21543.

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Design
O projeto de tese de doutoramento em design “Integração Vertical do Design na Indústria: redesenho do produto, da comunicação e do serviço na NCP”, integrado no Programa Doutoral em Design da Universidade de Aveiro (iniciada em outubro de 2012), foi desenvolvido pelo designer Eduardo Noronha em laboratório empresarial, tendo decorrido da cooperação entre a indústria metalomecânica de Águeda NCP (Fabrico de Produtos Metálicos S.A.) e a Universidade de Aveiro, projeto esse que a FCT validou pela atribuição de uma BDE (Bolsa de Doutoramento em Empresa). Esta investigação teve por base o interesse pessoal do investigador em compreender e explorar a gestão do Design como fator de incremento da competitividade no tecido empresarial, em desenvolver a comunicação como condição de valorização da marca e da promoção da inovação, assumindo o papel do Designer enquanto agente mediador na concepção de bens transacionáveis e de estratégias empresariais de sustentação e crescimento económico, com base na antecipação e desenho do futuro do consumo. Na resposta à questão: _Como potenciar ou garantir o futuro da NCP através do design? Considerou-se o conhecimento disponível sobre a gestão do design, convertendo-o na integração vertical do Design na organização NCP, nomeadamente nos seus três níveis: ao nível da produção – design Industrial; ao nível da marca – design de comunicação; ao nível da investigação – design estratégico. Nesse sentido foi projetado um novo sistema de bancada retráctil, uma nova marca e sistema retórico de comunicação, assim como um novo serviço interno de investigação em Design. Reconheceu-se, no entanto, que o objetivo de alcançar o estádio de excelência na gestão do design, só será possível através da inovação radical (semântica e sintática) que lhe conferirá não só a liderança da oferta como o desenho de novos mercados.
The project of doctoral thesis "Vertical Integration of Design in Industry: Redesign of Product, Communication and Service of NCP", integrated in the Doctoral Program in Design of the University of Aveiro (started in October 2012), was developed by the designer Eduardo Noronha in a business laboratory. This was followed by the cooperation between the mechanical engineering company of Águeda NCP (Fabrico de Produtos Metálicos SA) and the University of Aveiro, project validated by the FCT that awarding a BDE (Doctoral Degree Grant in company). This research is based on a personal interest to explore and understand the Design management as a factor of increased of competitiveness in the business world, develop communication as a condition for enhancing the brand and promoting innovation, assuming the role of the Designer as a mediating agent in the conception of tradable goods and business strategies for support and economic growth, based on the anticipation and design of the future of consumption. In the answer to the question: _How to enhance or guarantee the future of the NCP through design? Was considered the available knowledge about design management, converting it into the vertical integration of Design in the NCP, namely in its three levels: at the production level - Industrial design; at the brand level - communication design; at the research level - strategic design. In this sense, a new retractable workbench system, a new branding and rhetorical communication system was designed, as well as a new internal design research service. It was recognized, however, that the goal of achieving the stage of excellence in design management will only be possible through radical innovation (semantic and syntactic) that will give it not only the leadership of the offer as the design of new markets.

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14

Kabir, Ziaul. "User Centric Design of an NFC Mobile Wallet Framework". Thesis, KTH, Skolan för informations- och kommunikationsteknik (ICT), 2011. http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-37229.

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Near Field Communication (NFC) among various other things, allows end-users to enjoy contactless mobile services such as credit cards, transport tickets, office access etc. using NFC mobile phones. Such services are placed as software applications inside the secure-chip hardware of the NFC phone – often termed as a Secure Element (SE). Bringing these contactless smart-card services into mobile phones raises the need to allow the end-users to interact and control the information and the communication with secure-chip applications. The display of a mobile phone can easily allow such functionalities as graphical user interface applications. This thesis terms such applications as NFC mobile wallet applications where a mobile wallet is the container for all of these applications. A mobile wallet application for a single service is intended to be used on various phone platforms and often there is a need to keep the consistency and uniform functionalities between the designs. Primarily, this thesis aims to provide the means for the service providers (and for the developers) to design and develop one single wallet application for a particular NFC service and deploy it on various phone platforms using the support of a wallet framework. In order to achieve that, this thesis aims to identify a minimal but adequate set of user interaction functionalities for the mobile wallet services and include their support in the wallet framework. Due to time constraints, only three NFC services: payment, access control, and transport were investigated. Then a lightweight wallet framework was designed that includes support to implement the identified user interaction functionalities as a set of application programming interfaces (APIs) to develop interoperable wallet applications. There were complexities while designing the framework, for example, limited NFC supports on various phone platforms at this writing; however, the thesis achieved the desired goals at the end. Two prototype wallet applications were developed on the basis of the identified minimal functionalities and the wallet framework support. Usability testing was conducted for the prototypes to find usability issues and the applicability of the functionalities in the wallet interface. The result was very positive; the users had little trouble interacting with the wallet applications. Several recommendations were noted from the usability testing mainly on navigating the interface and consistency in the design, which are summarized for the developers as guidelines to develop wallet applications.

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15

Malmström, Mikael. "Design and Implementation of NFC-based gym mobile app". Thesis, Linköpings universitet, Institutionen för datavetenskap, 2015. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-123291.

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This report investigates the technical and economic viability of introducing a Near Field Communication (NFC) client system in a gym environment. The system aims to aid the customers with logging their workout, retrieving information regarding exercises as well as enhancing the attendance control for both staff and customers. To identify what information to be presented, the most important quality factors and what functionalities are most desired, an exploratory case study was conducted. The study showed that there is a discrepancy between the desire to log ones workout and actually doing it. Most people want to keep track of how they workout, but despite the wide variety of workout applications on the market, they choose not to use them. The main concern expressed was that the logging needs to be fast and easy, indicating that the existing apps do not fulfill the ease of use desired. The system presented in this report is coupled to the gym where NFC tags pair an exercise to its corresponding logger and information in the application. The ability for the gym to track its customers’ workout habits is a rare feature that provides several economic benefits such as targeted advertisement, better maintenance control and new customer services analyzing their workout. For the system to be effective the customers need to use the system and log their workout, therefore it needs to be supported by the major mobile platforms. To accommodate this a hybrid platform approach using PhoneGap was used. This approach allows for development in one language that translates into native embedded web applications. At the time of writing Apple’s latest models do include the hardware for NFC communication. However, it is not possible to develop a custom NFC application for iPhone yet. By adopting the hybrid approach there is no need to create a whole new app when they do release the rights to do so. In conclusion, the technical viability of the NFC based system comes with the tradeoffs of dealing with the lack of standards of a new technology and being early on the market with a new feature. This calls for some custom solutions, since each platform adopts their own way of NFC implementation, but is manageable. The economic aspects are tied to the use of the system where the ease of use is the key factor for the customers. The end user tests indicate that NFC provides that small advantage over traditional workout applications needed to make logging attractive.

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Carlsson, Erik. "Underwater Communications System with Focus on Antenna Design". Thesis, Linköpings universitet, Elektroniska Kretsar och System, 2015. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-121481.

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In this thesis the possibility of building an underwater communication system usingelectromagnetic waves has been explored. The focus became designing and testingan antenna even if the entire system has been outlined as well. The conclusion isthat using magnetically linked antennas in the near field it is a very real possibilitybut for long EM waves in the far field more testing needs to be done. This isbecause a lack of equipment and facilitates which made it hard to do the realworld testing for this implementation even if it should work in theory.

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Hernández, Luz Carles. "Addressing Manufacturing Challenges in NoC-based ULSI Designs". Doctoral thesis, Universitat Politècnica de València, 2012. http://hdl.handle.net/10251/16694.

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Hernández Luz, C. (2012). Addressing Manufacturing Challenges in NoC-based ULSI Designs [Tesis doctoral no publicada]. Universitat Politècnica de València. https://doi.org/10.4995/Thesis/10251/16694
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18

Ost, Luciano Copello. "Abstract models of NoC-based MPSoCs for design space exploration". Pontifícia Universidade Católica do Rio Grande do Sul, 2010. http://hdl.handle.net/10923/1663.

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Made available in DSpace on 2013-08-07T18:43:30Z (GMT). No. of bitstreams: 1 000425177-Texto+Completo-0.pdf: 2930765 bytes, checksum: 146324f55fdecec85040eaa6120e58f4 (MD5) Previous issue date: 2010
NoC-based MPSoCs can provide massive computing power on a single chip, achieving hundreds of billions of operations per second by employing dozens of processing cores that communicate over a packet-switched network at a rate that exceeds 100 Tbps. Such devices can support the convergence of several appliances (e. g. HDTV, multiple wireless communication standards, media players, gaming) due to their comparatively high performance, flexibility and power efficiency. Due to the vast design space alternatives, evaluating the NoC-based MPSoCs at lower abstraction levels does not provide the required support to find out the most efficient NoC architecture considering the performance constraints (e. g. latency, power) of a given application at early design process stages. Thus, NoC-based MPSoCs design requires simple and accurate high level models in order to achieve precise performance results, of each design alternative, in an acceptable design time. In this context, the present Thesis has two main contributions: (i) development of abstract NoC models, providing accurate performance evaluation; and (ii) integration of the proposed models into a model-based design flow, allowing the design space exploration of NoC-based MPSoCs at early stages of the design flow.
MPSoCs baseados em NoCs podem fornecer alto desempenho em um único circuito integrado, atingindo centenas de bilhões de operações por segundo através do emprego de múltiplos elementos de processamento que se comunicam através de uma NoC operando a uma freqüência que excede 100 Tbps. Tais dispositivos podem suportar a execução simultânea de múltiplas aplicações (e. g. HDTV, múltiplos padrões de comunicação sem fio, tocadores multimídia, jogos), devido a características como alto desempenho, flexibilidade e eficiência em termos de consumo de energia. Devido a quantidade de alternativas inerentes ao grande espaço de projeto, a avaliação de MPSoCs baseados em NoCs em baixo níveis de abstração não prove o suporte necessário para encontrar a melhor arquitetura para a NoC considerando métricas de desempenho (e. g. latência, potência) de uma dada aplicação nas fases iniciais de projeto. Dessa forma, o projeto de MPSoCs baseados em NoCs requer modelos simples e precisos em alto nível de abstração, os quais possam gerar resultados precisos de desempenho, de cada alternativa de projeto, em um tempo de projeto razoável. Neste contexto, a presente Tese tem duas contribuições principais: (i) desenvolvimento de modelos de NoC abstratos, e (ii) integração dos modelos propostos dentro de um fluxo de projeto baseado em modelos, permitindo assim a exploração do espaço de projeto de MPSoCs baseados em NoCs nas fases iniciais do fluxo projeto.

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Kilpeläinen, R. (Riikka). "Usability test design for a NFC-based seamless learning tool". Master's thesis, University of Oulu, 2015. http://urn.fi/URN:NBN:fi:oulu-201504171408.

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As mobile technologies and social media are being integrated more and more to current educational practices, the notion of seamless learning has become important. Seamless learning enables learning across different contexts whenever the students are stimulated to learn. The main motivation behind seamless learning is to encourage the students to switch from one learning context into another easily with the help of a personal device as a mediator. In the most common case this device is a smartphone. One challenge for wider seamless learning adoption is the lack of efficient tools with which teachers could create educational content that is more suitable for seamless learning. To address this challenge, the Interactive Spaces research group at the University of Oulu is implementing an editing tool, called NFC-ACT, with which teachers can create NFC based educational games and exercises for the students. Near Field Communication (NFC) is a short range wireless communication technology in which the devices initiate communication automatically once they are in close proximity. NFC is most commonly used in mobile phones. Thus NFC is a suitable technology for seamless learning applications. In order to test the usability, usefulness and efficiency of NFC-ACT, this thesis presents a detailed usability testing plan for NFC-ACT. With thorough usability testing with teachers as test participants, the most critical usability issues with NFC-ACT can be revealed. In addition, the aim of the usability testing is to study the need for such editing tools. This thesis consists of two parts. The first part is a comprehensive literature review about usability and seamless learning research. Then, the second part presents the current state of the application and goes through in detail the usability testing plan for NFC-ACT. Based on the literature review, the selected methodology for usability testing is an adapted combination of cooperative usability testing and SUXES method. In addition, the testing plan is constructed in a way that it takes into account the results from previously held usability demo sessions that already shed some light on the most critical usability issues with NFC-ACT. The resulted usability testing plan will be put into use once the implementation for NFC-ACT is ready
Mobiiliteknologiat ja sosiaalinen media ovat integroitumassa yhä enemmän valitseviin opetuskäytäntöihin, minkä myötä saumaton oppiminen on noussut tärkeäksi käsitteeksi. Saumaton oppiminen mahdollistaa oppimisen eri konteksteissa milloin tahansa silloin kun oppilaat ovat stimuloituneita oppimaan. Päämotivaatio saumattoman oppimisen takana on kannustaa oppilaita vaihtamaan oppimiskontekstista toiseen mahdollisimman joustavasti käyttäen hyväksi eri laitteita. Tätä nykyä yleisin tällainen vaihdot mahdollistava laite on älypuhelin. Eräs haaste laajemmalle saumattoman oppimisen omaksumiselle on tehokkaiden työkalujen puute, joiden avulla opettajat voisivat tehdä paremmin saumattomaan oppimiseen soveltuvaa opetusmateriaalia. Oulun yliopiston Interactive Spaces -tutkimusryhmä onkin kehittämässä tähän tarpeeseen editointityökalua nimeltään NFC- ACT, jonka avulla opettajat voivat luoda NFC-pohjasia pelejä ja tehtäviä oppilaille. NFC (Near Field Communication) on lyhyen kantomatkan langaton kommunikointiteknologia, missä laitteet muodostavat automaattisesti yhteyden heti kun ne ovat lähellä toisiaan. Koska NFC:tä käytetään yleisesti matkapuhelimissa, on se sopiva teknologia saumattomaan oppimiseen. Tämä diplomityö esittelee yksityiskohtaisen käytettävyystestaussuunnitelman NFC-ACT:lle, jotta sen käytettävyyttä, hyödyllisyyttä ja tehokkuutta voitaisiin testata. Perusteellisella käytettävyystestauksella opettajien toimiessa testikäyttäjinä työkalun kriittisimmät käytettävyysongelmat voidaan paikallistaa. Lisäksi käytettävyystestauksen tavoitteena on tutkia millainen tarve tällaisille editointi-työkaluille on. Tämä työ koostuu kahdesta osasta. Ensimmäinen osa on kattava selostus käytettävyyteen ja saumattomaan oppimiseen liittyvästä tutkimuksesta. Toinen osa esittelee työkalun nykyisen tilan sekä käy läpi yksityiskohtaisesti käytettävyystestaussuunnitelman. Ensimmäisen osan kirjallisen katsauksen pohjalta käytettävyystestauksen metodiksi muodostui kombinaatio, joka yhdistelee yhteistyökäytettävyystestausta ja SUXES-menetelmiä. Lisäksi testaussuunnitelma ottaa huomioon tulokset NFC-ACT:lle aiemmin järjestetyistä käytettävyysdemoista, jotka jo osaltaan antoivat suuntaa työkalun kriittisimmistä käytettävyysongelmista. Esitelty käytettävyystestaussuunnitelma on tarkoitus ottaa käyttöön heti, kun NFC-ACT:n toteutus on valmis

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Gawell, Elin, e Maria Hedvall. "Att designa en produkt för vuxna med ADHD och/eller autismspektrumtillstånd". Thesis, Linköpings universitet, Interaktiva och kognitiva system, 2016. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-129614.

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Att leva som vuxen med diagnosen attention deficit hyperactivity disorder, ADHD, och/eller autismspektrumtillstånd, AST, kan vara en utmaning i vardagen. För att kunna hjälpa dem i deras vardag har därför ett produktkoncept tagits fram som löser ett vardagligt problem. De erhållna erfarenheterna från utvecklandet av produktkonceptet har sammanställts på ett sätt så att det kan användas av andra produktutvecklare och därmed kan produkter i framtiden bli mer utvecklade för målgruppen. För att ta fram produktkonceptet har teori om diagnoserna studerats samt befintliga riktlinjer för att designa för personer med diagnoserna. Även vardagliga kognitiva hjälpmedel som finns på marknaden idag för personer med diagnoserna har studerats. Därefter har genomförandet bestått i idégenereringar, varav en med personer med diagnos eller kunskap om diagnoserna, konceptutveckling med en konceptutvärdering med personer med diagnos eller kunskap om diagnoserna, detaljdesign av valt koncept och användningstester varefter ytterligare modifikationer har kunnat göras. De slutsatser som dragits från arbetet är att det finns karaktäristiska drag för personer med diagnoserna som är relevanta vid utvecklandet av ett produktkoncept för dem. Det finns riktlinjer för design för vuxna personer med diagnos, men det är vanligare med riktlinjer för barn med diagnos. De riktlinjer som kunnat hittas är inom områdena inredningsdesign, användarcentrerad design och gränssnittsdesign. Dessa riktlinjer skapar dock inte en förståelse för individerna med diagnos utifrån både ett designperspektiv och ett psykologiskt perspektiv. Den insiktsammanställning som presenteras i det här arbetet kan användas av produktutvecklare som inte har kunskap om diagnoserna för att göra produkter mer anpassade för personer med ADHD och/eller AST i framtiden.
To live as an adult diagnosed with attention deficit hyperactivity disorder, ADHD and/or autism spectrum disorder, ASD, can be a challenge in everyday life. To help them in their daily lives, a concept that solves an everyday problem has been developed. The experience acquired from the development of the product concept have been summarized in a way that it can be used by other product developers, and thereby make products in the future more adopted to people with ADHD and/or ASD. Different areas have been studied to enable development of the concept. These areas are information about the diagnoses, guidelines to develop products for people with ADHD and ASD as well as what kind of cognitive assistive technology there is on the market for people with ADHD and ASD that is useful in their everyday life. The development process has consisted of idea generations, one of those where executed with people diagnosed with ADHD/ASD or with knowledge about the diagnoses, concept development with a concept evaluation with people diagnosed with ADHD/ASD or with knowledge about the diagnoses, detailed design of chosen concept and usability testing after which further modification has been made. The conclusion drawn from this work is that there are characteristic features of ADHD and ASD that are relevant to the development of a product concept. There are existing guidelines for designers when designing for adults with the diagnoses, but it is more common with guidelines when designing for children with these diagnoses. The guidelines that have been identified are in the areas of interior design, user centered design and interaction design. These guidelines don’t create understanding for the individuals with diagnoses regarding both a design- and a psychological perspective. The compiled insights presented in this thesis can be used by other product developers without knowledge about the diagnoses and make products more adopted to people with ADHD and/or ASD in the future.

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Zettervall, Alexandra, e Mariam Khazal. "Innovation + Design = ! : En kombination av processer". Thesis, Mälardalens högskola, Akademin för innovation, design och teknik, 2011. http://urn.kb.se/resolve?urn=urn:nbn:se:mdh:diva-12061.

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Område: Utvecklingen idag går allt snabbare vilket gör att företag behöver bli mer konkurrenskraftiga, ett sätt att bli det är genom innovation. Det kräver ett aktivt ställningstagande och ett sätt att genomföra detta är med hjälp av innovationsprocesser. Ett annat konkurrensverktyg som blir alltmer viktigt är design. Dessa två begrepp går att bryta ner i en rad faktorer och kan ses ur flera persektiv. Syfte: Syftet med denna uppsats är att förstå skillnader och likheter mellan innovations- och designprocesser samt se hur de kan komplettera varandra. Metod: Vi har använt oss av en kvalitativ metod och har genomfört intervjuer med tre olika företag. Dessa tre företag har sedan analyserats och jämförts med teori och med varandra. Teorier inom respektive område har även jämförts med varandra. Slutsatser: Vi har kommit fram till att innovations- och designprocesser kan ses som olika nivåer. Innovationsprocesser är mer övergripande kring hela organisationen och designprocesser är snarare mer detaljerad kring produktutvecklingen. Därför kan designprocesserna även sägas vara en del av innovationsprocessen, ett verktyg. Vi såg även att det fanns nio faktorer i praktiken som var viktiga för innovationsprocessen, nämligen en innovationsfrämjande organisationskultur, stödjande ledarskap, personalens delaktighet och engagemang, projektbaserad innovation, multidisciplinära team, bra kommunikation, kundinvolvering, omvärldsbevakning och utvärderingar/reflektion. Utifrån dessa slutsatser skapade vi en egen modell med inspiration från befintliga modeller.
Field: Because of the faster development today, companies need to become more competitive and one way is through innovation. It requires an active standpoint and one way to achieve this is through innovation processes. Another competitive tool that is becoming increasingly important is design. These two concepts can be broken down into a number of factors and can be viewed from several perspectives. Purpose: The purpose of this thesis is to understand similarities and differences between innovation and design processes, and to see how they can complement each other. Method: We have used a qualitative method and have conducted interviews with three different companies. These three companies have then been analyzed and compared with theory and with each other. Theories in each field have also been compared with each other. Conclusions: We have come to the conclusion that innovation and design processes can be viewed as different levels. Innovation processes are more general and about the entire organization and design processes are rather more detailed on product development. The design process can therefore also be said to be part of the innovation process, a tool. We also saw that there were nine factors in practice that were important to the innovation process, namely to foster innovation in the organizational culture, supportive leadership, staff involvement and engagement, project-based innovation, multidisciplinary teams, good communication, customer involvement, business intelligence and evaluation / reflection. Based on these findings, we created our own model, inspired by existing models.

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Castrup, Stefan. "Design of a full-sized NFC Desktop Keyboard for Smart Devices". Thesis, Högskolan i Jönköping, Tekniska Högskolan, 2015. http://urn.kb.se/resolve?urn=urn:nbn:se:hj:diva-27295.

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The master´s thesis project was performed in collaboration with the design and engineering company Eker Design from Fredrikstad in Norway, who is designing and developing flip cover NFC keyboards for smartphones. The new product idea is the full-sized NFC desktop keyboard for public institutions to offer to pupils, students or business people for instance. The thesis project is examining how such a product can be designed and should be designed in order to fit into its market and environment to meet the target group´s interest in order to be successful. With a human-centered design approach the project work was starting by the user and the market. The work consisted of analyzing and emphasizing with the market which mainly included the users, the competitors and the trends within a market analysis and a survey research. From the findings and insights of the research phase a design strategy and a business model for the new keyboard was created and communicated via a design brief. Different ideas and concepts were created, tested and presented via concept sketches along with mock-ups. The final concepts were evaluated via a concept evaluation in relation to the requirements of the business and user value. The final concept was developed and designed via the CAD software SolidWorks and the rendering software Keyshot. The design and development phase was focusing on functionality, usability, materials, surfaces, textures and the mechanical and technical solutions for the design. The result of this thesis project is named TRANSIT and is presenting how a collapsible desktop keyboard which is offering a NFC connection could look like and work to offer to people in public places such as libraries or universities and be as well be suitable for people to use at home. The TRANSIT keyboard is a simple and robust concept of a full-sized tactile keyboard which is offering a NFC connection as well as a Bluetooth connection for devices which do not support NFC yet. The design is aimed for smartphones and tablets and is offering a support which consists of an automated stand and a back plate which angle is adjustable step-less. The design allows to collapse stand, keyboard and back plate into a compact package which makes it easy to store and transport. Furthermore the design is providing a charging option for the smart device via energy harvesting or cable and has therefore internal batteries. The project is ending with the final presentation of the physical model in scale 1:1.
Detta examensarbete genomfördes i samarbete med design och ingenjörsföretaget Eker design från Fredriksstad i Norge, som designar och utvecklar flipcover NFC tangentbord till smartphones. Den nya produktidén är ett fullstort stationärt NFC tangentbord för offentliga institutioner, tänkt att användas av till exempel elever, studenter eller affärsmänniskor. Detta examensarbete undersöker hur ovan nämnda produkt kan och bör designas för att passa dess målmarknad och möta målgruppens intresse för att bli framgångsrik. Med en Human-centered design approach, började projektet med att utgå från användaren och marknaden. Arbetet bestod i att analysera och empatisera med marknaden som huvudsakligen bestod av användare och konkurrenterna, samt att undersöka trender genom en marknadsundersökning. Med utgångspunkt från de insikter som uppkom genom projektets utforskningsfas, skapades en design strategi och en affärsmodell för det nya tangentbordet i form av en design brief. Olika idéer och koncept skapades, testades och presenterades via koncept skisser och mock-ups. Det slutgiltiga konceptet utvecklades och designades med hjälp av CAD programvaran SolidWorks och renderingsprogrammet Keyshot. Design och utvecklingsfasen fokuserade på funktionalitet, användbarhet, material, ytor, texturer och mekaniska och tekniska lösningar för designen. Den slutgiltiga produkten heter TRANSIT och visar på hur ett hopfällbart stationärt tangentbord som erbjuder en NFC-anslutning skulle kunna se ut och fungera för människor som arbetar på olika platser i det publika rummet, som på bibliotek eller universitet. Men även för privat användning i hem. TRANSIT tangentbordet är ett enkelt och robust koncept av ett fullstort taktilt tangentbord som erbjuder en NFC-koppling såväl som Bluetooth for enheter som ännu inte stöder NFC. Designen, som är riktad mot smartphones och tablets, har ett ställ som består av ett automatiskt stöd och en bakplatta med steglös justering. Designen gör att tangentbordet, stödet och bakplattan går att fälla ihop till ett kompakt paket som är enkelt att transportera och förvara. Dessutom erbjuds möjligheter att ladda smart-enheter via energi-skördning eller kabel då enheten har inbyggda batterier. Projektet avslutades med en slutpresentation av en fysisk modell i skala 1:1.

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Elhajji, Majdi. "Co-Design de l’application H264 et implantation sur un NoC-GALS". Thesis, Lille 1, 2012. http://www.theses.fr/2012LIL10009/document.

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L'étude des réseaux sur puces (NoC) est un domaine de recherche qui traite principalement la communication globale dans les systèmes sur puce (SoC). La topologie choisie et l'algorithme de routage jouent un rôle essentiel durant la phase de conception des architectures NoC. La modélisation des structures répétitives telles que les topologies des réseaux sur puce sous des formes graphiques pose un défi particulier. Cet aspect peut être rencontré dans les applications orienté contrôle/données intensif tel que le codeur vidéo H.264. Model Driven Engineering est une méthodologie de développement logiciel où le système complet est modélisé à un niveau d'abstraction élevé en utilisant un langage de modélisation unifié comme l’UML/MARTE. Le profil UML pour la modélisation et l'analyse des systèmes embarqués en temps réel (MARTE) est la norme actuelle pour la modélisation des SoCs.Cette thèse décrit une méthodologie adéquate pour la modélisation des NoCs en utilisant le profil MARTE. L'étude proposée a montré que le paquetage RSM (Repetitive Structure Modeling) du profil MARTE est assez puissant pour modéliser différent types de topologies. En utilisant cette méthodologie, plusieurs aspects tels que l’algorithme de routage sont modélisés en se basant sur les machines d'état. Ceci permet au profil MARTE à être assez complet pour la modélisation d'un grand nombre d’architectures de NoCs. Certains travaux sont en cours pour synthétiser ces réseaux, en VHDL à partir de ces modèles. Pour la validation de la méthodologie proposée, une approche de co-design a été étudiée par l’implémentation d'un système de codage vidéo H.264 sur un NoC de type Diagonal Mesh en utilisant model en « Y » de l’outil Gaspard2. Avant de passer à l'association de l'application/architecture, une optimisation architecturale ciblant la réduction de la puissance consommée du module le plus critique (Estimateur de Mouvement) de l'application a été effectué. Ainsi, une architecture VLSI flexible d’un estimateur de mouvement à blocks variables (FSVBSME) a été proposée
The study of Networks on Chips (NoCs) is a research field that primarily addresses the global communication in Systems-on-Chip (SoCs). The selected topology and the routing algorithm play a prime role during the design of NoC architectures.The modeling of repetitive structures such as network on chip topologies in graphics forms poses a particular challenge. This aspect may be encountered in intensive data/control oriented applications such as H.264 video coder. Model driven engineering is a software development methodology where the complete system is modeled at a high abstraction level using a modeling language as UML/MARTE. The UML profile for Modeling and Analysis of Real-Time Embedded systems (MARTE) is the current standard for the SoCs modeling. This thesis describes an adequate methodology for modeling NoCs by using the MARTE standard profile. The proposed study has shown that the Repetitive Structure Modeling (RSM) package of MARTE profile is powerful enough for modeling different topologies. By using this methodology, several aspects such as routing algorithm are modeled based finite state machines. This allows to the MARTE profile to be complete enough for modeling a large number of NoCs architectures. Some work is on-going to synthesize such networks in VHDL from such models. While validating the proposed methodology, a co-design approach has been studied by mapping a H264 video coding system onto a Diagonal Mesh NoC by using the Y Chart of Gaspard2 tool. Before allowing the association of the application/architecture, an architectural optimization targeting power minimization of the most critical module of the application has been performed. So, a flexible VLSI architecture for full-search VBSME (FSVBSME) has been proposed

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Reehal, Gursharan Kaur. "Designing Low Power and High Performance Network-on-Chip Communication Architectures for Nanometer SoCs". The Ohio State University, 2012. http://rave.ohiolink.edu/etdc/view?acc_num=osu1340022240.

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Mothander, Ellinor. "Konsten att skapa tillsammans : En undersökning om gemensamt bildskapande för elever med NPF-diagnos". Thesis, Konstfack, Institutionen för Bildpedagogik (BI), 2019. http://urn.kb.se/resolve?urn=urn:nbn:se:konstfack:diva-6984.

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Hur kan vi främja interaktion, lustfyllt skapande, lek och kreativitet genom gemensamt bildskapande? Vilka metoder kan gynna personer som upplever det sociala samspelet som svårt? I min undersökning tittar jag på hur en grupp elever med NPF-diagnos kan utvecklas genom att arbeta tillsammans med bildskapande. Jag menar att någonting positivt händer i det kollektiva. Plötsligt ”äger” ingen verket och det lustfulla skapandet kan beredas plats. Ögon möts, fnitter uppstår och många vågar experimentera med teknik och material på ett annorlunda sätt. Det är något med interaktionen och kreativiteten som får sig en skjuts på vägen. Under våren 2019 håller jag i fyra stycken workshops på skolan där jag arbetar som bildlärare. Eleverna får själva välja att delta vid dessa tillfällen i gemensamt bildskapande. Metoder som har visat sig fruktbara är vikten av att aktivera kroppen, flera sinnen och att våga utmana undervisningsnormen för hur arbete i grupp ofta ser ut.Genom att laborera med den talade kommunikationen ges nya möjligheter för den sociala interaktionen. På Konstfacks vårutställning återskapades en variant av en utav workshoparna. Besökarna får ta del av ett interaktivt verk, där de erbjuds vara med och skapa ett collage på väggen som får växa fram under utställningens gång.

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Robino, Francesco. "A model-based design approach for heterogeneous NoC-based MPSoCs on FPGA". Licentiate thesis, KTH, Elektroniksystem, 2014. http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-145521.

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Network-on-chip (NoC) based multi-processor systems-on-chip (MPSoCs) are promising candidates for future multi-processor embedded platforms, which are expected to be composed of hundreds of heterogeneous processing elements (PEs) to potentially provide high performances. However, together with the performances, the systems complexity will increase, and new high level design techniques will be needed to efficiently model, simulate, debug and synthesize them. System-level design (SLD) is considered to be the next frontier in electronic design automation (EDA). It enables the description of embedded systems in terms of abstract functions and interconnected blocks. A promising complementary approach to SLD is the use of models of computation (MoCs) to formally describe the execution semantics of functions and blocks through a set of rules. However, also when this formalization is used, there is no clear way to synthesize system-level models into software (SW) and hardware (HW) towards a NoC-based MPSoC implementation, i.e., there is a lack of system design automation (SDA) techniques to rapidly synthesize and prototype system-level models onto heterogeneous NoC-based MPSoCs. In addition, many of the proposed solutions require large overhead in terms of SW components and memory requirements, resulting in complex and customized multi-processor platforms. In order to tackle the problem, a novel model-based SDA flow has been developed as part of the thesis. It starts from a system-level specification, where functions execute according to the synchronous MoC, and then it can rapidly prototype the system onto an FPGA configured as an heterogeneous NoC-based MPSoC. In the first part of the thesis the HeartBeat model is proposed as a model-based technique which fills the abstraction gap between the abstract system-level representation and its implementation on the multiprocessor prototype. Then details are provided to describe how this technique is automated to rapidly prototype the modeled system on a flexible platform, permitting to adjust the system specification until the designer is satisfied with the results. Finally, the proposed SDA technique is improved defining a methodology to automatically explore possible design alternatives for the modeled system to be implemented on a heterogeneous NoC-based MPSoC. The goal of the exploration is to find an implementation satisfying the designer's requirements, which can be integrated in the proposed SDA flow. Through the proposed SDA flow, the designer is relieved from implementation details and the design time of systems targeting heterogeneous NoC-based MPSoCs on FPGA is significantly reduced. In addition, it reduces possible design errors proposing a completely automated technique for fast prototyping. Compared to other SDA flows, the proposed technique targets a bare-metal solution, avoiding the use of an operating system (OS). This reduces the memory requirements on the FPGA platform comparing to related work targeting MPSoC on FPGA. At the same time, the performance (throughput) of the modeled applications can be increased when the number of processors of the target platform is increased. This is shown through a wide set of case studies implemented on FPGA.

QC 20140609

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Chou, Yajie. "Complexes de palladium-NHC atropisomériques : design, synthèse et applications en catalyse asymétriques". Electronic Thesis or Diss., Ecole centrale de Marseille, 2022. http://www.theses.fr/2022ECDM0012.

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Les performances des catalyseurs à base de palladium dans diverses réactions de couplage croisé ont suscité un intérêt croissant depuis les années soixante-dix et le développement de versions énantiosélectives a fait l’objet de recherches intensives. Dans ce domaine, les ligands auxiliaires N-hétérocycliques carbènes (NHCs) monodentates possédant de bonnes propriétés σ donneur et π-accepteur confèrent au métal d’excellentes réactivités. Les ligands NHCs sont appelés ligands intelligents, car leurs propriétés électroniques et stériques peuvent être finement ajustées à des transformations catalytiques spécifiques. Par conséquent, les complexes chiraux NHC-Pd sont une classe de catalyseurs chiraux qui se sont développés rapidement au cours des dernières décennies. Néanmoins, de nouveaux catalyseurs avec une réactivité et une énantiosélectivité améliorées sont nécessaires car seules quelques applications sont réellement développées dans l’industrie. L’objectif de mon doctorat était d’étudier un nouveau concept de complexes chiraux NHC-Pd et leurs applications pour explorer de nouvelles transformations catalytiques. Le premier chapitre expose la chimie du carbène en tant que ligands des métaux de transition avec les principales réalisations décrites dans la littérature. Les propriétés chimiques des NHCs sont également brièvement présentées. Dans ce chapitre, les différents designs de ligands chiraux NHC pour la catalyse à base de palladium sont résumés ainsi que les applications dans la catalyse énantiosélective. Enfin, des études antérieures sur les complexes chiraux NHC-palladium réalisées dans notre laboratoire sont présentées afin de définir les objectifs et les enjeux de mon travail de doctorat. Dans le deuxième chapitre de ce manuscrit, nous analysons les avantages et les inconvénients des catalyseurs développés dans notre groupe, afin de simplifier les étapes de synthèse et d’améliorer l’activité catalytique. En conséquence, certains nouveaux complexes NHC-avec chiralité axiale ont été conçus et synthétisés par des méthodologies de synthèse décrites dans la littérature. Les complexes chiraux de palladium possédants un NHC de symétrie C2 ont été d’abord préparés puis les diastéréoisomères ont été purifiés par chromatographie sur colonne de gel de silice pour éliminer les composés méso. Par la suite, les complexes hétérochiraux ont été résolus par HPLC chirale à l’échelle préparative pour les obtenir sous forme énantiomériquement pure. Enfin, la réactivité catalytique et l’induction énantiomérique que permet d’atteindre ces catalyseurs Pd-NHC-chiraux ont été évaluées dans une réaction modèle : l’α-amide arylation d’amides. De très bonnes inductions chirales ont été atteintes.Dans le troisième chapitre, de nouvelles transformations catalysées par le palladium ont été conçues et étudiées avec les nouveaux complexes chiraux-NHC précédemment établis en laboratoire. Après une étape d’optimisation des conditions de réaction et le criblage de plusieurs catalyseurs, nous avons constaté que ces nouveaux catalyseurs permettent d’obtenir une bonne induction chirale dans l’α-arylation de cétones. Nous avons également essayé l’hydrogénation catalysée par des complexes Pd-NHC cependant cette réaction n’a pas conduit à des résultats notables. Les réactions de couplage de Kumada ont également été étudiées pour synthétiser des métacyclophanes possédant une chiralité planaire. Divers métacyclophanes chiraux ont été préparés et leurs stabilités de configuration ont été étudiées. Des conditions de réaction optimales ont été identifiées afin de réaliser cette réaction asymétrique avec de bons résultats en termes de réactivité et d’énantiosélectivité
The performances of palladium-based catalysts in various cross-coupling reactions have attracted an ever-growing attention since the seventies and the development of enantioselective versions was the subject of intensive research. In this field, monodentate auxiliary N-heterocyclic carbene (NHCs) ligands possessing robust σ-donating and adaptable π-accepting properties confer to the metal excellent reactivities. NHCs ligands are referred as smart ligands, because their electronic and steric properties can be finely tuned to specific catalytic transformations. Therefore, chiral NHC-Pd complexes are a class of chiral catalysts that have developed rapidly in the recent decades. Nevertheless, new catalysts with enhanced reactivity and enantioselectivities are required as only few applications are actually developed in the industry. The goal of my Ph.D. was the investigated of a new design of chiral NHC-Pd complexes and their application to explore new catalytic transformations. The first chapter is focused on carbene chemistry as ligands of transition metals with main achievements reported in the literature. Chemical properties of NHCs have been also reviewed. In this chapter, the different designs of chiral NHC ligands for palladium-based catalysis reported in the literature as well as their applications in enantioselective catalysis have been also surveyed. Finally, previous studies on chiral NHC-palladium complexes in our laboratory are presented in order to define the objectives and issues of my Ph.D. work. In the second chapter of this manuscript, we analyze the advantages and disadvantages of the catalysts developed in our group, with the goal of simplifying the synthesis steps and improving the catalytic activity. As a result, some novel NHC-Pd complexes with axial chirality were designed and synthesized by known synthetic methods. The synthesized C2-symmetric NHC-Pd complexes were first attempted to separate diastereomers by silica gel column chromatography to remove meso compounds. Subsequently, heterochiral complexes were resolved in enantiomerically pure form by preparative-scale chiral HPLC. Finally, the catalytic reactivity and enantiomeric inductions of these highly enantiomerically pure chiral NHC-Pd catalysts were evaluated in the benchmark reaction: α-amide arylation of amides. Up to good chiral inductions were reached.In the third chapter, novel palladium-catalyzed transformations were investigated and developed with the new chiral Pd-NHC complexes previously established in the laboratory. After the optimization of reaction conditions and the screening of several catalysts, we found that these new catalysts can achieve good chiral induction in the α-arylation of ketones. We also tried NHC-Pd catalyzed hydrogenation, although the reaction did not lead to noticeable results. Kumada coupling reactions were also studied to synthesize planar-chiral metacyclophanes. Various chiral metacyclophanes have been prepared and their configurational stabilities have been investigated. Finally, optimal reaction conditions have been identified allowing to carry this asymmetric reaction with good results in terms of both reactivity and enantioselectivity

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Hueber, Damien. "Design, synthèse et application de nouveaux catalyseurs d'or (I) et d'or (III)". Thesis, Strasbourg, 2015. http://www.theses.fr/2015STRAF015/document.

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En synthèse organique, la recherche de nouveaux catalyseurs est un point crucial pour améliorer les conditions réactionnelles et découvrir de nouvelles réactions, particulièrement en chimie de l’or. Pour contribuer à ce développement, nous nous sommes intéressés à la nature du contre-ion, dont dépend la réactivité du catalyseur d’or, avec les polyoxométallates. Ces polyanions, de par leur nature intrinsèque, ont permis d’obtenir de nouveaux catalyseurs efficaces, polyvalents, multi-fonctionnels et hétérogènes, et applicables à un grand nombre de réactions catalysées à l’or.Nous avons aussi étudié un autre paramètre essentiel de la composition d’un catalyseur d’or : le ligand. Notre intérêt s’est porté sur les ligands carbènes N-hétérocycliques (NHC), dont la modularité de leurs propriétés électronique et stérique confère à l’or d’importantes activités. Nous avons ainsi développé différents types de NHC, en les fonctionnalisant pour les rendre acteurs de la réactivité, ou encore en leur attribuant de nouveaux groupements très encombrant pour influencer la réactivité et la sélectivité
In organic synthesis, the research of new catalysts is an essential issue to improve reactional conditions and to discover new reactions, especially in gold chemistry. To contribute to this development, we were interested in the nature of the counter-ion, which impact the reactivity of the gold catalyst, with the polyoxometalates. These polyanions, thanks to their nature, allowed to obtain new efficient, polyvalent, multi-functional and heterogeneous catalysts, which could be applied to a wide scope of gold catalyzed reactions.We also studied another essential parameter of the composition of gold catalysts: the ligand. We focused our attention on the N-heterocyclic carbenes (NHC), whose modularity of their electronic and steric properties confer important activities to gold catalysts. Thus we developed different kind of NHC, by functionalizing them so they can be involved in the reactivity, or by attributing them very bulky groups to influence the reactivity and selectivity

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Wu, Ruizhe. "Performance-Driven Communication Architecture Design in Irregular, Overlaid and Hybrid Mesh Wireless NoC". Thesis, University of Louisiana at Lafayette, 2014. http://pqdtopen.proquest.com/#viewpdf?dispub=3622964.

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With the scaling of silicon technology, multi-processor Systems-on-Chip (MPSoC) are moving towards many-core structures with distributed architecture where a number of processing cores with memory are interconnected by a high-speed on chip communication network to support advanced computing trends such as tera scale computing. Due to the stringent performance and power limitation, the state-of-the-art shared bus and point-to-point connections have been shown unable to supply nano scale MPSoCs (where hundreds or even thousands of cores are embedded) with both sufficient bandwidth and low latency. Network-on-Chips (NoCs) are emerging as an alternative communication platform for complex MPSoCs. In this work, we presents three novel WiNoC architectures based on UWB technology. We provide comprehensive designs, which includes Medium Access Control layer, Network layer, and modeling scheme. The implementation includes the lossless MAC, deadlock free routing algorithm, and unique simulator. Our work does not just include the pure WiNoC but also hybrid architecture. The results provides new architecture directions for wireless network on chip.

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Giroudot, Frédéric. "NoC-based Architectures for Real-Time Applications : Performance Analysis and Design Space Exploration". Thesis, Toulouse, INPT, 2019. https://oatao.univ-toulouse.fr/25921/1/Giroudot_Frederic.pdf.

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Les architectures mono-processeur montrent leurs limites en termes de puissance de calcul face aux besoins des systèmes actuels. Bien que les architectures multi-cœurs résolvent partiellement ce problème, elles utilisent en général des bus pour interconnecter les cœurs, et cette solution ne passe pas à l'échelle. Les architectures dites pluri-cœurs ont été proposées pour palier les limitations des processeurs multi-cœurs. Elles peuvent réunir jusqu'à des centaines de cœurs sur une seule puce, organisés en dalles contenant une ou plusieurs entités de calcul. La communication entre les cœurs se fait généralement au moyen d'un réseau sur puce constitué de routeurs reliés les uns aux autres et permettant les échanges de données entre dalles. Cependant, ces architectures posent de nombreux défis, en particulier pour les applications temps-réel. D'une part, la communication via un réseau sur puce provoque des scénarios de blocage entre flux, ce qui complique l'analyse puisqu'il devient difficile de déterminer le pire cas. D'autre part, exécuter de nombreuses applications sur des systèmes sur puce de grande taille comme des architectures pluri-cœurs rend la conception de tels systèmes particulièrement complexe. Premièrement, cela multiplie les possibilités d'implémentation qui respectent les contraintes fonctionnelles, et l'exploration d'architecture résultante est plus longue. Deuxièmement, une fois une architecture matérielle choisie, décider de l'attribution de chaque tâche des applications à exécuter aux différents cœurs est un problème difficile, à tel point que trouver une une solution optimale en un temps raisonnable n'est pas toujours possible. Ainsi, nos premières contributions s'intéressent à cette nécessité de pouvoir calculer des bornes fiables sur le pire cas des latences de transmission des flux de données empruntant des réseaux sur puce dits "wormhole". Nous proposons un modèle analytique, BATA, prenant en compte la taille des mémoires tampon des routeurs et applicable à une configuration de flux de données périodiques générant un paquet à la fois. Nous étendons ensuite le domaine d'applicabilité de BATA pour couvrir un modèle de traffic plus général ainsi que des architectures hétérogènes. Cette nouvelle méthode, appelée G-BATA, est basée sur une structure de graphe pour capturer les interférences possibles entre flux de données. Elle permet également de diminuer le temps de calcul de l'analyse, améliorant la capacité de l'approche à passer à l'échelle. Dans une seconde partie, nous proposons une méthode pour la conception d'applications temps-réel s'exécutant sur des plateformes pluri-cœurs. Cette méthode intègre notre modèle d'analyse G-BATA dans un processus de conception systématique, faisant en outre intervenir un outil de modélisation et de simulation de systèmes reposant sur des concepts d'ingénierie dirigée par les modèles, TTool, et un logiciel pour l'analyse de performance pire-cas des réseaux, WoPANets. Enfin, nous proposons une validation de nos contributions grâce à (a) une série d'expériences sur une plateforme physique et (b) deux études de cas d'applications réelle; le système de contrôle d'un véhicule autonome et une application de décodeur 5G
Monoprocessor architectures have reached their limits in regard to the computing power they offer vs the needs of modern systems. Although multicore architectures partially mitigate this limitation and are commonly used nowadays, they usually rely on intrinsically non-scalable buses to interconnect the cores. The manycore paradigm was proposed to tackle the scalability issue of bus-based multicore processors. It can scale up to hundreds of processing elements (PEs) on a single chip, by organizing them into computing tiles (holding one or several PEs). Intercore communication is usually done using a Network-on-Chip (NoC) that consists of interconnected onchip routers allowing communication between tiles. However, manycore architectures raise numerous challenges, particularly for real-time applications. First, NoC-based communication tends to generate complex blocking patterns when congestion occurs, which complicates the analysis, since computing accurate worst-case delays becomes difficult. Second, running many applications on large Systems-on-Chip such as manycore architectures makes system design particularly crucial and complex. On one hand, it complicates Design Space Exploration, as it multiplies the implementation alternatives that will guarantee the desired functionalities. On the other hand, once a hardware architecture is chosen, mapping the tasks of all applications on the platform is a hard problem, and finding an optimal solution in a reasonable amount of time is not always possible. Therefore, our first contributions address the need for computing tight worst-case delay bounds in wormhole NoCs. We first propose a buffer-aware worst-case timing analysis (BATA) to derive upper bounds on the worst-case end-to-end delays of constant-bit rate data flows transmitted over a NoC on a manycore architecture. We then extend BATA to cover a wider range of traffic types, including bursty traffic flows, and heterogeneous architectures. The introduced method is called G-BATA for Graph-based BATA. In addition to covering a wider range of assumptions, G-BATA improves the computation time; thus increases the scalability of the method. In a second part, we develop a method addressing design and mapping for applications with real-time constraints on manycore platforms. It combines model-based engineering tools (TTool) and simulation with our analytical verification technique (G-BATA) and tools (WoPANets) to provide an efficient design space exploration framework. Finally, we validate our contributions on (a) a serie of experiments on a physical platform and (b) two case studies taken from the real world: an autonomous vehicle control application, and a 5G signal decoder application

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Meijer, Felix. "Shopal : Utforskning av applikationer för det digitala jaget på den fysiska världen". Thesis, Umeå universitet, Designhögskolan vid Umeå universitet, 2017. http://urn.kb.se/resolve?urn=urn:nbn:se:umu:diva-135773.

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This project aimed to explore how payments and identification might be moved from traditional wallets and implemented into a smart wearable.The thesis was that this would be doable through the use of NFC (Near Field Communication), IoT (Internet of Things) and Cloud-based services.Research was made by collecting data through questionnaires, local workshops, bodystorming and looking into online literature and articles on the subject of future consumer trends, wearable technology and biometric systems, security concerning wireless payments and identification as well as trend analysis articles concerning the Digital Self - also known as the Exoself - which came to have a major impact on the direction the project took. Through ideation five concepts concerning services and products using a person’s Digital Self were formed and evaluated with workshops. This eventually led to a concept called Shopal being decided as the endgame of the project. Shopal was a service which filtered the user’s information within the Digital Self to make shopping decisions easier, by learning what the user wants to know about certain types of products, then aiming to deliver said information. This service was called AIA (Artificial Intelligence Assistant). The second outcome of the Shopal concept was the AHW (At-Hand-Wearable) collection named SIGIL, which works as a means to extend AIA:s perception to what the user touches and interacts with, allowing it to gather information about the product, then delivering it through the physical AHW to the user.

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KJELLSTRÖM, FRANCISKA. "Design Assurance Important: aspects for implementation". Thesis, KTH, Industriell produktion, 2017. http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-214442.

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A rapidly changing environment for industrial technology companies operating on a global market has increased the competitiveness and accelerated the rate of new technologies. The demands on companies to be more efficient and innovative without compromising quality are thereby enlarged. To maintain competitiveness and meet customer expectation a well-functioning product development is essential. Correcting product quality issues on newly developed products becomes increasingly more expensive the later it takes place in the development process and problems that arise can often be linked to the product design. In order to secure that new product development projects efficiently can deliver high quality products without compromising cost targets and time-to-market Design Assurance can be applied during the product development. The intention is to uncover and detect problems in the design and prevent errors to occur in the engineering process, by executing controls to assure design has been completed according to standards and policies. This project aims to investigate Design Assurance to further establish the concept at Alfa Laval BU HSS and describe how product quality is assured in product development. Analysis of literature studies, interviews at Alfa Laval BU HSS as well as benchmarking at three companies; Atlas Copco Industrial Technique, Getinge (Maquet Critical Care division) and Tetra Pak, provide the basis of the results in this study. The results show there are a number of factors greatly influencing an organization’s ability to ensure product quality in product development. Key factors identified in this study are cross functional team work, the internal culture in the organization, firmly established product strategies, product development processes and requirement management and validation capability. These factors can be seen as essential conditions for ensuring product quality during development and prerequisites for establishing Design Assurance at Alfa Laval BU HSS. Key building blocks in the Design Assurance capability are identified and described, which include reviews of actions and project documentation that safeguards continuous improvements and prevent future deficiencies. The Design Assurance activities are identified as documentation management, change management, risk assessments, nonconformance management, product quality follow up and lessons learned.
Dagens industritekniska företag verkar i en global miljö med snabba förändringar, vilket har bidragit till ökad konkurrens och accelererat hastigheten för ny teknik. Därmed har även kraven på företagen att bli mer effevtiva och innovativa, utan att kompromissa med produktens kvalitet, ökat. En väl-fungerande produktutveckling är nödvändig för att bibehålla konkurrenskraft och möta kundernas förväntningar. Ju senare produkters kvalitetsproblem upptäcks och rättas till under utvecklings-processen desto dyrare är det och problemen härstammar ofta från produktens konstruktion. För att säkerställa att nyutvecklingsprojekt effektivt kan leverera högkvalitativa produkter utan att påverka kostnadsmål eller time-to-market, kan Design Assurance tillämpas under produktutvecklingen. Avsikten är att upptäcka, identifiera och förebygga brister i konstruktionen som kan orsaka problem senare under utvecklingen, genom att utföra kontroller för att säkerställa att konstruktionen uppfyller standarder, anvisningar och andra krav. Denna uppsats syftar till att undersöka Design Assurance för att ytterligare etablera konceptet på Alfa Laval BU HSS och beskriva hur produktkvaliteten säkras under produktutvecklingen. Analys av litteraturstudier, intervjuer på Alfa Laval BU HSS samt benchmarking vid tre företag; Atlas Copco Industriteknik, Getinge Maquet Critical Care divisionen och Tetra Pak, utgör grunden för resultatet i denna studie. Resultatet visar att det finns ett antal faktorer som i hög grad påverkar en organisations förmåga att säkerställa produkternas kvalitet i produktutvecklingen. Nyckelfaktorer har i denna studie identifierats som tvärfunktionellt arbete, den interna kulturen på företaget, väl förankrade produkt-strategier, processer inom produktutveckling samt kravhantering och valideringsförmågan under utvecklingen. Dessa faktorer kan ses som nödvändiga förutsättningar för att säkerställa produktkvalitet under produktutveckling och därmed förutsättningar för att framgångsrikt etablera Design Assurance på Alfa Laval BU HSS. Slutligen är de centrala delarna för att genomföra och applicera Design Assurance identifierade och beskrivna, vilka innefattar granskning av handlingar och projektdokument som säkerställer ständiga förbättringar och förebygger framtida brister. Design Assurance-aktiviteter är identifierade som kontroll av korrekt dokumentering, hantering av ändringar, avvikelsehantering, riskbedömningar, uppföljning av produktkvalitet och lärdomar under produktutvecklingsprojektet.

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Han, Koogin. "Design leadership and communication : characteristics and abilities of design leaders communicating design to non-designers during the fuzzy front end of new product development". Thesis, Brunel University, 2014. http://bura.brunel.ac.uk/handle/2438/9759.

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This research investigates the key characteristics of design leaders in the context of New Product Development (NPD) at the Fuzzy Front End (FFE) or early stage of this process. It particularly focuses on how design leaders communicate design to non-designers. It is often observed that designers struggle to communicate design to non-designers. Previous research has identified design leaders as competent design communicators. However, the definition and key characteristics of design leaders remain unclear. By reviewing the literature on leadership studies, design leadership and project leadership, it is evident that no single universal definition of leadership exists. The most common definition is that leaders apply their knowledge and skills to conduct activities and use their traits to influence other people’s actions. Leadership requires different characteristics for different tasks. To understand the characteristics of design leaders, triangulated research was employed at a real-life NPD project involving young designers and non-designers at early stages of NPD as part of the first study. All participants (N=32) were directly observed, interviewed in semi-structured interviews and administered with assistive questionnaires to compare design and non-design participants’ leadership and communication styles. The second study was in-depth, focusing on UK design leaders (N=11) through semi-structured interviews and based on deficiencies in leadership and communicating design, identified from the first study and the literature review. Comparative studies indicate that designers and design leaders vary their attitudes towards non-designers, motivation and communication style. This study highlights the key characteristics of design leaders: an epiphany by experiencing the entire NPD process, interest in the benefits of NPD stakeholders, a good understanding of design competency, reflectively flexible working attitude and strong, active listening. Thus, a conceptual model was formulated and evaluated, able to guide designers who wish to become design leaders and help to enhance design communication and relationships with non-designers.

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Sandborgh, Line. "Hur kan produktdesign förbättra kommunikationen mellan grundskolelärare och elever med NPF diagnoser?" Thesis, Malmö universitet, Fakulteten för kultur och samhälle (KS), 2019. http://urn.kb.se/resolve?urn=urn:nbn:se:mau:diva-23801.

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Elever med neuropsykiatriska funktionsvariationer (NPF) upplever en försämrad skolgång på grund av att den är dåligt anpassad efter deras behov. Grundskolelärare har ett ansvar att anpassa sin undervisning så den passar alla, men deras ökade belastning lämnar lite tid över till att kommunicera med sina elever på individnivå för att ta reda på deras behov. Den bristande kommunikationen mellan grundskolelärare och elever med NPF blir problematisk då parternas behov missförstås av varandra. Denna studie undersökte hur man genom produktdesign kan skapa en bättre kommunikation mellan elever med NPF och deras lärare. Studien genomfördes med teorier och metoder från forskningsfältet användarcentrerad design. Genom intervjuer, observationer, dokumentanalys, en ökad empatisk förståelse och marknadsundersökning skaffade studien en förståelse av användarnas behov och önskemål. En koncept- och produktutvecklingsfas möjliggjorde skapandet av ett slutgiltigt produktförslag. Studiens slutsats visar hur produktdesign i en användarcentrerad designprocess skapar en förståelse för en användargrupp och möjliggör ett produktförslag som tillfredsställer deras behov. Studien resulterade i ett produktförslag som kan förbättra kommunikationen mellan grundskoleelever med NPF och deras lärare. Produktförslaget kan förhoppningsvis leda till en bättre skolgång för elever med NPF om läraren gör anpassningar i sitt klassrum och/eller undervisning som tar hänsyn till elevens behov. Produktförslaget är endast ett förslag på hur en produktlösning kan se ut bland många andra möjliga lösningar. Studiens kunskapsbidrag bidrar med insikt i hur man genom produktdesign och en användarcentrerad designprocess kan utforska en användargrupp för att tillgodose deras behov.
Students with cognitive disabilities are unsatisfied with their lower school education because of poor adaption to their needs. Lower school teachers have a responsibility to adjust their way of teaching and classroom environment in order to fulfill everyone’s needs. But the abundant workload teachers experience leaves little time for individual communication with their students to find out their needs. This study examined how product design can create a better communication between lower school students with cognitive disabilities and their teachers. The study used theories and methods from the research field of user-centered design. The methods used were interviews, observations, analysis of documents, improvement of empathetic understanding and a market analysis. These enabled a better understanding of the users’ needs and desires. The study’s conclusion shows how product design in a user-centered design process can create a better understanding of a user group and a design-proposal that satisfies the users’ needs and desires. The study resulted in a design-proposal that can improve communication between lower school students and their teachers. The design proposal can potentially lead to an improved education for students with cognitive disabilities if the teacher adjusts their classroom environment and/or way of teaching with regards to their students’ needs. The design-proposal is merely a proposal among many other solutions of how a product solution could be made. The study contributes with research about how product design and a user-centered design process can examine a user group in order to satisfy their needs.

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Savchuk, Mariia. "Complexes atropisomériques d'or-NHC : design, synthèse et applications dans des réactions de cycloisomérisation asymétriques". Electronic Thesis or Diss., Aix-Marseille, 2022. http://www.theses.fr/2022AIXM0571.

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Le premier chapitre de ce manuscrit est consacré à l’étude des différents designs de NHCs chiraux décrits dans la littérature et leurs applications en tant que ligand dans les transformations énantiosélectives catalysées par l’or. Un nouveau concept de complexes atroipsomériques métal de transition-NHC a été conçu et développé dans notre groupe. Son application pour préparer des complexes de métaux de transition chiraux portant un ligand NHC de symétrie C1 contenant un NHC saturé a été étudiée au cours de mes travaux de doctorat et sera présentée dans le deuxième chapitre. Divers complexes chiraux ont été obtenus, séparés par HPLC chirale à l’échelle préparative et leurs stabilités configurationnelles ont été étudiées en profondeur. Le complexe contenant de l’or(I) a été testé pour la cycloisomérisation d’1,6-énynes, donnant une énantiosélectivité prometteuse (70% ee). Dans le troisième chapitre de ce manuscrit, le concept de complexes atroipsomériques métal de transition-NHC a été étendu à des ligands NHCs de symétrie C2 et appliqué des transformations asymétriques catalysées par de l’or(I). Les 1,6-énynes possédant un lien malonate de diisopropyle se sont avérés être d’excellents substrats pour des réactions de cycloisomérisation et les produits d’alcoxycyclisation qui en ont résultées ont été isolés avec d’excellentes énantiopuretés (7 exemples avec des rendements de 51 à 92% et des excès énantiomériques compris entre 56 et 99%). La cycloisomérisation lorsqu’elle est réalisée sans nucléophile externe a également conduit à d’excellents résultats (6 exemples avec des rendements allant de 72 à 99%, et des excès énantiomériques dans la gamme 86-93% ee)
The first chapter of this manuscript is dedicated to survey the design of chiral NHC and their applications as ligand in gold-catalyzed enantioselective transformations. This presentation clearly showed the importance of new ligand designs, because only poor enantioselectivities have been reached up to date. A new concept of atroipsomeric transition metal-NHC complexes has been devised and developed in our group. Its application to prepare chiral transition metal complexes bearing C1-symmetric NHC ligand containing a satured backbone was investigated during my Ph.D. work and will be presented in the second chapter. Various chiral complexes were obtained, separated by chiral HPLC at preparative scale and their configurational stabilities were investigated in depth. The gold (I) containing complex was tried in the 1,6-enyne cycloisomerization, giving a promissing enantioselectivity (70% ee). In the third chapter of this manuscript, the concept of atroipsomeric transition metal-NHC complexes was extended to C2-symmetric NHC ligands and applied to the asymmetric Au(I)-catalyzed transformations. Diisopropyl malonate-tethered 1,6-enynes were identified as excellent substrates for cycloisomerization reactions and resulting alkoxycyclization products were isolated with excellent enantiopurities (7 examples with 51-92% yield, 56-99% ee). The cyclization without external nucleophiles led also to excellent results a (6 examples with 72-99% yield, 86-93% ee)

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Fransson, Emelie. "Mängdavtagning från dynamisk BIM-modell, en fallstudie på NCC Montagebro". Thesis, KTH, Bro- och stålbyggnad, 2012. http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-99379.

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Byggbranschen har flertalet gånger blivit kritiserad för att inte uppnå samma utveckling och produktivitet som andra sektorer. Visionen om ett effektivt samhällsbyggande är ändå positiv och en av de stora nämnarna för framgång är BIM, Building Information Modeling. Arbetsmetoden, som handlar om att effektivt tillhandahålla information, tillämpas redan i relativt stor utsträckning på hussidan. Samtidigt ligger bro- och anläggningssidan i startgroparna för att följa efter husbyggnad i utvecklingen. NCC Montagebro är en prefabricerad betongbro som utvecklades på 80-talet och som återigen lyfts fram för utveckling. De tidigare standardmåtten har avskaffats för att i högre grad möta kundens önskemål om längd och bredd. Problemet med de fritt valbara måtten är att det inte finns något underlag att utgå ifrån vid prissättning i ett anbud. Syftet med detta arbete var därför att undersöka möjligheten med att upprätta en parameterstyrd BIM-modell att använda för mängdavtagning. Genom att belysa hinder och möjligheter var målet att resultatet skulle kunna användas för fortsatt utveckling av produkten. Studien utfördes med hjälp av intervjuer med verksamma personer i branschen och en praktisk fallstudie. Resultaten från dessa diskuterades utifrån de uppställda frågeställningarna och den tidigare redovisade litteraturstudien. En viktig aspekt som framkommit under studien är att möjligheten att effektivisera och standardisera prissättningen går hand i hand med graden av standardisering för brokonceptet som helhet. För att kunna göra en generell och anpassningsbar modell måste det utredas vilka mått och parametrar som ska vara standard och vilka som kan justeras fritt för varje nytt projekt. Detta och alla övriga erfarenhetsdokument borde samlas i en egen tekniska plattform för NCC Montagebron. Studiens slutsats är att det går att effektivisera prissättningen av NCC Montagebro med hjälp av BIM men det är inte ett tillräckligt argument för att skapa en BIM-modell. Förslagsvis bör modellen uppdateras med mer information så att den kan utnyttjas i fler delprocessen för annars går en stor del av syftet med BIM förlorat.
The Construction Industry has been criticized several times for their slow development and for not being as productive as other industries. In orderto achieve an efficient Architecture, Engineering & Construction (AEC) Industry, Building Information Modeling, BIM, is one of the most debatedtopics in the field. The work process, which is about to efficiently provide information about a project, is already applied in the building construction. On the other hand, bridge and civil construction are just about to start the implementation of BIM. NCC Montagebro is a prefabricated concrete bridge which was developed in the 1980s and is once again up-to-date for product development. Theprevious standard dimensions have been removed in order to meet the customers’ requirements for length and width. A problem that occurs when allowing the customers to choose the dimensions is that there is no corresponding documentation to base the pricing on. The aim of this work was to investigate the possibility of establishing a parametric BIM model to use for quantity take off. A goal was to facilitate the continuing improvement of the product by highlighting obstacles and opportunities. The study was carried out through interviews and a practical case study. The results of these were discussed from the stated research questions andthe previously reported literature review. An important aspect emerging from the study is that the ability to rationalize and standardize the pricing depends on the degree of standardizationof the whole bridge concept. To make a general and flexible model it is necessary to examine which dimensions and parameters that should be set to default and which can be freely adjusted for each new project. These decisions and all other documents of experience should be gathered in a special technical platform for the NCC Montagebro. The study concludes that it is possible to rationalize the pricing of NCC Montagebro by using BIM but the arguments may not be enough to design a BIM model. The model should be provided with additional information so that it can be used in several sub-processes because otherwise, a large part of the purpose of BIM is lost.

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Enblom, Pernilla. "ADHD-Design : En undersökning av bilder om, för och av ADHD". Thesis, Konstfack, Institutionen för Bildpedagogik (BI), 2012. http://urn.kb.se/resolve?urn=urn:nbn:se:konstfack:diva-3317.

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Undersökningen baseras på frågorna, ”Hur kan pedagogik avsedd för människor med diagnosen ADHD se ut idag?” och ”Hur kan en undervisningsmetod som är utvecklad genom ett designpedagogiskt perspektiv och avsedd för människor med diagnosen ADHD se ut?” Syftet är att ur ett designpedagogiskt perspektiv undersöka hur pedagogiska metoder för människor med ADHD diagnos ser ut samt att analysera dessa utifrån en diskursanalysinspirerad metod. Undersökningen använder begreppet ADHD- pedagogik som samlingsbenämning för pedagogik avsedd för människor med diagnosen ADHD. Jag har använt mig av en diskursinspirerad metod för att analysera olika former av pedagogiskt material avsedda för människor med diagnosen ADHD. Analysen resulterade i tre diskurser som jag kallar bilder om, för och av ADHD.Under arbetets gång har jag letat efter människor med diagnosen ADHD för att tillsammans utveckla pedagogiska metoder. Detta resulterade i en workshop i slutet av arbetet men namnet ”Gör ditt eget diagnos-smycke”, där personer med olika neuropsykiatriska funktionsnedsättningar deltog. Min gestaltning bestod av ”Diagnos-smycken” gjorda av deltagare på workshopen inklusive mig själv. De flesta smyckena har en medföljande text som förklarar/beskriver eller berättar något om smycket och/eller om den egna diagnosen/diagnoserna.

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Karapinar, Ercument. "Modification and verification of an antenna design for Petite Amateur Navy Satellite (PANSAT) using NEC". Thesis, Monterey, Calif. : Springfield, Va. : Naval Postgraduate School ; Available from National Technical Information Service, 1995. http://handle.dtic.mil/100.2/ADA302829.

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McIntyre, James. "Enhancing the SME NPD process through customer focused design activities: a New Zealand case study". Massey University, 2009. http://hdl.handle.net/10179/1073.

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Small to Medium Enterprises (SMEs) face enormous financial risk when embarking on a new product launch. SMEs are less likely to implement more formal risk minimization strategies for new product development (NPD) such as StageGate, often citing reasons of resource constraints or the more prevalent notion that “this stuff doesn’t apply to us”. Two key elements of any such risk minimization strategies are an early emphasis on benchmarking competitors and a thorough study of the attitudes and behaviours of potential customers. The SME’s investment of time and resource in early acquisition of this knowledge is a critical factor for success (Cooper 2001). Armed with this information, the SME is able to adopt a Customer Focused Design (CFD) strategy, whereby the product development effort is remains focused on the external customers wants and needs through all phases. SMEs that are able to satisfy these needs more effectively enjoy an obvious competitive advantage (Matzler and Hinterhuber 1998; Lüthje 2004). SMEs are often challenged by these tasks (Freel 2000; Larsen and Lewis 2007; Owens 2007). They may be overwhelmed by the prospect of expected costs, lack of expertise, and financial pressures to rush to market. Too often the more conventional path is chosen, whereby a solution is proposed, developed and tested in the market to “see if it sticks”. Such methodologies are less effective and subject the SME to increased financial risk. International studies of SMEs attitudes and behaviour towards NPD reveal common challenges of resource limitations, skills deficiencies and organizational issues (Xueli, Soutar et al. 2002; de Jong and Vermeulen 2006; Siu, Lin et al. 2006; Murphy and Ledwith 2007; Owens 2007). New Zealand firms are no exception, and are burdened with similar challenges as their international counterparts. This study aims to propose a simple framework for small firms who wish to acquire knowledge about their target markets and potential customers with limited time and resources. The framework enables SMEs to incorporate customer focused design principles into their product definition phase, and better orient themselves to the consumer marketplace. The study makes use of a New Zealand based case study to evaluate how the framework may be employed to identify quick and inexpensive efforts that can reproduce some elements of more sophisticated CFD and benchmarking methods. The obtained results are incorporated into a product design specification and embodied into a physical prototype to further illuminate the process. In addition to the primary area of study, prospects for new adjacent product lines and new potential markets for future development are also gained from the research.

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Yuan, Wen. "Hybrid Nanophotonic NOC Design for GPGPU". Thesis, 2012. http://hdl.handle.net/1969.1/ETD-TAMU-2012-05-10913.

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Due to the massive computational power, Graphics Processing Units (GPUs) have become a popular platform for executing general purpose parallel applications. The majority of on-chip communications in GPU architecture occur between memory controllers and compute cores, thus memory controllers become hot spots and bottle neck when conventional mesh interconnection networks are used. Leveraging this observation, we reduce the network latency and improve throughput by providing a nanophotonic ring network which connects all memory controllers. This new interconnection network employs a new routing algorithm that combines Dimension Ordered Routing (DOR) and nanophotonic ring algorithms. By exploring this new topology, we can achieve to reduce interconnection network latency by 17% on average (up to 32%) and improve IPC by 5% on average (up to 11.5%). We also analyze application characteristics of six CUDA benchmarks on the GPGPU-Sim simulator to obtain better perspective for designing high performance GPU interconnection network.

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41

Vikram, Kulkarni Nikhil. "STT-MRAM Based NoC Buffer Design". Thesis, 2012. http://hdl.handle.net/1969.1/ETD-TAMU-2012-08-11684.

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As Chip Multiprocessor (CMP) design moves toward many-core architectures, communication delay in Network-on-Chip (NoC) is a major bottleneck in CMP design. An emerging non-volatile memory - STT MRAM (Spin-Torque Transfer Magnetic RAM) which provides substantial power and area savings, near zero leakage power, and displays higher memory density compared to conventional SRAM. But STT-MRAM suffers from inherit drawbacks like multi cycle write latency and high write power consumption. So, these problem have to addressed in order to have an efficient design to incorporate STT-MRAM for NoC input buffer instead of traditional SRAM based input buffer design. Motivated by short intra-router latency, previously proposed write latency reduction technique is explored by sacrificing retention time and a hybrid design of input buffers using both SRAM and STT-MRAM to "hide" the long write latency efficiently is proposed. Considering that simple data migration in the hybrid buffer consumes more dynamic power compared to SRAM, a lazy migration scheme that reduces the dynamic power consumption of the hybrid buffer is also proposed.

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Chen, Yan-Zuo, e 陳彥佐. "Design of Combination Antennas for NFC Applications". Thesis, 2014. http://ndltd.ncl.edu.tw/handle/wp3hn3.

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碩士
國立高雄應用科技大學
光電與通訊工程研究所
102
In this thesis, a combination antenna for near-field communication is proposed and tested. Three chapters in this thesis show the design rules for wireless power charging coil, near-field communication coil, two integrated coils and the near-field reader coil. A transmitter sends a signal to a receiver. When the receiver obtains minimum driver inductance that can communicate with the transmitter. The near-field communication coil needs impedance matching with chip. Finally, a near-field reader embedded in the slot is proposed. This antenna can reduce the influence of metal effect by connecting the edges of slot. This reader antenna also uses the lump matching circuit to reach the designed resonant frequency.

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Luo, Si-Jheng, e 羅西政. "Near Field Communication (NFC) Array Antenna Design". Thesis, 2014. http://ndltd.ncl.edu.tw/handle/00853448158722432450.

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碩士
國立勤益科技大學
電子工程系
102
This paper proposed a development of near field communication system (Near Field Communication; NFC) array antenna design for extending the range of NFC signals receiving and transmitting. The first step is designing various single antennas at 13.56MHz for NFC signal receiving and transmitting, and then combining single antenna into array configurations. The array antenna impedance matching problems become very important issues to achieve radiation efficiency and need to use adequate inductors and capacitors circuit configurations and special selected values to resolve the problem. This research is conducted using electromagnetic simulation software IE3D for 13.56MHz single antenna design, and by using AUTOCAD for the circuit layout, and then applied the PCB engraving machine for the final physical antenna output. Combining each NFC single antenna and adding serial/parallel capacitor Cr to achieve the required return loss value. This work is done by measuring the characteristics |S 11 | of adjourned antenna, and adjusting the capacitor Cr to meet the return loss value at 13.56MHz. The final NFC antenna array design is completed by repeated adding all the single antennas on and adjusted the capacitors to satisfy required return loss.

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huang, ming-yu, e 黃明煜. "Design of NFC Tag Antenna for Mobile Phone". Thesis, 2015. http://ndltd.ncl.edu.tw/handle/657w5q.

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碩士
國立中央大學
通訊工程學系在職專班
103
This thesis designed NFC tag antennas embedded in the middle of mobile phone back cover and battery, and we used NFC tag to reach the maximum distance of electromagnetic induction. Based on antenna and electromagnetic theory, we used high frequency structure simulator (HFSS) software to do emulations. We chose flexible printed circuit board (FPCB) to make the NFC tag antenna and measured the bandwidth by using Agilent E5061A spectrum analyzer. At the same time, we had also recorded the influence of the shape of NFC tag antenna, match capacitance value, and absorbing material relationship on the distance of electromagnetic induction. Based on the research results, we can apply to the development and the reference of design of NFC wireless charging hardware in the future.

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Tseng, Chang-Chuan, e 曾丈權. "The NFC Design Study for Point of Service". Thesis, 2015. http://ndltd.ncl.edu.tw/handle/67282218671048158255.

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碩士
國立高雄第一科技大學
資訊管理研究所
103
For many people, the mobile has become a wallet with just as important items they carry with them. Consumer gradually began to use NFC card to pay, but in the use are still many restrictions. The paper APP combination of NFC paid, to significantly reduce the cost structure equipment and increase consumer use of electronic cash. Due to the expected 2016 will be listed NFC SIM card, so the telecommunications companies are also available standards. motivated by this, a company release point card machines which matches trends. Although Kaohsiung City Government once release, card of memory card, but the result bad. The study used O 2 O way design, it is online to line innovative ideas and the beginning. In the system, use clients more interaction, and meals for streamlining, manpower, it is important in the client waiting and customer feedback there was a marked feeling. Whether shops CRM system used to see the present point meal feeding the progress, and stores operating revenue APP or a customer use to interaction, is an innovative features, and this is to retain the APP customers use and store owners more targeted to the customers spread the message. The Institute research and development system that can apply to restaurant management, provide users with quick meals, rapid disbursement, for the industry provides a complete end the management system for managing franchise operators are to save manpower costs, and notify users advantages, is a point card machine system to provide a possible solutions. In future applications development can be electronic payment systems, and to integrate capital and high in the clouds stored-value, in a restaurant on businesses expand their applications such as: Special Offers feedback, different industry alliances for strengthening such as the breadth enterprises, and can match in the public transport applications, could also be used in personal use, such as contact information automatically log on, the company rush card NFC such as related applications.

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Tsai, Shin-Ni, e 蔡昕霓. "Evaluation of NoC Design for Heterogeneous Multicore Systems". Thesis, 2017. http://ndltd.ncl.edu.tw/handle/f2hhru.

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碩士
國立清華大學
資訊工程學系所
105
Heterogeneous multicore systems integrate different types of processors on the same chip in order to match the workloads with the most appropriate processors. Among the different types of processors, Graphic Processing Unit (GPU) is one of the most commonly used processors, not only because of their technology maturity but also because of their high computing-power ratio. To interconnect the multiple CPUs, GPUs, caches, and memory controllers on a chip, a network-on-chip (NoC) is often used, whose design is very critical to the performance of the whole system. As CPUs and GPUs often play different roles and execute different workloads, the traffic injected into the NoC from CPUs and GPUs may have very different characteristics. GPU cores tend to generate bursty high-volume traffic, which is throughputsensitive. Therefore, the placement of GPU cores in the NoC and the network resources allocated to the GPUs should be designed carefully in order not to hinder the performance of GPUs. In this thesis, we evaluate the performance of NoC under different processor placement and network resource allocation. We use gem5-gpu simulator to simulate applications running in a heterogeneous CPU-GPU multicore system and record the memory access trace. We then modify Garnet2.0 to take the trace as input and evaluate the performance of different system configurations. It is observed that GPUs are sensitive to the proximity to memory from the evaluations. Therefore it can be referred as a critical impacting factor in terms of heterogeneous NoC design.

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Basavaraj, T. "NoC Design & Optimization of Multicore Media Processors". Thesis, 2013. http://etd.iisc.ac.in/handle/2005/3296.

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Network on Chips[1][2][3][4] are critical elements of modern System on Chip(SoC) as well as Chip Multiprocessor(CMP)designs. Network on Chips (NoCs) help manage high complexity of designing large chips by decoupling computation from communication. SoCs and CMPs have a multiplicity of communicating entities like programmable processing elements, hardware acceleration engines, memory blocks as well as off-chip interfaces. With power having become a serious design constraint[5], there is a great need for designing NoC which meets the target communication requirements, while minimizing power using all the tricks available at the architecture, microarchitecture and circuit levels of the de-sign. This thesis presents a holistic, QoS based, power optimal design solution of a NoC inside a CMP taking into account link microarchitecture and processor tile configurations. Guaranteeing QoS by NoCs involves guaranteeing bandwidth and throughput for connections and deterministic latencies in communication paths. Label Switching based Network-on-Chip(LS-NoC) uses a centralized LS-NoC Management framework that engineers traffic into QoS guaranteed routes. LS-NoC uses label switching, enables band-width reservation, allows physical link sharing and leverages advantages of both packet and circuit switching techniques. A flow identification algorithm takes into account band-width available in individual links to establish QoS guaranteed routes. LS-NoC caters to the requirements of streaming applications where communication channels are fixed over the lifetime of the application. The proposed NoC framework inherently supports heterogeneous and ad-hoc SoC designs. A multicast, broadcast capable label switched router for the LS-NoC has been de-signed, verified, synthesized, placed and routed and timing analyzed. A 5 port, 256 bit data bus, 4 bit label router occupies 0.431 mm2 in 130nm and delivers peak band-width of80Gbits/s per link at312.5MHz. LS Router is estimated to consume 43.08 mW. Bandwidth and latency guarantees of LS-NoC have been demonstrated on streaming applications like Hiper LAN/2 and Object Recognition Processor, Constant Bit Rate traffic patterns and video decoder traﬃc representing Variable Bit Rate traffic. LS-NoC was found to have a competitive figure of merit with state-of-the-art NoCs providing QoS. We envision the use of LS-NoC in general purpose CMPs where applications demand deterministic latencies and hard bandwidth requirements. Design variables for interconnect exploration include wire width, wire spacing, repeater size and spacing, degree of pipelining, supply, threshold voltage, activity and coupling factors. An optimal link configuration in terms of number of pipeline stages for a given length of link and desired operating frequency is arrived at. Optimal configurations of all links in the NoC are identified and a power-performance optimal NoC is presented. We presents a latency, power and performance trade-off study of NoCs using link microarchitecture exploration. The design and implementation of a framework for such a design space exploration study is also presented. We present the trade-oﬀ study on NoCs by varying microarchitectural(e.g. pipelining) and circuit level(e.g. frequency and voltage) parameters. A System-C based NoC exploration framework is used to explore impacts of various architectural and microarchitectural level parameters of NoC elements on power and performance of the NoC. The framework enables the designer to choose from a variety of architectural options like topology, routing policy, etc., as well as allows experimentation with various microarchitectural options for the individual links like length, wire width, pitch, pipelining, supply voltage and frequency. The framework also supports a flexible traffic generation and communication model. Latency, power and throughput results using this framework to study a 4x4 CMP are presented. The framework is used to study NoC designs of a CMP using different classes of parallel computing benchmarks[6]. One of the key findings is that the average latency of a link can be reduced by increasing pipeline depth to a certain extent, as it enables link operation at higher link frequencies. Abstract There exists an optimum degree of pipelining which minimizes the energy-delay product of the link. In a 2D Torus when the longest link is pipelined by 4 stages at which point least latency(1.56 times minimum) is achieved and power(40% of max) and throughput (64%of max) are nominal. Using frequency scaling experiments, power variations of up to40%,26.6% and24% can be seen in 2D Torus, Reduced 2D Torus and Tree based NoC between various pipeline configurations to achieve same frequency at constant voltages. Also in some cases, we find that switching to a higher pipelining configuration can actually help reduce power as the links can be designed with smaller repeaters. We also find that the overall performance of the ICNs is determined by the lengths of the links needed to support the communication patterns. Thus the mesh seems to perform the best amongst the three topologies(Mesh, Torus and Folded Torus) considered in case studies. The effects of communication overheads on performance, power and energy of a multiprocessor chip using L1,L2 cache sizes as primary exploration parameters using accurate interconnect, processor, on-chip and off-chip memory modelling are presented. On-chip and off-chip communication times have significant impact on execution time and the energy efficiency of CMPs. Large cache simply larger tile area that result in longer inter-tile communication link lengths and latencies, thus adversely impacting communication time. Smaller caches potentially have higher number of misses and frequent of off-tile communication. Energy efficient tile design is a configuration exploration and trade-off study using different cache sizes and tile areas to identify a power-performance optimal configuration for the CMP. Trade-offs are explored using a detailed, cycle accurate, multicore simulation frame-work which includes superscalar processor cores, cache coherent memory hierarchies, on-chip point-to-point communication networks and detailed interconnect model including pipelining and latency. Sapphire, a detailed multiprocessor execution environment integrating SESC, Ruby and DRAM Sim was used to run applications from the Splash2 benchmark(64KpointFFT).Link latencies are estimated for a16 core CMP simulation on Sapphire. Each tile has a single processor, L1 and L2 caches and a router. Different sizesofL1 andL2lead to different tile clock speeds, tile miss rates and tile area and hence interconnect latency. Simulations across various L1, L2 sizes indicate that the tile configuration that maximizes energy efficiency is related to minimizing communication time. Experiments also indicate different optimal tile configurations for performance, energy and energy efficiency. Clustered interconnection network, communication aware cache bank mapping and thread mapping to physical cores are also explored as potential energy saving solutions. Results indicate that ignoring link latencies can lead to large errors in estimates of program completion times, of up to 17%. Performance optimal configurations are achieved at lower L1 caches and at moderateL2 cache sizes due to higher operating frequencies and smaller link lengths and comparatively lesser communication. Using minimal L1 cache size to operate at the highest frequency may not always be the performance-power optimal choice. Larger L1 sizes, despite a drop in frequency, offer a energy advantage due to lesser communication due to misses. Clustered tile placement experiments for FFT show considerable performance per watt improvement (1.2%). Remapping most accessed L2 banks by a process in the same core or neighbouring cores after communication traffic analysis offers power and performance advantages. Remapped processes and banks in clustered tile placement show a performance per watt improvement of5.25% and energy reductionof2.53%. This suggests that processors could execute a program in multiple modes, for example, minimum energy, maximum performance.

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48

Basavaraj, T. "NoC Design & Optimization of Multicore Media Processors". Thesis, 2013. http://etd.iisc.ernet.in/2005/3296.

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Network on Chips[1][2][3][4] are critical elements of modern System on Chip(SoC) as well as Chip Multiprocessor(CMP)designs. Network on Chips (NoCs) help manage high complexity of designing large chips by decoupling computation from communication. SoCs and CMPs have a multiplicity of communicating entities like programmable processing elements, hardware acceleration engines, memory blocks as well as off-chip interfaces. With power having become a serious design constraint[5], there is a great need for designing NoC which meets the target communication requirements, while minimizing power using all the tricks available at the architecture, microarchitecture and circuit levels of the de-sign. This thesis presents a holistic, QoS based, power optimal design solution of a NoC inside a CMP taking into account link microarchitecture and processor tile configurations. Guaranteeing QoS by NoCs involves guaranteeing bandwidth and throughput for connections and deterministic latencies in communication paths. Label Switching based Network-on-Chip(LS-NoC) uses a centralized LS-NoC Management framework that engineers traffic into QoS guaranteed routes. LS-NoC uses label switching, enables band-width reservation, allows physical link sharing and leverages advantages of both packet and circuit switching techniques. A flow identification algorithm takes into account band-width available in individual links to establish QoS guaranteed routes. LS-NoC caters to the requirements of streaming applications where communication channels are fixed over the lifetime of the application. The proposed NoC framework inherently supports heterogeneous and ad-hoc SoC designs. A multicast, broadcast capable label switched router for the LS-NoC has been de-signed, verified, synthesized, placed and routed and timing analyzed. A 5 port, 256 bit data bus, 4 bit label router occupies 0.431 mm2 in 130nm and delivers peak band-width of80Gbits/s per link at312.5MHz. LS Router is estimated to consume 43.08 mW. Bandwidth and latency guarantees of LS-NoC have been demonstrated on streaming applications like Hiper LAN/2 and Object Recognition Processor, Constant Bit Rate traffic patterns and video decoder traﬃc representing Variable Bit Rate traffic. LS-NoC was found to have a competitive figure of merit with state-of-the-art NoCs providing QoS. We envision the use of LS-NoC in general purpose CMPs where applications demand deterministic latencies and hard bandwidth requirements. Design variables for interconnect exploration include wire width, wire spacing, repeater size and spacing, degree of pipelining, supply, threshold voltage, activity and coupling factors. An optimal link configuration in terms of number of pipeline stages for a given length of link and desired operating frequency is arrived at. Optimal configurations of all links in the NoC are identified and a power-performance optimal NoC is presented. We presents a latency, power and performance trade-off study of NoCs using link microarchitecture exploration. The design and implementation of a framework for such a design space exploration study is also presented. We present the trade-oﬀ study on NoCs by varying microarchitectural(e.g. pipelining) and circuit level(e.g. frequency and voltage) parameters. A System-C based NoC exploration framework is used to explore impacts of various architectural and microarchitectural level parameters of NoC elements on power and performance of the NoC. The framework enables the designer to choose from a variety of architectural options like topology, routing policy, etc., as well as allows experimentation with various microarchitectural options for the individual links like length, wire width, pitch, pipelining, supply voltage and frequency. The framework also supports a flexible traffic generation and communication model. Latency, power and throughput results using this framework to study a 4x4 CMP are presented. The framework is used to study NoC designs of a CMP using different classes of parallel computing benchmarks[6]. One of the key findings is that the average latency of a link can be reduced by increasing pipeline depth to a certain extent, as it enables link operation at higher link frequencies. Abstract There exists an optimum degree of pipelining which minimizes the energy-delay product of the link. In a 2D Torus when the longest link is pipelined by 4 stages at which point least latency(1.56 times minimum) is achieved and power(40% of max) and throughput (64%of max) are nominal. Using frequency scaling experiments, power variations of up to40%,26.6% and24% can be seen in 2D Torus, Reduced 2D Torus and Tree based NoC between various pipeline configurations to achieve same frequency at constant voltages. Also in some cases, we find that switching to a higher pipelining configuration can actually help reduce power as the links can be designed with smaller repeaters. We also find that the overall performance of the ICNs is determined by the lengths of the links needed to support the communication patterns. Thus the mesh seems to perform the best amongst the three topologies(Mesh, Torus and Folded Torus) considered in case studies. The effects of communication overheads on performance, power and energy of a multiprocessor chip using L1,L2 cache sizes as primary exploration parameters using accurate interconnect, processor, on-chip and off-chip memory modelling are presented. On-chip and off-chip communication times have significant impact on execution time and the energy efficiency of CMPs. Large cache simply larger tile area that result in longer inter-tile communication link lengths and latencies, thus adversely impacting communication time. Smaller caches potentially have higher number of misses and frequent of off-tile communication. Energy efficient tile design is a configuration exploration and trade-off study using different cache sizes and tile areas to identify a power-performance optimal configuration for the CMP. Trade-offs are explored using a detailed, cycle accurate, multicore simulation frame-work which includes superscalar processor cores, cache coherent memory hierarchies, on-chip point-to-point communication networks and detailed interconnect model including pipelining and latency. Sapphire, a detailed multiprocessor execution environment integrating SESC, Ruby and DRAM Sim was used to run applications from the Splash2 benchmark(64KpointFFT).Link latencies are estimated for a16 core CMP simulation on Sapphire. Each tile has a single processor, L1 and L2 caches and a router. Different sizesofL1 andL2lead to different tile clock speeds, tile miss rates and tile area and hence interconnect latency. Simulations across various L1, L2 sizes indicate that the tile configuration that maximizes energy efficiency is related to minimizing communication time. Experiments also indicate different optimal tile configurations for performance, energy and energy efficiency. Clustered interconnection network, communication aware cache bank mapping and thread mapping to physical cores are also explored as potential energy saving solutions. Results indicate that ignoring link latencies can lead to large errors in estimates of program completion times, of up to 17%. Performance optimal configurations are achieved at lower L1 caches and at moderateL2 cache sizes due to higher operating frequencies and smaller link lengths and comparatively lesser communication. Using minimal L1 cache size to operate at the highest frequency may not always be the performance-power optimal choice. Larger L1 sizes, despite a drop in frequency, offer a energy advantage due to lesser communication due to misses. Clustered tile placement experiments for FFT show considerable performance per watt improvement (1.2%). Remapping most accessed L2 banks by a process in the same core or neighbouring cores after communication traffic analysis offers power and performance advantages. Remapped processes and banks in clustered tile placement show a performance per watt improvement of5.25% and energy reductionof2.53%. This suggests that processors could execute a program in multiple modes, for example, minimum energy, maximum performance.

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49

Pottepalem, Siddhardha. "Design and Analysis of Router Architectures for NoC". Thesis, 2015. http://ethesis.nitrkl.ac.in/7553/1/2015_Design_Pottepalem.pdf.

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The advance of process technology keeps on reducing the device size. As a result, the number of processing elements that can be integrated on a single chip (SoC) increases. The reduction in the device size also reducing the gate delay compared to the wire delay giving rise to increase in the frequency of operation of the devices. Further, in order to reduce the design time to market the communication system must support the plug and play architecture and should support design reuse. The conventional on-chip communication architecture, which consists of point-to-point connection and bus infrastructure, may not be able to provide sufficient communication requirements for SoC in terms of increasing the frequency of operation, providing reliability and flexibility. Further, conventional communication systems used for on-chip communication are not scalable and does not support design reuse. The NOC design represents a new paradigm to design multi-processor SoC which is scalable and supports design reuse. The NOC architecture uses layered protocols and packet switched networks which consist of on-chip routers, links and network interface on a predefined topology. NoC requires many on-chip resources which can increase the cost, area and power consumption. The efficiency of the NoC depends on how the resources are utilized for traversing the packet from source to destination which is determined by the flow control mechanism. The components which are used in the NoC for establishing communication between the modules of SoC were designed using VERILOG HDL. Different types of router architectures used by NoC were also designed mentioning their merits and demerits and their area and power consumption was also estimated

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50

El, Miligi Haytham. "Networks-on-chip: modeling, analysis, and design methodologies". Thesis, 2011. http://hdl.handle.net/1828/3633.

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The growing complexity of System-on-Chip (SoC) designs motivates both academic and industrial researchers to find better solutions for the complexity of the chip-interconnect. For SoC designs that have hundreds of Processing Elements (PEs), a single shared bus can no longer be accepted as an efficient communication scheme. To address this problem, the Networks-on-Chip (NoC) concept is proposed as a new paradigm, which provides an integrated solution for achieving efficient interconnection scheme for complex SoC applications. NoC-based designs are composed of computational resources in the form of PE cores, and switching nodes (routers) that allow PEs to communicate with each other. For different applications, this research work: 1) proposes new analytical models for various NoC design parameters, 2) performs comparative analyses of the commonly used network architectures, and 3) presents novel methodologies for efficiently designing the NoC-topology. The proposed methodologies are developed to help NoC-designers better achieve minimum power consumption and delay, and maximum performability for their applications. Graph-theoretic concepts are adopted to study the topological architecture of NoCs and propose a new topology-based models for network power, performability, and delay. The proposed models take into consideration important design parameters, which significantly affect the power, performability, and delay of a NoC-based system; such as network topology architecture, traffic distribution, noise power, voltage swing, probability of edge failure, router design and number of ports, clock frequency, and target technology. In this dissertation, we show how the proposed models could be used to optimally design the network topology so that it achieves the target design requirement for a given application. After studying each design metric individually, a joint consideration of NoC power, performability, and delay is carried out simultaneously. We use Particle Swarm Optimization (PSO) to find the optimum network topology, that achieves minimum delay, maximum performability, and minimum power consumption, for a given NoC application. Real case studies are presented to validate the proposed theoretical concepts. This validation is carried out through experimental work, targeting various real NoC applications. Experimental results show that using the proposed design methodologies, designers can improve the overall system efficiency in terms of power, delay, and performability, by choosing the design parameters (i.e., network topology architecture, PEs’ mapping, etc.) efficiently at early design phases. This improvement is measured in some cases by an order of magnitude, compared to the worst case scenario of choosing wrong design parameters for the target application.
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