Artigos de revistas sobre o tema "Non-Volatile SRAM"
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Wang, Ming Qian, Jie Tao Diao, Nan Li, Xi Wang e Kai Bu. "A Study on Reconfiguring On-Chip Cache with Non-Volatile Memory". Applied Mechanics and Materials 644-650 (setembro de 2014): 3421–25. http://dx.doi.org/10.4028/www.scientific.net/amm.644-650.3421.
Texto completo da fonteMispan, Mohd Syafiq, Aiman Zakwan Jidin, Muhammad Raihaan Kamarudin e Haslinah Mohd Nasir. "Lightweight hardware fingerprinting solution using inherent memory in off-the-shelf commodity devices". Indonesian Journal of Electrical Engineering and Computer Science 25, n.º 1 (1 de janeiro de 2022): 105. http://dx.doi.org/10.11591/ijeecs.v25.i1.pp105-112.
Texto completo da fonteAngizi, Shaahin, Navid Khoshavi, Andrew Marshall, Peter Dowben e Deliang Fan. "MeF-RAM: A New Non-Volatile Cache Memory Based on Magneto-Electric FET". ACM Transactions on Design Automation of Electronic Systems 27, n.º 2 (31 de março de 2022): 1–18. http://dx.doi.org/10.1145/3484222.
Texto completo da fonteVijay, H. M., e V. N. Ramakrishnan. "Radiation effects on memristor-based non-volatile SRAM cells". Journal of Computational Electronics 17, n.º 1 (8 de novembro de 2017): 279–87. http://dx.doi.org/10.1007/s10825-017-1080-x.
Texto completo da fonteSingh, Damyanti, Neeta Pandey e Kirti Gupta. "Process invariant Schmitt Trigger non-volatile 13T1M SRAM cell". Microelectronics Journal 135 (maio de 2023): 105773. http://dx.doi.org/10.1016/j.mejo.2023.105773.
Texto completo da fonteJanniekode, Uma Maheshwar, Rajendra Prasad Somineni, Osamah Ibrahim Khalaf, Malakeh Muhyiddeen Itani, J. Chinna Babu e Ghaida Muttashar Abdulsahib. "A Symmetric Novel 8T3R Non-Volatile SRAM Cell for Embedded Applications". Symmetry 14, n.º 4 (7 de abril de 2022): 768. http://dx.doi.org/10.3390/sym14040768.
Texto completo da fontePriya, G. Lakshmi, Namita Rawat, Abhishek Sanagavarapu, M. Venkatesh e A. Andrew Roobert. "Hybrid Silicon Substrate FinFET-Metal Insulator Metal (MIM) Memristor Based Sense Amplifier Design for the Non-Volatile SRAM Cell". Micromachines 14, n.º 2 (17 de janeiro de 2023): 232. http://dx.doi.org/10.3390/mi14020232.
Texto completo da fonteKhan, Asif. "(Invited) Ferroelectric Field-Effect Transistors as High-Density, Ultra-fast, Embedded Non-Volatile Memories". ECS Meeting Abstracts MA2022-02, n.º 15 (9 de outubro de 2022): 805. http://dx.doi.org/10.1149/ma2022-0215805mtgabs.
Texto completo da fontePan, James N. "Atomic Force High Frequency Phonons Non-volatile Dynamic Random-Access Memory Compatible with Sub-7nm ULSI CMOS Technology". MRS Advances 4, n.º 48 (2019): 2577–84. http://dx.doi.org/10.1557/adv.2019.212.
Texto completo da fonteP, Saleem Akram. "Non-Volatile 7T1R SRAM cell design for low voltage applications". International Journal of Emerging Trends in Engineering Research 7, n.º 11 (15 de novembro de 2019): 704–7. http://dx.doi.org/10.30534/ijeter/2019/487112019.
Texto completo da fonteWang, Jinhui, Lina Wang, Haibin Yin, Zikui Wei, Zezhong Yang e Na Gong. "cNV SRAM: CMOS Technology Compatible Non-Volatile SRAM Based Ultra-Low Leakage Energy Hybrid Memory System". IEEE Transactions on Computers 65, n.º 4 (1 de abril de 2016): 1055–67. http://dx.doi.org/10.1109/tc.2014.2375187.
Texto completo da fonteJafari, Atousa, Christopher Münch e Mehdi Tahoori. "A Spintronic 2M/7T Computation-in-Memory Cell". Journal of Low Power Electronics and Applications 12, n.º 4 (6 de dezembro de 2022): 63. http://dx.doi.org/10.3390/jlpea12040063.
Texto completo da fonteJovanovic, Bojan, Raphael Brum e Lionel Torres. "MTJ-based hybrid storage cells for “normally-off and instant-on” computing". Facta universitatis - series: Electronics and Energetics 28, n.º 3 (2015): 465–76. http://dx.doi.org/10.2298/fuee1503465j.
Texto completo da fonteSharma, Parul, Balwinder Raj e Sandeep Singh Gill. "Spintronics Based Non-Volatile MRAM for Intelligent Systems". International Journal on Semantic Web and Information Systems 18, n.º 1 (1 de janeiro de 2022): 1–16. http://dx.doi.org/10.4018/ijswis.310056.
Texto completo da fonteMounica, J., e G. V. Ganesh. "Design Of A Nonvolatile 8T1R SRAM Cell For Instant-On Operation". International Journal of Electrical and Computer Engineering (IJECE) 6, n.º 3 (1 de junho de 2016): 1183. http://dx.doi.org/10.11591/ijece.v6i3.9448.
Texto completo da fonteMounica, J., e G. V. Ganesh. "Design Of A Nonvolatile 8T1R SRAM Cell For Instant-On Operation". International Journal of Electrical and Computer Engineering (IJECE) 6, n.º 3 (1 de junho de 2016): 1183. http://dx.doi.org/10.11591/ijece.v6i3.pp1183-1189.
Texto completo da fonteGe, Fen, Lei Wang, Ning Wu e Fang Zhou. "A Cache Fill and Migration Policy for STT-RAM-Based Multi-Level Hybrid Cache in 3D CMPs". Electronics 8, n.º 6 (6 de junho de 2019): 639. http://dx.doi.org/10.3390/electronics8060639.
Texto completo da fonte., D. Ane Delphin. "DESIGN OF A 4-BIT NON-VOLATILE SRAM USING MAGNETIC TUNNEL JUNCTION". International Journal of Research in Engineering and Technology 05, n.º 16 (25 de maio de 2016): 186–91. http://dx.doi.org/10.15623/ijret.2016.0516039.
Texto completo da fonteLemanov, V. V., Yu V. Frolov, A. A. Iofan e V. K. Yarmarkin. "Some physical and technological aspects of designing of ferroelectric non-volatile SRAM". Microelectronic Engineering 29, n.º 1-4 (dezembro de 1995): 37–40. http://dx.doi.org/10.1016/0167-9317(95)00111-5.
Texto completo da fonteItoh, Kiyoo. "Trends in low-voltage embedded-RAM technology". Facta universitatis - series: Electronics and Energetics 15, n.º 1 (2002): 1–12. http://dx.doi.org/10.2298/fuee0201001i.
Texto completo da fonteShin, Donghwa. "Design Space Exploration of EEPROM-SRAM Hybrid Non-volatile Counter Considering Energy Consumption and Memory Endurance". IEMEK Journal of Embedded Systems and Applications 11, n.º 4 (31 de agosto de 2016): 201–8. http://dx.doi.org/10.14372/iemek.2016.11.4.201.
Texto completo da fonteBazzi, Hussein, Hassen Aziza, Mathieu Moreau e Adnan Harb. "Performances and Stability Analysis of a Novel 8T1R Non-Volatile SRAM (NVSRAM) versus Variability". Journal of Electronic Testing 37, n.º 4 (agosto de 2021): 515–32. http://dx.doi.org/10.1007/s10836-021-05965-x.
Texto completo da fonteLin, Zhiting, Yong Wang, Chunyu Peng, Wenjuan Lu, Xuan Li, Xiulong Wu e Junning Chen. "Read‐decoupled 8T1R non‐volatile SRAM with dual‐mode option and high restore yield". Electronics Letters 55, n.º 9 (maio de 2019): 519–21. http://dx.doi.org/10.1049/el.2019.0295.
Texto completo da fonteJunsangsri, Pilin, Jie Han e Fabrizio Lombardi. "Design of a hybrid non-volatile SRAM cell for concurrent SEU detection and correction". Integration 52 (janeiro de 2016): 156–67. http://dx.doi.org/10.1016/j.vlsi.2015.09.005.
Texto completo da fonteAbbasi, Alireza, Farbod Setoudeh, Mohammad Bagher Tavakoli e Ashkan Horri. "A novel design of high performance and robust ultra-low power SRAM cell based on memcapacitor". Nanotechnology 33, n.º 16 (24 de janeiro de 2022): 165202. http://dx.doi.org/10.1088/1361-6528/ac46d6.
Texto completo da fonteBagheriye, Leila, Siroos Toofan, Roghayeh Saeidi, Behzad Zeinali e Farshad Moradi. "A Reduced Store/Restore Energy MRAM-Based SRAM Cell for a Non-Volatile Dynamically Reconfigurable FPGA". IEEE Transactions on Circuits and Systems II: Express Briefs 65, n.º 11 (novembro de 2018): 1708–12. http://dx.doi.org/10.1109/tcsii.2017.2768409.
Texto completo da fonteRani, Khushboo, e Hemangee K. Kapoor. "Write-variation aware alternatives to replace SRAM buffers with non-volatile buffers in on-chip interconnects". IET Computers & Digital Techniques 13, n.º 6 (1 de novembro de 2019): 481–92. http://dx.doi.org/10.1049/iet-cdt.2019.0039.
Texto completo da fonteAsad, Arghavan, Mahdi Fazeli, Mohammad Reza Jahed-Motlagh, Mahmood Fathy e Farah Mohammadi. "An Energy-Efficient Reliable Heterogeneous Uncore Architecture for Future 3D Chip-Multiprocessors". Journal of Circuits, Systems and Computers 28, n.º 13 (12 de março de 2019): 1950224. http://dx.doi.org/10.1142/s0218126619502244.
Texto completo da fonteKanika, R. Sankara Prasad, Nitin Chaturvedi e S. Gurunarayanan. "A low power high speed MTJ based non-volatile SRAM cell for energy harvesting based IoT applications". Integration 65 (março de 2019): 43–50. http://dx.doi.org/10.1016/j.vlsi.2018.11.002.
Texto completo da fonteHraziia, Adam Makosiej, Giorgio Palma, Jean-Michel Portal, Marc Bocquet, Olivier Thomas, Fabien Clermidy et al. "Operation and stability analysis of bipolar OxRRAM-based Non-Volatile 8T2R SRAM as solution for information back-up". Solid-State Electronics 90 (dezembro de 2013): 99–106. http://dx.doi.org/10.1016/j.sse.2013.02.045.
Texto completo da fonteZhang, Honghong, e Guoguo Zhang. "Review of Research on Storage Development". Scalable Computing: Practice and Experience 22, n.º 3 (21 de novembro de 2021): 365–85. http://dx.doi.org/10.12694/scpe.v22i3.1904.
Texto completo da fonteLuo, Yandong, Panni Wang e Shimeng Yu. "Accelerating On-Chip Training with Ferroelectric-Based Hybrid Precision Synapse". ACM Journal on Emerging Technologies in Computing Systems 18, n.º 2 (30 de abril de 2022): 1–20. http://dx.doi.org/10.1145/3473461.
Texto completo da fonteEscuin, Carlos, Pablo Ibáñez, Denis Navarro, Teresa Monreal, José M. Llabería e Víctor Viñals. "L2C2: Last-level compressed-contents non-volatile cache and a procedure to forecast performance and lifetime". PLOS ONE 18, n.º 2 (7 de fevereiro de 2023): e0278346. http://dx.doi.org/10.1371/journal.pone.0278346.
Texto completo da fonteGarzón, Esteban, Adam Teman e Marco Lanuzza. "Embedded Memories for Cryogenic Applications". Electronics 11, n.º 1 (25 de dezembro de 2021): 61. http://dx.doi.org/10.3390/electronics11010061.
Texto completo da fonteZhang, Tiefei, Jixiang Zhu, Jun Fu e Tianzhou Chen. "CWC: A Companion Write Cache for Energy-Aware Multi-Level Spin-Transfer Torque RAM Cache Design". Journal of Circuits, Systems and Computers 24, n.º 06 (26 de maio de 2015): 1550079. http://dx.doi.org/10.1142/s0218126615500796.
Texto completo da fontePandu, Ratnakar. "CrFe 2O4 - BiFeO3 Perovskite Multiferroic Nanocomposites – A Review". Material Science Research India 11, n.º 2 (24 de dezembro de 2014): 128–45. http://dx.doi.org/10.13005/msri/110206.
Texto completo da fonte"Low Power Non-Volatile 7T1M Subthreshold SRAM Cell". Indian Journal of Pure & Applied Physics, 2022. http://dx.doi.org/10.56042/ijpap.v60i12.67455.
Texto completo da fonte"Memristor based Non-Volatile Random Access Memory Cell by 45nm CMOS Techology". International Journal of Recent Technology and Engineering 9, n.º 1 (30 de maio de 2020): 1432–35. http://dx.doi.org/10.35940/ijrte.f8714.059120.
Texto completo da fonteRaman, Siddhartha Raman Sundara, S. S. Nibhanupudi e Jaydeep P. Kulkarni. "Enabling In-Memory Computations in Non-Volatile SRAM Designs". IEEE Journal on Emerging and Selected Topics in Circuits and Systems, 2022, 1. http://dx.doi.org/10.1109/jetcas.2022.3174148.
Texto completo da fonteBazzi, Hussein, Adnan Harb, Hassen Aziza e Mathieu Moreau. "Non-volatile SRAM memory cells based on ReRAM technology". SN Applied Sciences 2, n.º 9 (8 de agosto de 2020). http://dx.doi.org/10.1007/s42452-020-03267-z.
Texto completo da fonteBadri, Satya Jaswanth, Mukesh Saini e Neeraj Goel. "Mapi-Pro: An Energy Efficient Memory Mapping Technique for Intermittent Computing". ACM Transactions on Architecture and Code Optimization, 20 de outubro de 2023. http://dx.doi.org/10.1145/3629524.
Texto completo da fonteGupta, Pankaj, Kanchan Sharma e Sneha Barnawal. "LOW POWER NON-VOLATILE 11T2R and 13T2R SRAM CELL USING MEMRISTOR". Telecommunications and Radio Engineering, 2021. http://dx.doi.org/10.1615/telecomradeng.2021038115.
Texto completo da fonteKumar, C. S. Hemanth, e B. S. Kariyappa. "Node Voltage and KCL Model-Based Low Leakage Volatile and Non-Volatile 7T SRAM Cells". IETE Journal of Research, 8 de fevereiro de 2022, 1–17. http://dx.doi.org/10.1080/03772063.2022.2027279.
Texto completo da fontePrinz, Erwin Josef. "Materials Challenges in Automotive Embedded Non-Volatile Memories". MRS Proceedings 997 (2007). http://dx.doi.org/10.1557/proc-0997-i02-01.
Texto completo da fonteSingh, Damyanti, Neeta Pandey e Kirti Gupta. "Schmitt Trigger 12T1M Non-volatile SRAM Cell with Improved Process Variation Tolerance". AEU - International Journal of Electronics and Communications, fevereiro de 2023, 154573. http://dx.doi.org/10.1016/j.aeue.2023.154573.
Texto completo da fonteBazzi, Hussein, Adnan Harb, Hassen Aziza, Mathieu Moreau e Abdallah Kassem. "RRAM-based non-volatile SRAM cell architectures for ultra-low-power applications". Analog Integrated Circuits and Signal Processing, 24 de janeiro de 2020. http://dx.doi.org/10.1007/s10470-020-01587-z.
Texto completo da fonteSivakumar, S., John Jose e Vijaykrishnan Narayanan. "Enhancing Lifetime and Performance of MLC NVM Caches using Embedded Trace buffers". ACM Transactions on Design Automation of Electronic Systems, 16 de abril de 2024. http://dx.doi.org/10.1145/3659102.
Texto completo da fonteWang, Jianjian, Jinshun Bi, Gang Liu, Hua Bai, Kai Xi, Bo Li, Sandip Majumdar, Lanlong Ji, Ming Liu e Zhangang Zhang. "Simulations of single event effects on the ferroelectric capacitor-based non-volatile SRAM design". Science China Information Sciences 64, n.º 4 (19 de novembro de 2020). http://dx.doi.org/10.1007/s11432-019-2854-9.
Texto completo da fonteZhao, Dongyan, Yubo Wang, Yanning Chen, Jin Shao, Zhen Fu, Guangyao Wang, Peng Zhang, Cheng Pan e Biao Pan. "Radiation Hardening Design of Non-Volatile Hybrid Flip-Flop Based on Spin Orbit Torque MTJ and SRAM". SPIN, 17 de junho de 2022. http://dx.doi.org/10.1142/s2010324722500163.
Texto completo da fonteHyun, Gihwan, Batyrbek Alimkhanuly, Donguk Seo, Minwoo Lee, Junseong Bae, Seunghyun Lee, Shubham Patil et al. "CMOS‐Integrated Ternary Content Addressable Memory using Nanocavity CBRAMs for High Sensing Margin". Small, 12 de abril de 2024. http://dx.doi.org/10.1002/smll.202310943.
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