Teses / dissertações sobre o tema "Neuromorphic devices"

The organic polymer has gained considerable interest in the field of bioelectronics during the last few decades. Organic materials based devices have several unique characteristics; low-cost and low thermal budget fabrication processes, tunable properties through chemical synthesis, flexibility and biocompatibility. Those entire features make organic materials suitable for new functionalities in comparison to their inorganic counterparts. Moreover, the attributes mentioned earlier give an additional degree of freedom to use organic materials in neuromorphic devices whose functions have the potential to induce biological realism in brain-inspired information processing. Nowadays, neuromorphic devices have attracted the interest in research and industry. The use of organic materials might lead to a new class of neuromorphic devices that has several applications in areas that range from brain-computer interfaces to circuits for local data processing in energy restricted environments. However, flexibility and biocompatibility helps to optimize the mechanical mismatch between electronics and biological substances that might be a new way of signal processing at the interface with biology. In this thesis project, three-terminal organic polymer-based Organic Electrochemical Transistors (OECTs) have fabricated in cleanroom-based fabrication process. PEDOT:PSS and p(g2T-TT) thin-film polymers were used as active channel materials in OECTs. Ions inject from the liquid electrolytes by using a specific gate bias. The migrated ions modulate the entire bulk-volume conductivity of the organic polymer channel due to the strong coupling between ionic and electronic charges within the channel. Several electrical characterizations of OECTs were investigated in the presence of liquid electrolytes. The memory phenomena of PEDOT:PSS and p(g2T-TT) polymer-based OECTs were systematically studied in this work. It was observed that PEDOT:PSS organic polymer shows no memory properties/negligible memory, and p(g2T-TT) polymer exhibits memory phenomena due to its unique polymer structure. It also seen that the memory process in p(g2T-TT) polymer is a reversible process that can be return to its initial state by applying opposite gate bias. Beside it, the polymer's behavior also was investigated in contact with and without aqueous solutions. Additionally, it observed that p(g2T-TT) polymer is less hydrophilic compared to PEDOT:PSS due to its intrinsic properties. Multiple memory devices were fabricated at different times and reproducible memory phenomenon was observed in OECTs.

Depuis les années soixante-dix l'évolution des performances des circuits électroniques repose exclusivement sur l'amélioration des performances des transistors. Ce composant a des propriétés extraordinaires puisque lorsque ses dimensions sont réduites, toutes ses caractéristiques sont améliorées. Mais, dû à certaines limites physiques fondamentales, la diminution des dimensions des transistors n’est plus possible. Néanmoins, de nouveaux nano-composants mémoire innovants qui peuvent être intégré conjointement avec les transistors voient le jour tant au niveau académique qu'industriel, ce qui constitue une opportunité pour repenser complètement l'architecture des circuits électroniques actuels. L'une des voies de recherche possible est l’inspiration du fonctionnement du cerveau biologique. Ce dernier peut accomplir des tâches complexes et variées en consommant très peu d’énergie. Ces travaux de thèse explorent trois paradigmes neuro-inspirés pour l'utilisation de ces composants mémoire. Chacune de ces approches explore différentes problématiques du calcul en mémoire
While electronics has prospered inexorably for several decades, its leading source of progress will stop in the next coming years, due to the fundamental technological limits of transistors. Nevertheless, microelectronics is currently offering a major breakthrough: in recent years, memory technologies have undergone incredible progress, opening the way for multiple research venues in embedded systems. Additionally, a major feature for future years will be the ability to integrate different technologies on the same chip. new emerging memory devices that can be embedded in the core of the CMOS, such as Resistive Random Access Memory (RRAM) or Spin Torque Magnetic Tunnel Junction (STMRAM) based on naturally intelligent inmemory-computing architecture. Three braininspired algorithms are carefully examined: Bayesian reasoning binarized neural networks, and an approach that further exploits the intrinsic behavior of components, population coding of neurons. Each of these approaches explores different aspects of in-memory computing

Future computing will require significant development in new computing device paradigms. This is motivated by CMOS devices reaching their technological limits, the need for non-Von Neumann architectures as well as the energy constraints of wearable technologies and embedded processors. The first device proposal, an energy-efficient voltage-controlled domain wall device for implementing an artificial neuron and synapse is analyzed using micromagnetic modeling. By controlling the domain wall motion utilizing spin transfer or spin orbit torques in association with voltage generated strain control of perpendicular magnetic anisotropy in the presence of Dzyaloshinskii-Moriya interaction (DMI), different positions of the domain wall are realized in the free layer of a magnetic tunnel junction to program different synaptic weights. Additionally, an artificial neuron can be realized by combining this DW device with a CMOS buffer. The second neuromorphic device proposal is inspired by the brain. Membrane potential of many neurons oscillate in a subthreshold damped fashion and fire when excited by an input frequency that nearly equals their Eigen frequency. We investigate theoretical implementation of such “resonate-and-fire” neurons by utilizing the magnetization dynamics of a fixed magnetic skyrmion based free layer of a magnetic tunnel junction (MTJ). Voltage control of magnetic anisotropy or voltage generated strain results in expansion and shrinking of a skyrmion core that mimics the subthreshold oscillation. Finally, we show that such resonate and fire neurons have potential application in coupled nanomagnetic oscillator based associative memory arrays.

La present tesi recull els resultats de la recerca orientada a aportar una metodologia de caracterització elèctrica, modelat i simulació per a dispositius de commutació resistiva, quan es consideren aplicacions de computació neuromòrfica basades en aprenentatge no-supervisat, àmpliament demandades en l’actualitat com a solució de baix consum a les següents problemàtiques: per una banda, la limitació de la velocitat en la transferència de dades entre les unitats de memoria i processament que té lloc en les arquitectures de computador convencional (von Neumann). Per altra banda, la necessitat creixent de sistemes computacionals que realitzin tasques de classificació, anàlisi i inferència de quantitats massives de dades (per exemple, per a aplicacions de Big Data), junt amb tasques de detecció de patrons, predicció de comportaments i presa de decisions (aplicacions enfocades a Internet-of-Things, entre d’altres). En concret, s’investiguen els dispositius Oxide-based Resistive Random Access Memory (OxRAM) com a candidats per a la implementació electrònica de sinapsis en xarxes neuronals artificials físiques, altrament anomenades arquitectures neuromòrfiques. En primer lloc, es presenta una introducció teòrica a les diferents tecnologies electròniques amb propietats de commutació resistiva i memòria no volàtil, junt amb les figures de mèrit de cadascuna d’aquestes, tan demostrades com projectades segons l’International Roadmap for Devices and Systems de 2018. Amb aquest primer capítol, es pretén proveïr al lector de les bases necessàries per a poder comprendre els resultats exposats en els següents capítols. A continuació i mitjançant un enfocament bottom-up dividit en tres capítols, es tracten els procediments i resultats de la caracterització elèctrica i modelat dels dispositius estudiats per a la implementació de sinapsis electròniques analògiques. Com a punt de partida, es verifica experimentalment que els dispositius compleixen els requisits necessaris per a l’aplicació indicada. Al següent capítol, es demostren de forma experimental dues regles d’aprenentatge fonamentals per a poder executar algorismes d’aprenentatge autònoms (no supervisats) sobre una arquitectura neuromòrfica basada en els dispositius analitzats. Les regles d’aprenentatge demostrades permeten que els dispositius emulin procesos i mecanismes d’aprenentatge reportats en el camp de les neurociències, tals com la dependència temporal de la plasticitat, o el fenòmen de condicionament clàssic, per al qual es replica l’experiment dels gossos de Pavlov, permetent establir els fonaments de l’aprenentatge associatiu en dos o més dispositius. Per a concloure aquesta part relativa a les sinapsis electròniques analògiques, es proposa l’adaptació hardware d’un algorisme d’aprenentatge no supervisat. L’algorisme dissenyat permet que el sistema organitzi les seves connexions de forma autònoma i no supervisada, de tal manera que, un cop entrenada, la xarxa neuronal física mostri una organització topogràfica a la seva capa de sortida, que és característica de les regions del cervell biològic dedicades al processament de la informació sensorial. A més, el disseny del sistema permet concatenar diverses xarxes neuronals per a poder executar tasques cognitives de naturalesa més complexa, tals com l’associació de diferents atributs a un mateix concepte, permetent la computació jeràrquica. L’últim capítol està dedicat a l’estudi de dispositius OxRAM quan es considera un mode d’operació de baix consum, per a la implementació de sinapsis binàries. De nou, amb una perspectiva bottom-up, es parteix de la caracterització elèctrica i modelat dels dispositius, que en aquest cas constitueixen un xip neuromòrfic. Es verifica una regla d’aprenentatge probabilística, que després s’empra en un algorisme d’aprenentatge no supervisat dissenyat per a la inferència i predicció de seqüències periòdiques. Per acabar, es discuteixen les diferències i similituds entre els dos algorismes descrits a la tesi, i es proposa com es poden fer servir cadascun d’aquests de forma conjunta i complementària.
The present thesis compiles the results of the research oriented to provide a methodology for the electrical characterization, modeling and simulation of resistive switching devices, taking into consideration neuromorphic applications based on unsupervised learning This is widely demanded today as a low-consumption solution to the following issues: on the one hand, the speed limitations that take place in data transfer between the memory and processing units that takes place in conventional computer architectures. On the other hand, the growing need for low-power computational systems that perform tasks of classification, analysis and inference of massive amounts of data (for example, for Big Data applications), together with pattern recognition, prediction of behaviors and decision-making tasks (for applications focused on Internet-of-Things, among others). Specifically, Oxide-based Resistive Random Access Memory (OxRAM) devices are investigated as candidates for the electronic implementation of synapses in physical artificial neural networks, also referred to as neuromorphic architectures. First of all, a theoretical introduction to the different electronic technologies with resistive switching and non-volatile memory properties is provided. The figures of merit demonstrated and projected of each one of them are indicated according to the International Roadmap for Devices and Systems of 2018. With this first chapter, the intention is to provide the reader with the necessary background required to understand the results outlined in the following chapters. Next, and by using a bottom-up approach divided into the three following chapters, the procedures and results of the electrical characterization and modeling of the OxRAM devices studied for the implementation of analog electronic synapses are discussed. As a starting point, it is experimentally verified that the devices meet the requirements for the indicated application. In the following chapter, two fundamental learning rules are demonstrated experimentally in order to permit the execution of an autonomous (unsupervised) learning algorithm on a neuromorphic architecture based on the tested devices. The proven learning rules allow the devices to emulate certain processes and learning mechanisms reported in the neuroscience field, such as spike-timing dependent plasticity, or the classical conditioning phenomenon, for which Pavlov’s dog experiment is replicated as to establish the foundations of associative learning, to be implemented between two or more synaptic devices. To conclude this part related to analog electronic synapses, the hardware adaptation of an unsupervised learning algorithm is proposed. The designed algorithm provides the system with the property of self-organization, in such a way that, once trained, the physical neuronal network shows a topographical organization in its output layer, which is characteristic of the sensory processing areas of the biological brain. Furthermore, the proposed design and algorithm allow the concatenation of several neuronal networks, in order to execute cognitive tasks of a more complex nature, such as the association of different attributes to the same concept, related to hierarchical computation. The last chapter is dedicated to the study of OxRAM devices when a low-power mode is considered, for the implementation of binary synapses. Again using a bottom-up perspective, the chapter begins with the electrical characterization and modeling of the devices, which in this case constitute a neuromorphic chip. A probabilistic learning rule is demonstrated, which is then used in an unsupervised on-line learning algorithm designed for the inference and prediction of periodic temporal sequences. Finally, the differences and similarities between the two algorithms described in the thesis are discussed, and a proposal is made as to how each of these can be used in a joint and complementary way.

The aggressive scaling of CMOS technology, to reduce device size while also increasing device performance, has reached a point where continuing improvement is becoming increasingly problematic and alternative routes for the development of future memory and processing devices may be necessary; in this thesis the use of phase-change and carbon based materials as one such alternative route is investigated. As pointed out by Ovshinsky [1, 2] some phase-change material should be capable of non-binary arithmetic processing, multi-value logic and biological (neuromorphic) type processing. In this thesis, generic, nanometre-sized, phase-change pseudodevices were fabricated and utilised to perform various types of computational operations for the first time, including addition, subtraction, division, parallel factorization and logic using a novel resistive switching accumulator-type regime in the electrical domain. The same accumulator response is also shown to provide an electronic mimic of an integrate-and-fire type neuron. The accumulator-type regime uses fast electrical pulses to gradually crystallize a phase-change device in a finite number of steps and does not require a multilevel detection scheme. The phase-change materials used in this study were protected by a capping layer of sputtered amorphous carbon. It was found that this amorphous carbon layer also underwent a form of resistive switching when subjected to electrical pulses. In particular, sputtered amorphous carbon layers were found to switch from an initially high resistivity state to a low resistivity state when a voltage pulse was locally applied using a Conductive Atomic Force Microscope (CAFM) tip. Further experiments on amorphous carbon vertical pseudo-devices and lithographically defined planar devices showed that it has potential as a new material for Resistive Random Access Memory (ReRam) applications. The switching mechanism was identified as clustering of the sp2 hybridized carbon sites induced by Joule heating. It was not possible to reset the devices back to their initial high resistivity state presumably due to the highly conductive nature of sputtered amorphous carbon.

Hardware computation is facing in the present age a deep transformation of its own paradigms. Silicon based computation is reaching its limit due to the physical constraints of transistor technology. As predicted by the Moore’s law, downscaling of transistor dimensions doubled each year since the 60s, leading nowadays to the extreme of 16-nm channel width of the present state-of-the-art technology. No further improvement is possible, since laws of physics impose a different electrical behavior when lower dimensions are attempted. Multiple solutions are then envisaged, spanning the range from quantum computing to neuromorphic computing. The present dissertation wants to be a preliminary study for understanding the opportunities enabled by neuromorphic computing based on resistive switching memories. In particular, brain inspires technology and architecture of new generation processors because of its unique properties: parallel and distributed computation, superposition of processing and memory unit, low power consumption, to cite only some of them. Such features make brain particularly efficient and robust against degraded data, further than particularly suitable to process and store in memory new nformation. Despite many research projects and some commercial products are already proposing brain-like computing processors, like spiNNaker or IBM’s Bluenorth, they only mimic the brain functioning with standard Silicon technology, that is inherently serial and distinguish between processing and memory unit. Resistive switching technology on the other hand, would allow to overcome many of these issues, enabling a far better match between biological and artificial neuromorphic computation. Resistive switching are, generally speaking, Metal-Insulator-Metal structures able to change their electrical conductance as a consequence of the history of applied electric signal. In such sense, they behave exactly as synapses do in a biological neural networks. For this reason, resistive switching when modeled as memristor, i.e. memory-resistor, can act as artificial synapses and, moreover, are particularly suitable to be interfaced with artificial Silicon neurons that are designed to replicate the biological behavior when excited with electric pulses. Anyhow, from the technological standpoint, there is still no standard on the design and fabrication of resistive switching, so that multiple structure and materials are investigated. In this dissertation, it is reported an analysis of multiple resistive switching devices, based on various materials, i.e. TiO2, ZnO and HfO, and device architectures, i.e. thin film and nanostructured devices, with the scope of both characterizing and comprehending the physics behind resistive switching phenomena. Furthermore, numerical simulations of artificial spiking neural networks, embedding Silicon neurons and HfO-based resistive switching are designed and performed, in order to give a systematic analysis of the performances reached by this new kind of computing paradigm.

Alors que les exigences en matière d'IA augmentent, de nouveaux paradigmes informatiques deviennent essentiels. Les architectures traditionnelles de von Neumann peinent à répondre aux exigences intensives de l'IA. L'informatique neuromorphique, inspirée par le cerveau, intègre traitement et mémoire pour une computation plus rapide et efficace, idéale pour des applications d'IA comme l'apprentissage profond et la reconnaissance de formes. Les matériaux clés pour l'informatique neuromorphique incluent les synaptors et les neuristors. Les memristors, des mémoires non volatiles fabriquées à partir d'oxydes tels que HfO2 et TiO2, imitent le comportement synaptique en changeant d'état via des filaments à l'échelle nanométrique ou des transitions de phase. Quant aux neuristors, ils imitent le celui du déclenchement des neurones en utilisant des memristors et des circuits résistance-condensateur reproduisant le modèle LIF (Leaky, Integrate, and Fire). À température ambiante, l’isolant de Mott VO2 remplit les fonctions neuronales en formant des chemins conducteurs volatiles. Cependant, les synaptors et les neuristors nécessitent souvent des matériaux différents. L'optimisation de VO2 comme synapse pourrait lui permettre de remplir les deux fonctions à température ambiante.Étudier des systèmes à séparation de phases comme VO2 reste complexe en raison des inhomogénéités. Les avancées en microscopie infrarouge et optique permettent désormais d'imager ces régions avec une résolution nanométrique. Les techniques de champ proche peuvent sonder la conductivité locale à l'échelle nanométrique. Cependant, ces sondes ont des limites : (i) des scans longs pour les inhomogénéités plus grandes et (ii) des transitions de phase induites par la température causant des dérives thermiques et des comparaisons d'images difficiles. Pour y remédier, nous avons développé un système de microscopie optique à champ lointain pour étudier les transitions de phase dans le VO2. Ce système exploite le contraste optique entre les phases isolantes et métalliques, observable des nanomètres aux microns.Nous avons mis en œuvre différents protocoles de température en imagerie continue, compensant la dérive thermique et alignant des images nettes. Cela permet des traces temporelles de pixels uniques pour indiquer les températures spécifiques de transition de phase. Nous avons tout d’abord cartographié la température critique (Tc), la largeur de transition (ΔTc) et leur netteté (δTc). Ces cartographies pourraient permettre d'adapter les propriétés du VO2 pour des applications spécifiques comme les dispositifs de mémoire et les composants à commutation rapide. Nous avons également présenté la première imagerie optique de la mémoire à inversion de rampe (RRM) dans le VO2, montrant l'évolution des clusters pendant l'entraînement thermique. L'accumulation de mémoire se produit aux frontières des clusters et à l'intérieur des patchs, suggérant une diffusion préférentielle des défauts ponctuels.De plus, nous avons mené une analyse d'apprentissage automatique (ML) des motifs fractals dans le VO2, en utilisant le ML pour classifier l'Hamiltonien, conduisant à la formation de motifs. Notre réseau neuronal convolutionnel (CNN) a atteint une haute précision avec des données synthétiques et expérimentales, confirmant la formation de motifs due à la proximité d'un point critique du modèle Ising 2D à champ aléatoire. Cela, combiné à la réduction de symétrie et à la quantification de confiance, offre un puissant nouvel outil pour analyser les transitions de phase complexes dans les matériaux corrélés. Notre recherche fournit une nouvelle méthode de caractérisation optique pour comprendre la dynamique de transition du VO2 et introduit des approches innovantes pour des applications non-mémoires. Ces perspectives posent les bases d'études futures explorant le potentiel de la RRM et étendant les cadres ML à d'autres matériaux corrélés
As AI demands grow, new computing paradigms are essential. Traditional von Neumann architectures struggle with intensive AI requirements. Neuromorphic computing, inspired by the brain, integrates processing and memory for faster, efficient computation, ideal for AI applications like deep learning and pattern recognition.Key materials for neuromorphic computing include synaptors and neuristors. Memristors, non-volatile memories made from oxides like HfO2 and TiO2, mimic synaptic behavior by switching states via nanoscale filaments or phase transitions. Neuristors emulate neuron spiking behavior using memristors and resistance-capacitance circuits to replicate the Leaky, Integrate, and Fire model. Mott insulators like VO2 mimic neuron-like behavior by forming volatile conductive pathways. However, synaptors and neuristors often require different materials. Optimizing VO2 for synaptic behavior could enable it to serve both functions at room temperature.Studying phase-separated systems like VO2 is complex due to inhomogeneities. Advances in infrared and optical microscopy now allow imaging these regions with nanometer-scale resolution. Near-field techniques, using atomic force microscopes coupled to IR lasers, can probe local conductivity at the nanoscale. However, these probes have limitations: (i) long scans for larger inhomogeneities and (ii) temperature-driven phase transitions causing temperature drifts and difficult imaging comparisons.To address these, we developed a far-field optical microscopy setup to study VO2 phase transitions. This setup leverages optical contrast between insulating and metallic phases, observable from nanometers to microns. We applied different temperature protocols while continuously imaging, counteracting temperature drift and aligning sharp images. This enables single-pixel time traces to indicate specific phase transition temperatures.We first mapped critical temperature (Tc), transition width (ΔTc), and transition sharpness (δTc) in VO2. These maps could enable tailoring VO2 properties for specific applications like memory devices and fast switching components.We also presented the first optical imaging of ramp reversal memory (RRM) in VO2, showing cluster evolution during thermal subloop training. Memory accumulation occurs at cluster boundaries and within patches, suggesting preferential diffusion of point defects. This could enhance memory effects through defect engineering, improving memory devices' robustness and stability.Additionally, we pursued a machine learning (ML) analysis of fractal patterns in VO2, using ML to classify the Hamiltonian driving pattern formation. Our convolutional neural network (CNN) achieved high accuracy with synthetic and experimental data, confirming pattern formation driven by proximity to a critical point of the two-dimensional random field Ising model. This framework, combined with symmetry reduction and confidence quantification, offers a new powerful tool for analyzing complex phase transitions in correlated materials.Our research provides a new optical characterization method for understanding VO2 transition dynamics and introduces innovative approaches for optimizing VO2 for non-memory applications. These insights lay a foundation for future studies that explore RRM's potential, and extend ML frameworks to other correlated materials

Neurocomputers offer a massively parallel computing paradigm by mimicking the human brain. Their efficient use in statistical information processing has been proposed to overcome critical bottlenecks with traditional computing schemes for applications such as image and speech processing, and associative memory. In neural networks information is generally represented by phase (e.g., oscillatory neural networks) or amplitude (e.g., cellular neural networks). Phase-based neurocomputing is constructed as a network of coupled oscillatory neurons that are connected via programmable phase elements. Representing each neuron circuit with one oscillatory device and implementing programmable phases among neighboring neurons, however, are not clearly feasible from circuits perspective if not impossible. In contrast to nascent oscillatory neurocomputing circuits, mature amplitude-based neural networks offer more efficient circuit solutions using simpler resistive networks where information is carried via voltage- and current-mode signals. Yet, such circuits have not been efficiently realized by CMOS alone due to the needs for an efficient summing mechanism for weighted neural signals and a digitally-controlled weighting element for representing couplings among artificial neurons. Large power consumption and high circuit complexity of such CMOS-based implementations have precluded adoption of amplitude-based neurocomputing circuits as well, and have led researchers to explore the use of emerging technologies for such circuits. Although they provide intriguing properties, previously proposed neurocomputing components based on emerging technologies have not offered a complete and practical solution to efficiently construct an entire system. In this thesis we explore the generalized problem of co-optimization of technology and architecture for such systems, and develop a recipe for device requirements and target capabilities. We describe four plausible technologies, each of which could potentially enable the implementation of an efficient and fully-functional neurocomputing system. We first investigate fully-digital neural network architectures that have been tried before using CMOS technology in which many large-size logic gates such as D flip-flops and look-up tables are required. Using a newly-proposed all-magnetic non-volatile logic family, mLogic, we demonstrate the efficacy of digitizing the oscillators and phase relationships for an oscillatory neural network by exploiting the inherent storage as well as enabling an all-digital cellular neural network hardware with simplified programmability. We perform system-level comparisons of mLogic and 32nm CMOS for both networks consisting of 60 neurons. Although digital implementations based on mLogic offer improvements over CMOS in terms of power and area, analog neurocomputing architectures seem to be more compatible with the greatest portion of emerging technologies and devices. For this purpose in this dissertation we explore several emerging technologies with unique device configurations and features such as mCell devices, ovenized aluminum nitride resonators, and tunable multi-gate graphene devices to efficiently enable two key components required for such analog networks – that is, summing function and weighting with compact D/A (digital-to-analog) conversion capability. We demonstrate novel ways to implement these functions and elaborate on our building blocks for artificial neurons and synapses using each technology. We verify the functionality of each proposed implementation using various image processing applications based on compact circuit simulation models for such post-CMOS devices. Finally, we design a proof-of-concept neurocomputing circuitry containing 20 neurons using 65nm CMOS technology that is based on the primitives that we define for our analog neurocomputing scheme. This allows us to fully recognize the inefficiencies of an all-CMOS implementation for such specific applications. We share our experimental results that are in agreement with circuit simulations for the same image processing applications based on proposed architectures using emerging technologies. Power and area comparisons demonstrate significant improvements for analog neurocomputing circuits when implemented using beyond- CMOS technologies, thereby promising huge opportunities for future energy-efficient computing.

Unconventional computing paradigms are subject of increasing interest for the design and the development of computing systems that aim to overcome the limitations of standard digital technologies related to low power efficiency and intrinsic integration limits in the fabrication processes. Networks of nano-objects fabricated exploiting the self-assembling of their building blocks at the nanoscale, are promising physical substrate for the fabrication of neuromorphic devices thanks to their non-linear electrical properties and dynamic behavior in response to external applied voltage. Recently, cluster-assembled metallic films showed resistive switching properties under the application of an external electrical films and the possibility to fabricate multi-electrode device capable to implement information processing systems [9, 10]. Here I studied the non local and correlated electrical behaviour of multi-electrode cluster-assembeld gold films and I proposed a device that exploits the coduction porperties of these systems to implement efficient and autonomous data processing.

Present-day robots are, to some extent, able to deal with high complexity and variability of the real-world environment. Their cognitive capabilities can be further enhanced, if they physically interact and explore the real-world objects. For this, the need for efficient tactile sensors is growing day after day in such a way are becoming more and more part of daily life devices especially in robotic applications for manipulation and safe interaction with the environment. In this thesis, we highlight the importance of touch sensing in humans and robots. Inspired by the biological systems, in the the first part, we merge between neuromorphic engineering and CMOS technology where the former is a eld of science that replicates what is biologically (neurons of the nervous system) inside humans into the circuit level. We explain the operation and then characterize different sensor circuits through simulation and experiment to propose finally new prototypes based on the achieved results. In the second part, we present a machine learning technique for detecting the direction and orientation of a sliding tip over a complete skin patch of the iCub robot. Through learning and online testing, the algorithm classies different trajectories across the skin patch. Through this part, we show the results of the considered algorithm with a future perspective to extend the work.

Ce document présente la réalisation du premier système tactile de substitution sensorielle neuromorphique, en venant fusionner le domaine des neuroprothèses avec celui de la substitution sensorielle. L’évolution du dispositif jusqu’à sa version la plus aboutie est détaillée. Le système est testé au sein de deux études. La première permet d’étudier la discrimination spatiale et temporelle des sujets. Il rend possible l’évaluation de la capacité de discrimination de mouvement d’un point via le dispositif porté sur le dos. Dans la deuxième étude, le système tactile neuromorphique est couplé à une rétine artificielle. Une étude clinique permet d’étudier l’évolution d’un tel dispositif dans un environnement plus complexe via un apprentissage progressif et personnalisé. Cette étude permet également d’évaluer les retours des sujets vis à vis de l’ergonomie d’un tel système. Dix non-voyants acquis et cinq bien-voyants ont participé à cette étude. Les sujets sont capables grâce à ce dispositif de détecter des objets en mouvement, de discriminer l’espacement entre des formes, de trouver une cible dans une salle à luminosité variable, de suivre un chemin signalé au sol et d’éviter un potentiel obstacle. Enfin, ce dispositif a reçu un retour positif de la part des sujets nonvoyants, avec le souhait de voir le système devenir moins encombrant et plus discret pour permettre une utilisation quotidienne
This document presents the conception of the first neuromorphic tactile sensory substitution device, merging the domains of neuroprosthetics and sensory substitution.After a presentation of the state of art of the domains at the core of this work, we will introduce the device and present its chronological evolution and technical choices. We will then in a second stage introduce the validation studies that have been carried out to test the tactile neuromorphic device on blind and healthy control patients. The first study relies on psychophysical tests carried out to evaluate the link between spatial and temporal resolution of the developed device. The test relied on the ability of subjects to detect the direction of motion of a point sent on the tactile belt contacting the back of the subject. In the second study, the neuromorphic tactile system is coupled with an artificial silicon retina. A clinical trial is performed to study the performances of the developed device in a more complex environments using an incremental learning method. This study also evaluates the subjects’ feedback on the ergonomics of such an equipment. Ten visually impaired and five well-sighted subjects were selected. Subjects were able to detect objects in motion, discriminate the spacing between shapes, find a target in a scene with variable brightness, follow a signaled path on the ground and even avoid potential obstacles

La transformation de nos sociétés par le digital génère des quantités importantes de données dont la croissance a atteint une vitesse exponentielle depuis les dernières années. En dépit du progrès technique en matière de calcul, les ordinateurs digitaux actuels suivent difficilement cette tendance et sont dépassés par l'ampleur de certains problèmes, notamment liés aux algorithmes d'intelligence artificielle et aux problèmes d'optimisation de grande échelle. La limitation principale est liée à l'architecture même des calculateurs digitaux, à savoir la séparation du processeur et de la mémoire qui induit un ralentissement par le transfert des données, aussi appelée le goulot d'étranglement de von Neumann. Afin de contourner cette limitation, d'autres méthodes de calcul furent proposées distribuant le processeur et la mémoire telles que les architectures neuromorphiques basées sur l'implémentation de réseaux de neurones artificiels inspirés du cerveau. En outre, repenser la manière digitale de calculer comme par exemple utiliser les lois physiques et analogiques a le potentiel de réduire l'impact énergétique de certains calculs tout en les accélérant. Cette thèse a pour objectif principal d'explorer une approche physique du calcul fondée sur des réseaux de neurones oscillants (ONN) analogiques à faible coût énergétique. En particulier, ce travail se concentre sur (1) les performances d'une architecture ONN basée sur des neurones oscillants à partir de dioxyde de vanadium et couplés par des résistances, (2) une nouvelle architecture d'ONN à signaux mixtes calculant dans le domaine analogique, et propageant l'information de manière digitale afin de faciliter la conception à grande échelle, et (3) comment les ONNs peuvent résoudre des problèmes d'optimisation combinatoire dont la complexité croît de manière exponentielle avec la taille du problème. Pour conclure, de potentielles applications et futurs axes de recherche sont discutés
Digitalization of society creates important quantities of data that have been increasing at an exponential rate during the past few years. Despite the tremendous technological progress, digital computers have trouble meeting the demand, especially for challenging tasks involving artificial intelligence or optimization problems. The fundamental reason comes from the architecture of digital computers which separates the processor and memory and slows down computations due to undesired data transfers, the so-called von Neumann bottleneck. To avoid unnecessary data movement, various computing paradigms have been proposed that merge processor and memory such as neuromorphic architectures that take inspiration from the brain and physically implement artificial neural networks. Furthermore, rethinking digital operations and using analog physical laws to compute has the potential to accelerate some tasks at a low energy cost.This dissertation aims to explore an energy-efficient physical computing approach based on analog oscillatory neural networks (ONN). In particular, this dissertation unveils (1) the performances of ONN based on vanadium dioxide oscillating neurons with resistive synapses, (2) a novel mixed-signal and scalable ONN architecture that computes in the analog domain and propagates the information digitally, and (3) how ONNs can tackle combinatorial optimization problems whose complexity scale exponentially with the problem size. The dissertation concludes with discussions of some promising future research directions

Neuromorphic engineering is the research field dedicated to the study and design of brain-inspired hardware and software tools. Recent advances in emerging nanoelectronics promote the implementation of synaptic connections based on memristive devices. Their non-volatile modifiable conductance was shown to exhibit the synaptic properties often used in connecting and training neural layers. With their nanoscale size and non-volatile memory property, they promise a next step in designing more area and energy efficient neuromorphic hardware. My research deals with the challenges of harnessing memristive device properties that go beyond the behaviors utilized for synaptic weight storage. Based on devices that exhibit non-linear state changes and volatility, I present novel architectures and algorithms that can harness such features for computation. The crossbar architecture is a dense array of memristive devices placed in-between horizontal and vertical nanowires. The regularity of this structure does not inherently provide the means for nonlinear computation of applied input signals. Introducing a modulation scheme that relies on nonlinear memristive device properties, heterogeneous state patterns of applied spatiotemporal input data can be created within the crossbar. In this setup, the untrained and dynamically changing states of the memristive devices offer a useful platform for information processing. Based on the MNIST data set I'll demonstrate how the temporal aspect of memristive state volatility can be utilized to reduce system size and training complexity for high dimensional input data. With 3 times less neurons and 15 times less synapses to train as compared to other memristor-based implementations, I achieve comparable classification rates of up to 93%. Exploiting dynamic state changes rather than precisely tuned stable states, this approach can tolerate device variation up to 6 times higher than reported levels. Random assemblies of memristive networks are analyzed as a substrate for intrinsic computation in connection with reservoir computing; a computational framework that harnesses observations of inherent dynamics within complex networks. Architectural and device level considerations lead to new levels of task complexity, which random memristive networks are now able to solve. A hierarchical design composed of independent random networks benefits from a diverse set of topologies and achieves prediction errors (NRMSE) on the time-series prediction task NARMA-10 as low as 0.15 as compared to 0.35 for an echo state network. Physically plausible network modeling is performed to investigate the relationship between network dynamics and energy consumption. Generally, increased network activity comes at the cost of exponentially increasing energy consumption due to nonlinear voltage-current characteristics of memristive devices. A trade-off, that allows linear scaling of energy consumption, is provided by the hierarchical approach. Rather than designing individual memristive networks with high switching activity, a collection of less dynamic, but independent networks can provide more diverse network activity per unit of energy. My research extends the possibilities of including emerging nanoelectronics into neuromorphic hardware. It establishes memristive devices beyond storage and motivates future research to further embrace memristive device properties that can be linked to different synaptic functions. Pursuing to exploit the functional diversity of memristive devices will lead to novel architectures and algorithms that study rather than dictate the behavior of such devices, with the benefit of creating robust and efficient neuromorphic hardware.

Les technologies neuromorphiques constituent une voie prometteuse pour le développement d'une informatique plus avancée et plus économe en énergie. Elles visent à reproduire les caractéristiques attrayantes du cerveau, telles qu'une grande efficacité de calcul et une faible consommation d'énergie au niveau des logiciels et du matériel. À l'heure actuelle, les implémentations logicielles inspirées du cerveau (telles que ANN et SNN) ont déjà démontré leur efficacité dans différents types de tâches (reconnaissance d'images et de la parole). Toutefois, pour tirer un meilleur parti des algorithmes inspirés du cerveau, il est possible de les combiner avec une implémentation materielle appropriée qui s'appuierait également sur une architecture et des processus inspirés du cerveau. L'ingénierie neuromorphique s'est principalement appuyée sur les technologies conventionnelles (CMOS circuits, memristor) pour le développement de circuits inspirés du cerveau. Néanmoins, ces implémentations sont fabriquées suivant une approche top-down. En revanche, l'informatique cérébrale repose sur des processus bottom-up tels que l'interconnectivité entre les cellules et la formation de voies de communication neuronales.À la lumière de ce qui précède, ce travail de thèse porte sur le développement de dispositifs neuromorphiques organiques programmables en 3D qui, contrairement à la plupart des technologies neuromorphiques actuelles, peuvent être créés de manière bottom-up. Cela permet de rapprocher les technologies neuromorphiques du niveau de programmation du cerveau, où les chemins neuronaux nécessaires sont établis uniquement en fonction des besoins.Tout d'abord, nous avons découvert que les interconnexions 3D à base de PEDOT:PSS peuvent être formées au moyen d'électropolymérisation bipolaire en courant alternatif, permettant d'imiter la croissance des cellules neuronales. En réglant individuellement les paramètres de la forme d'onde (tension d'amplitude de crête - VP, fréquence - f, duty cycle- dc et tension de décalage - Voff), une large gamme de structures semblables à des dendrites a été observée avec différents degrés de ramification, volumes, surfaces, asymétries et dynamiques de croissance.Ensuite, nous avons montré que les morphologies dendritiques obtenues à différentes fréquences sont conductrices. De plus, chaque structure présente une valeur de conductance qui peut être interprétée comme un poids synaptique. Plus important encore, la capacité des dendrites à fonctionner comme OECT a été révélée. Différentes morphologies de dendrites ont présenté des performances différentes en tant qu'OECT. De plus, la capacité des dendrites en PEDOT:PSS à modifier leur conductivité en réponse à la tension de grille a été utilisée pour imiter les fonctions de mémoire du cerveau (plasticité à court terme -STP et plasticité à long terme -LTP). Les réponses à la STP varient en fonction de la structure dendritique. En outre, l'émulation de la LTP a été démontrée non seulement au moyen d'un fil de grille Ag/AgCl, mais aussi au moyen d'une grille dendritique en polymère développée par électropolymérisation.Enfin, la plasticité structurelle a été démontrée par la croissance dendritique, où le poids de la connexion finale est régi par les règles d'apprentissage de type Hebbien (plasticité dépendante du moment de l'impulsion - STDP et plasticité dépendante du rythme de l'impulsion - SRDP). En utilisant les deux approches, une variété de topologies dendritiques avec des états de conductance programmables (c'est-à-dire le poids synaptique) et diverses dynamiques de croissance ont été observées. Finalement, en utilisant la même plasticité structurelle dendritique, des caractéristiques cérébrales plus complexes telles que l'apprentissage associatif et les tâches de classification ont été émulées.En outre, les perspectives futures de ces technologies basées sur des objets dendritiques polymères ont été discutées
Neuromorphic technologies is a promising direction for development of more advanced and energy-efficient computing. They aim to replicate attractive brain features such as high computational efficiency at low power consumption on a software and hardware level. At the moment, brain-inspired software implementations (such as ANN and SNN) have already shown their successful application for different types of tasks (image and speech recognition). However, to benefit more from the brain-like algorithms, one may combine them with appropriate hardware that would also rely on brain-like architecture and processes and thus complement them. Neuromorphic engineering has already shown the utilization of solid-state electronics (CMOS circuits, memristor) for the development of brain-inspired devices. Nevertheless, these implementations are fabricated through top-down methods. In contrast, brain computing relies on bottom-up processes such as interconnectivity between cells and the formation of neural communication pathways.In the light of mentioned above, this work reports on the development of programmable 3D organic neuromorphic devices, which, unlike most current neuromorphic technologies, can be created in a bottom-up manner. This allows bringing neuromorphic technologies closer to the level of brain programming, where necessary neural paths are established only on the need.First, we found out that PEDOT:PSS based 3D interconnections can be formed by means of AC-bipolar electropolymerization and that they are capable of mimicking the growth of neural cells. By tuning individually the parameters of the waveform (peak amplitude voltage -VP, frequency - f, duty cycle - dc and offset voltage - Voff), a wide range of dendrite-like structures was observed with various branching degrees, volumes, surface areas, asymmetry of formation, and even growth dynamics.Next, it was discovered that dendritic morphologies obtained at various frequencies are conductive. Moreover, each structure exhibits an individual conductance value that can be interpreted as synaptic weight. More importantly, the ability of dendrites to function as OECT was revealed. Different dendrites exhibited different performances as OECT. Further, the ability of PEDOT:PSS dendrites to change their conductivity in response to gate voltage was used to mimic brain memory functions (short-term plasticity -STP and long-term plasticity -LTP). STP responses varied depending on the dendritic structure. Moreover, emulation of LTP was demonstrated not only by means of an Ag/AgCl gate wire but as well by means of a self-developed polymer dendritic gate.Finally, structural plasticity was demonstrated through dendritic growth, where the weight of the final connection is governed according to Hebbian learning rules (spike-timing-dependent plasticity - STDP and spike-rate-dependent plasticity - SRDP). Using both approaches, a variety of dendritic topologies with programmable conductance states (i.e., synaptic weight) and various dynamics of growth have been observed. Eventually, using the same dendritic structural plasticity, more complex brain features such as associative learning and classification tasks were emulated.Additionally, future perspectives of such technologies based on self-propagating polymer dendritic objects were discussed

En utilisant les méthodes d’apprentissages tirées des récentes découvertes en neuroscience, les réseaux de neurones impulsionnels ont démontrés leurs capacités à analyser efficacement les grandes quantités d’informations provenant de notre environnement. L’implémentation de ces circuits à l’aide de processeurs classiques ne permet pas d’exploiter efficacement leur parallélisme. L’utilisation de mémoire numérique pour implémenter les poids synaptique ne permet pas la lecture ou la programmation parallèle des synapses et est limité par la bande passante reliant la mémoire à l’unité de calcul. Les technologies mémoire de type memristive pourrait permettre l’implémentation de ce parallélisme au coeur de la mémoire.Dans cette thèse, nous envisageons le développement d’un réseau de neurones impulsionnels dédié au monde de l’embarqué à base de dispositif mémoire émergents. Dans un premier temps, nous avons analysé un réseau impulsionnel afin d’optimiser ses différentes composantes : neurone, synapse et méthode d’apprentissage STDP en vue d’une implémentation numérique. Dans un second temps, nous envisageons l’implémentation de la mémoire synaptique par des dispositifs memristifs. Enfin, nous présentons le développement d’une puce co-intégrant des neurones implémentés en CMOS avec des synapses en technologie CBRAM
By using learning mechanisms extracted from recent discoveries in neuroscience, spiking neural networks have demonstrated their ability to efficiently analyze the large amount of data from our environment. The implementation of such circuits on conventional processors does not allow the efficient exploitation of their parallelism. The use of digital memory to implement the synaptic weight does not allow the parallel reading or the parallel programming of the synapses and it is limited by the bandwidth of the connection between the memory and the processing unit. Emergent memristive memory technologies could allow implementing this parallelism directly in the heart of the memory.In this thesis, we consider the development of an embedded spiking neural network based on emerging memory devices. First, we analyze a spiking network to optimize its different components: the neuron, the synapse and the STDP learning mechanism for digital implementation. Then, we consider implementing the synaptic memory with emergent memristive devices. Finally, we present the development of a neuromorphic chip co-integrating CMOS neurons with CBRAM synapses

Dans cette thèse, nous étudions les applications potentielles des nano-dispositifs mémoires émergents dans les architectures de calcul. Nous montrons que des architectures neuro-inspirées pourraient apporter l'efficacité et l'adaptabilité nécessaires à des applications de traitement et de classification complexes pour la perception visuelle et sonore. Cela, à un cout moindre en termes de consommation énergétique et de surface silicium que les architectures de type Von Neumann, grâce à une utilisation synaptique de ces nano-dispositifs. Ces travaux se focalisent sur les dispositifs dit "memristifs", récemment (ré)-introduits avec la découverte du memristor en 2008 et leur utilisation comme synapse dans des réseaux de neurones impulsionnels. Cela concerne la plupart des technologies mémoire émergentes : mémoire à changement de phase - "Phase-Change Memory" (PCM), "Conductive-Bridging RAM" (CBRAM), mémoire résistive - "Resistive RAM" (RRAM)... Ces dispositifs sont bien adaptés pour l'implémentation d'algorithmes d'apprentissage non supervisés issus des neurosciences, comme "Spike-Timing-Dependent Plasticity" (STDP), ne nécessitant que peu de circuit de contrôle. L'intégration de dispositifs memristifs dans des matrices, ou "crossbar", pourrait en outre permettre d'atteindre l'énorme densité d'intégration nécessaire pour ce type d'implémentation (plusieurs milliers de synapses par neurone), qui reste hors de portée d'une technologie purement en "Complementary Metal Oxide Semiconductor" (CMOS). C'est l'une des raisons majeures pour lesquelles les réseaux de neurones basés sur la technologie CMOS n'ont pas eu le succès escompté dans les années 1990. A cela s'ajoute la relative complexité et inefficacité de l'algorithme d'apprentissage de rétro-propagation du gradient, et ce malgré tous les aspects prometteurs des architectures neuro-inspirées, tels que l'adaptabilité et la tolérance aux fautes. Dans ces travaux, nous proposons des modèles synaptiques de dispositifs memristifs et des méthodologies de simulation pour des architectures les exploitant. Des architectures neuro-inspirées de nouvelle génération sont introduites et simulées pour le traitement de données naturelles. Celles-ci tirent profit des caractéristiques synaptiques des nano-dispositifs memristifs, combinées avec les dernières avancées dans les neurosciences. Nous proposons enfin des implémentations matérielles adaptées pour plusieurs types de dispositifs. Nous évaluons leur potentiel en termes d'intégration, d'efficacité énergétique et également leur tolérance à la variabilité et aux défauts inhérents à l'échelle nano-métrique de ces dispositifs. Ce dernier point est d'une importance capitale, puisqu'il constitue aujourd'hui encore la principale difficulté pour l'intégration de ces technologies émergentes dans des mémoires numériques.

abstract: A workload-aware low-power neuromorphic controller for dynamic power and thermal management in VLSI systems is presented. The neuromorphic controller predicts future workload and temperature values based on the past values and CPU performance counters and preemptively regulates supply voltage and frequency. System-level measurements from stateof-the-art commercial microprocessors are used to get workload, temperature and CPU performance counter values. The controller is designed and simulated using circuit-design and synthesis tools. At device-level, on-chip planar inductors suffer from low inductance occupying large chip area. On-chip inductors with integrated magnetic materials are designed, simulated and fabricated to explore performance-efficiency trade offs and explore potential applications such as resonant clocking and on-chip voltage regulation. A system level study is conducted to evaluate the effect of on-chip voltage regulator employing magnetic inductors as the output filter. It is concluded that neuromorphic power controller is beneficial for fine-grained per-core power management in conjunction with on-chip voltage regulators utilizing scaled magnetic inductors.
Dissertation/Thesis
Ph.D. Electrical Engineering 2011

A memristor, memory resistor, is a two-terminal nanodevice that can be made as thin as a single-atom-thick that has become of tremendous interest for its potential to revolutionise electronics, computing, computer architectures, and neuromorphic engineering. This thesis encompasses two major parts containing original contributions, (Part I) modelling and fabrication, and (Part II) circuit application and computing. Each part contains three chapters. The fundamentals necessary for understanding the main idea of each chapter are provided therein. A background chapter revolving around memristors and memristive devices is given. A system overview links the two parts together. A brief description of the two parts is as follows: Part I—modelling and fabrication is relevant to modelling and fabrication of memristors. A basic modelling approach following the early modelling by Hewlett- Packard is presented and tested with several simple circuits. Memristor fabrication process and materials are discussed and two different fabrication runs along with initial measurement results are presented. SPICE modelling for two memristive devices, (i) the memristor and (ii) the complementary resistive switch are also provided. Part II—nanocrossbar array and memristive-based memory and computing provides an analytical approach for crossbar arrays based on memristive devices. Proposed designs for memristor-based content addressable memories and their analysis are given. This part provides a binary/ternary content addressable memory structure based on a new complementary resistive switch. A number of fundamental building blocks for analogue and digital computing are also presented in this section. The observation of implementing a learning process based on a pair of spikes is also shown and an extension of such a process to a relatively large scale structure based on SPICE simulation is reported. In addition to these original contributions, the thesis offers an introductory background on memristors, in the area of materials and applications. The thesis also provides a system overview of the targeted system (a CMOS-memristor imager system), which provides a the link between the two parts of the thesis. In addition to the original contributions in the area of modelling and characterisation, an overview on the understanding of the memristor element via the quasistatic expansion of Maxwell’s equations is discussed.
Thesis (Ph.D.) -- University of Adelaide, School of Electrical and Electronic Engineering, 2012.

abstract: Over the past few decades, the silicon complementary-metal-oxide-semiconductor (CMOS) technology has been greatly scaled down to achieve higher performance, density and lower power consumption. As the device dimension is approaching its fundamental physical limit, there is an increasing demand for exploration of emerging devices with distinct operating principles from conventional CMOS. In recent years, many efforts have been devoted in the research of next-generation emerging non-volatile memory (eNVM) technologies, such as resistive random access memory (RRAM) and phase change memory (PCM), to replace conventional digital memories (e.g. SRAM) for implementation of synapses in large-scale neuromorphic computing systems. Essentially being compact and “analog”, these eNVM devices in a crossbar array can compute vector-matrix multiplication in parallel, significantly speeding up the machine/deep learning algorithms. However, non-ideal eNVM device and array properties may hamper the learning accuracy. To quantify their impact, the sparse coding algorithm was used as a starting point, where the strategies to remedy the accuracy loss were proposed, and the circuit-level design trade-offs were also analyzed. At architecture level, the parallel “pseudo-crossbar” array to prevent the write disturbance issue was presented. The peripheral circuits to support various parallel array architectures were also designed. One key component is the read circuit that employs the principle of integrate-and-fire neuron model to convert the analog column current to digital output. However, the read circuit is not area-efficient, which was proposed to be replaced with a compact two-terminal oscillation neuron device that exhibits metal-insulator-transition phenomenon. To facilitate the design exploration, a circuit-level macro simulator “NeuroSim” was developed in C++ to estimate the area, latency, energy and leakage power of various neuromorphic architectures. NeuroSim provides a wide variety of design options at the circuit/device level. NeuroSim can be used alone or as a supporting module to provide circuit-level performance estimation in neural network algorithms. A 2-layer multilayer perceptron (MLP) simulator with integration of NeuroSim was demonstrated to evaluate both the learning accuracy and circuit-level performance metrics for the online learning and offline classification, as well as to study the impact of eNVM reliability issues such as data retention and write endurance on the learning performance.
Dissertation/Thesis
Doctoral Dissertation Electrical Engineering 2018

With the Moore’s Law era coming to an end, much attention has been given to novel nanoelectronic devices as a key driving force behind technological innovation. Utilizing the inherent device physics of nanoelectronic components, for sensory and computational tasks have proven to be useful in reducing the area and energy requirements of the underlying hardware fabrics. In this work we demonstrate how the intrinsic noise present in nano magnetic devices can pave the pathway for energy efficient neuromorphic hardware. Furthermore, we illustrate how the unique magnetic properties of such devices can be leveraged for accurate estimation of environmental magnetic fields. We focus on spintronic technologies in particular, due to the low current and energy requirements in contrast to traditional CMOS technologies.

Image segmentation is a crucial pre-processing stage used in many object identification tasks that involves simplifying the representation of an image so it can be conveniently analyzed in the later stages of a problem. This is achieved through partitioning a complicated image into specific groups based on color, intensity or texture of the pixels of that image. Locally Excitatory Globally Inhibitory Oscillator Network or LEGION is one such segmentation algorithm, where synchronization and desynchronization between coupled oscillators are used for segmenting an image. In this work we present an energy efficient and scalable hardware implementation of LEGION using stochastic Magnetic Tunnel Junctions that leverage the fast parallel

nature of the algorithm. We demonstrate that the proposed hardware is capable of segmenting binary and gray-scale images with multiple objects more efficiently than
existing hardware implementations.

It is understood that the underlying device physics of spin devices can be used for emulating the functionality of a spiking neuron. Stochastic spiking neural networks based on nanoelectronic spin devices can be a possible pathway of achieving brain-like compact and energy-efficient cognitive intelligence. Current computational models attempt to exploit the intrinsic device stochasticity of nanoelectronic synaptic or neural components to perform learning and inference. However, there has been limited analysis on the scaling effect of stochastic spin devices and its impact on the operation of such stochastic networks at the system level. Our work attempts to explore the design space and analyze the performance of nanomagnet based stochastic neuromorphic computing architectures, for magnets with different barrier heights. We illustrate how the underlying network architecture must be modified to account for the random telegraphic switching behavior displayed by magnets as they are scaled into the superparamagnetic regime.

Next we investigate how the magnetic properties of spin devices can be utilized for real world sensory applications. Magnetic Tunnel Junctions can efficiently translate variations in external magnetic fields into variations in electrical resistance. We couple this property of Magnetic Tunnel Junctions with Amperes law to design a non-invasive sensor to measure the current flowing through a wire. We demonstrate how undesirable effects of thermal noise and process variations can be suppressed through novel analog and digital signal conditioning techniques to obtain reliable and accurate current measurements. Our results substantiate that the proposed noninvasive current sensor surpass other state-of-the-art technologies in terms of noise and accuracy.

碩士
國立交通大學
電子研究所
108
In this thesis, we characterize the negative voltage read induced conductance change in a hafnium oxide RRAM synapse. An analytical model is developed to describe the conductance evolution with the number of read cycles. The proposed model includes the impact of read voltage and initial conductance level on conductance state stability. We found that the current degradation induced by read pulses is determined by cumulative read time, rather than the duration of a single read pulse. A two-stage featured conductance evolution is observed. The conductance reduction reveals an inverse power-law dependence on cumulative read number in the second stage. We discover that the measured power factor is dependent on read voltages. On the other hand, the measured transition read number between the two stages is affected by both read voltages and initial conductance levels. To describe the conductance evolution, we present an analytical model to simulate the transition read number at different read voltages and initial conductance levels. The proposed model is in great consistency with measurement results. Our model is not only capable of describing the conductance evolution in a wide range of read cycle numbers but also provides physical insights to read-induced conductance changes in RRAM synapses.

Novel computational paradigms based on non-von Neumann architectures are being extensively explored for modern data-intensive applications and big-data problems. One direction in this context is to harness the intrinsic physics of spintronics devices for the implementation of nanoscale and low-power building blocks of such emerging computational systems. For example, a Probabilistic Spin Logic (PSL) that consists of networks of p-bits has been proposed for neuromorphic computing, Bayesian networks, and for solving optimization problems. In my work, I will discuss two types of device-components required for PSL: (i) p-bits mimicking binary stochastic neurons (BSN) and (ii) compound synapses for implementing weighted interconnects between p-bits. Furthermore, I will also show how the integration of recently discovered van der Waals ferromagnets in spintronics devices can reduce the current densities required by orders of magnitude, paving the way for future low-power spintronics devices.

First, a spin-device with input-output isolation and stable magnets capable of generating tunable random numbers, similar to a BSN, was demonstrated. In this device, spin-orbit torque pulses are used to initialize a nano-magnet with perpendicular magnetic anisotropy (PMA) along its hard axis. After removal of each pulse, the nano-magnet can relax back to either of its two stable states, generating a stream of binary random numbers. By applying a small Oersted field using the input terminal of the device, the probability of obtaining 0 or 1 in binary random numbers (P) can be tuned electrically. Furthermore, our work shows that in the case when two stochastic devices are connected in series, “P” of the second device is a function of “P” of the first p-bit and the weight of the interconnection between them. Such control over correlated probabilities of stochastic devices using interconnecting weights is the working principle of PSL.

Next my work focused on compact and energy efficient implementations of p-bits and interconnecting weights using modified spin-devices. It was shown that unstable in-plane magnetic tunneling junctions (MTJs), i.e. MTJs with a low energy barrier, naturally fluctuate between two states (parallel and anti-parallel) without any external excitation, in this way generating binary random numbers. Furthermore, spin-orbit torque of tantalum is used to control the time spent by the in-plane MTJ in either of its two states i.e. “P” of the device. In this device, the READ and WRITE paths are separated since the MTJ state is read by passing a current through the MTJ (READ path) while “P” is controlled by passing a current through the tantalum bar (WRITE path). Hence, a BSN/p-bit is implemented without energy-consuming hard axis initialization of the magnet and Oersted fields. Next, probabilistic switching of stable magnets was utilized to implement a novel compound synapse, which can be used for weighted interconnects between p-bits. In this experiment, an ensemble of nano-magnets was subjected to spin-orbit torque pulses such that each nano-magnet has a finite probability of switching. Hence, when a series of pulses are applied, the total magnetization of the ensemble gradually increases with the number of pulses

applied similar to the potentiation and depression curves of synapses. Furthermore, it was shown that a modified pulse scheme can improve the linearity of the synaptic behavior, which is desired for neuromorphic computing. By implementing both neuronal and synaptic devices using simple nano-magnets, we have shown that PSL can be realized using a modified Magnetic Random Access Memory (MRAM) technology. Note that MRAM technology exists in many current foundries.

To further reduce the current densities required for spin-torque devices, we have fabricated heterostructures consisting of a 2-dimensional semiconducting ferromagnet (Cr₂Ge₂Te₆) and a metal with spin-orbit coupling metal (tantalum). Because of properties such as clean interfaces, perfect crystalline nanomagnet structure and sustained magnetic moments down to the mono-layer limit and low current shunting, 2D ferromagnets require orders of magnitude lower current densities for spin-orbit torque switching than conventional metallic ferromagnets such as CoFeB.

碩士
國立交通大學
電子研究所
107
Neuromorphic computing is expected to emulate brain functions in the near future. There are several nonvolatile memory such as PCRAM, CBRAM, RRAM have been proposed as synaptic memory device. All of above, RRAM is the most promising candidate, due to its several advantages, low power consumption, simple structure, excellent endurance, high operation speed. However, the desirable characteristic of synaptic device is different from traditional RRAM. It requires analog switching behavior and multi-level conductance states, which are beneficial to learning accuracy. In this thesis, the bipolar resistive switching behavior and synaptic characteristics are investigated in TiOx-based synaptic memory device. There are three parts in this thesis. First, different thickness TiOx film are deposited in TiN/Ti/TiOx/TiN structure. The relationship between thickness and electrical characteristics is discussed. The thickness of the TiOx switching layer determine the working operation current of the devices. The thicker layer device can work at lower compliance current and make smaller conductive filament. In addition, the influence of different pulse amplitudes applied on potentiation and depression is investigated. When lower pulse amplitude was applied on the device, conductance can gradually change and the nonlinearity is better. However, dynamic range become small and noise increase. The second part is that different Ti thickness effect on TiOx-based synaptic device. We compare their electrical characteristics and synaptic characteristics. We observed that the analog behavior can be improved after inserting a thin Ti layer. Different thickness of Ti layer make different thickness of interfacial layer, which leads the TiOx- based memory device has different capability to form and rupture the filament. As a result, they perform different electrical characteristics and weight update behavior. The other part is that comparing ZrOx/TiOx synaptic device and TiOx synaptic device. The ZrOx/TiOx synaptic device shows more stable analog switching and the nonlinearity of potentiation and depression can be improved to 2.08 and 1.84. Furthermore, it exhibits good endurance and data retention properties.It demonstrates good performance not only for data storage application but also for mimicking biological synapse.

Today, there is an ever-growing demand for compact, and energy autonomous, implantable biomedical sensors. These devices, which continuously collect in vivo physiological data, are imperative in the next generation patient monitoring systems. One of the fundamental challenges in their implementation, besides the obvious size constraints and the tissue-to-electronics biocompatibility impediments, is the efficient means to wirelessly deliver power to them. This work addresses this challenge by demonstrating an energy-autonomous and fully-integrated implantable sensor chip which takes advantage of the existing on-chip photodiodes of a standard CMOS process as photovoltaic (PV) energy-harvesting cells. This 2.5 mm × 2.5 mm chip is capable of harvesting [mu]W’s of power from the ambient light passing through the tissue and performing real-time sensing. This system is also MRI compatible as it includes no magnetic material and requires no RF coil or antennae. In this dissertation, the optical properties of tissue and the capabilities of the CMOS integrated PV cells are studied first. Next, the implementation of an implantable sensor using such PV devices is discussed. The sensor characterizing and the in vitro measurement results using this system, demonstrate the feasibility of monolithically integrated CMOS PV-driven implantable sensors. In addition, they offer an alternative method to create low-cost and mass-deployable energy autonomous ICs in biomedical applications and beyond.
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