Artigos de revistas sobre o tema "Neural network accelerator"
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Eliahu, Adi, Ronny Ronen, Pierre-Emmanuel Gaillardon e Shahar Kvatinsky. "multiPULPly". ACM Journal on Emerging Technologies in Computing Systems 17, n.º 2 (abril de 2021): 1–27. http://dx.doi.org/10.1145/3432815.
Texto completo da fonteCho, Jaechan, Yongchul Jung, Seongjoo Lee e Yunho Jung. "Reconfigurable Binary Neural Network Accelerator with Adaptive Parallelism Scheme". Electronics 10, n.º 3 (20 de janeiro de 2021): 230. http://dx.doi.org/10.3390/electronics10030230.
Texto completo da fonteNoskova, E. S., I. E. Zakharov, Y. N. Shkandybin e S. G. Rykovanov. "Towards energy-efficient neural network calculations". Computer Optics 46, n.º 1 (fevereiro de 2022): 160–66. http://dx.doi.org/10.18287/2412-6179-co-914.
Texto completo da fonteHong, JiUn, Saad Arslan, TaeGeon Lee e HyungWon Kim. "Design of Power-Efficient Training Accelerator for Convolution Neural Networks". Electronics 10, n.º 7 (26 de março de 2021): 787. http://dx.doi.org/10.3390/electronics10070787.
Texto completo da fonteFerianc, Martin, Hongxiang Fan, Divyansh Manocha, Hongyu Zhou, Shuanglong Liu, Xinyu Niu e Wayne Luk. "Improving Performance Estimation for Design Space Exploration for Convolutional Neural Network Accelerators". Electronics 10, n.º 4 (23 de fevereiro de 2021): 520. http://dx.doi.org/10.3390/electronics10040520.
Texto completo da fonteSunny, Febin P., Asif Mirza, Mahdi Nikdast e Sudeep Pasricha. "ROBIN: A Robust Optical Binary Neural Network Accelerator". ACM Transactions on Embedded Computing Systems 20, n.º 5s (31 de outubro de 2021): 1–24. http://dx.doi.org/10.1145/3476988.
Texto completo da fonteAnmin, Kong, e Zhao Bin. "A Parallel Loading Based Accelerator for Convolution Neural Network". International Journal of Machine Learning and Computing 10, n.º 5 (5 de outubro de 2020): 669–74. http://dx.doi.org/10.18178/ijmlc.2020.10.5.989.
Texto completo da fonteXia, Chengpeng, Yawen Chen, Haibo Zhang, Hao Zhang, Fei Dai e Jigang Wu. "Efficient neural network accelerators with optical computing and communication". Computer Science and Information Systems, n.º 00 (2022): 66. http://dx.doi.org/10.2298/csis220131066x.
Texto completo da fonteTang, Wenkai, e Peiyong Zhang. "GPGCN: A General-Purpose Graph Convolution Neural Network Accelerator Based on RISC-V ISA Extension". Electronics 11, n.º 22 (21 de novembro de 2022): 3833. http://dx.doi.org/10.3390/electronics11223833.
Texto completo da fonteAn, Fubang, Lingli Wang e Xuegong Zhou. "A High Performance Reconfigurable Hardware Architecture for Lightweight Convolutional Neural Network". Electronics 12, n.º 13 (27 de junho de 2023): 2847. http://dx.doi.org/10.3390/electronics12132847.
Texto completo da fonteBiookaghazadeh, Saman, Pravin Kumar Ravi e Ming Zhao. "Toward Multi-FPGA Acceleration of the Neural Networks". ACM Journal on Emerging Technologies in Computing Systems 17, n.º 2 (abril de 2021): 1–23. http://dx.doi.org/10.1145/3432816.
Texto completo da fonteGe, Fen, Ning Wu, Hao Xiao, Yuanyuan Zhang e Fang Zhou. "Compact Convolutional Neural Network Accelerator for IoT Endpoint SoC". Electronics 8, n.º 5 (5 de maio de 2019): 497. http://dx.doi.org/10.3390/electronics8050497.
Texto completo da fonteClements, Joseph, e Yingjie Lao. "DeepHardMark: Towards Watermarking Neural Network Hardware". Proceedings of the AAAI Conference on Artificial Intelligence 36, n.º 4 (28 de junho de 2022): 4450–58. http://dx.doi.org/10.1609/aaai.v36i4.20367.
Texto completo da fonteXia, Chengpeng, Yawen Chen, Haibo Zhang e Jigang Wu. "STADIA: Photonic Stochastic Gradient Descent for Neural Network Accelerators". ACM Transactions on Embedded Computing Systems 22, n.º 5s (9 de setembro de 2023): 1–23. http://dx.doi.org/10.1145/3607920.
Texto completo da fonteWei, Rongshan, Chenjia Li, Chuandong Chen, Guangyu Sun e Minghua He. "Memory Access Optimization of a Neural Network Accelerator Based on Memory Controller". Electronics 10, n.º 4 (10 de fevereiro de 2021): 438. http://dx.doi.org/10.3390/electronics10040438.
Texto completo da fonteHu, Jian, Xianlong Zhang e Xiaohua Shi. "Simulating Neural Network Processors". Wireless Communications and Mobile Computing 2022 (23 de fevereiro de 2022): 1–12. http://dx.doi.org/10.1155/2022/7500195.
Texto completo da fonteChen, Weijian, Zhi Qi, Zahid Akhtar e Kamran Siddique. "Resistive-RAM-Based In-Memory Computing for Neural Network: A Review". Electronics 11, n.º 22 (9 de novembro de 2022): 3667. http://dx.doi.org/10.3390/electronics11223667.
Texto completo da fonteLim, Se-Min, e Sang-Woo Jun. "MobileNets Can Be Lossily Compressed: Neural Network Compression for Embedded Accelerators". Electronics 11, n.º 6 (9 de março de 2022): 858. http://dx.doi.org/10.3390/electronics11060858.
Texto completo da fonteAfifi, Salma, Febin Sunny, Amin Shafiee, Mahdi Nikdast e Sudeep Pasricha. "GHOST: A Graph Neural Network Accelerator using Silicon Photonics". ACM Transactions on Embedded Computing Systems 22, n.º 5s (9 de setembro de 2023): 1–25. http://dx.doi.org/10.1145/3609097.
Texto completo da fonteLi, Yihang. "Sparse-Aware Deep Learning Accelerator". Highlights in Science, Engineering and Technology 39 (1 de abril de 2023): 305–10. http://dx.doi.org/10.54097/hset.v39i.6544.
Texto completo da fonteXie, Xiaoru, Mingyu Zhu, Siyuan Lu e Zhongfeng Wang. "Efficient Layer-Wise N:M Sparse CNN Accelerator with Flexible SPEC: Sparse Processing Element Clusters". Micromachines 14, n.º 3 (24 de fevereiro de 2023): 528. http://dx.doi.org/10.3390/mi14030528.
Texto completo da fonteYang, Zhi. "Dynamic Logo Design System of Network Media Art Based on Convolutional Neural Network". Mobile Information Systems 2022 (31 de maio de 2022): 1–10. http://dx.doi.org/10.1155/2022/3247229.
Texto completo da fonteHosseini, Morteza, e Tinoosh Mohsenin. "Binary Precision Neural Network Manycore Accelerator". ACM Journal on Emerging Technologies in Computing Systems 17, n.º 2 (abril de 2021): 1–27. http://dx.doi.org/10.1145/3423136.
Texto completo da fontePark, Sang-Soo, e Ki-Seok Chung. "CENNA: Cost-Effective Neural Network Accelerator". Electronics 9, n.º 1 (10 de janeiro de 2020): 134. http://dx.doi.org/10.3390/electronics9010134.
Texto completo da fonteKim, Dongyoung, Junwhan Ahn e Sungjoo Yoo. "ZeNA: Zero-Aware Neural Network Accelerator". IEEE Design & Test 35, n.º 1 (fevereiro de 2018): 39–46. http://dx.doi.org/10.1109/mdat.2017.2741463.
Texto completo da fonteChen, Tianshi, Zidong Du, Ninghui Sun, Jia Wang, Chengyong Wu, Yunji Chen e Olivier Temam. "A High-Throughput Neural Network Accelerator". IEEE Micro 35, n.º 3 (maio de 2015): 24–32. http://dx.doi.org/10.1109/mm.2015.41.
Texto completo da fonteTo, Chun-Hao, Eduardo Rozo, Elisabeth Krause, Hao-Yi Wu, Risa H. Wechsler e Andrés N. Salcedo. "LINNA: Likelihood Inference Neural Network Accelerator". Journal of Cosmology and Astroparticle Physics 2023, n.º 01 (1 de janeiro de 2023): 016. http://dx.doi.org/10.1088/1475-7516/2023/01/016.
Texto completo da fonteLiang, Yong, Junwen Tan, Zhisong Xie, Zetao Chen, Daoqian Lin e Zhenhao Yang. "Research on Convolutional Neural Network Inference Acceleration and Performance Optimization for Edge Intelligence". Sensors 24, n.º 1 (31 de dezembro de 2023): 240. http://dx.doi.org/10.3390/s24010240.
Texto completo da fonteLiu, Yang, Yiheng Zhang, Xiaoran Hao, Lan Chen, Mao Ni, Ming Chen e Rong Chen. "Design of a Convolutional Neural Network Accelerator Based on On-Chip Data Reordering". Electronics 13, n.º 5 (4 de março de 2024): 975. http://dx.doi.org/10.3390/electronics13050975.
Texto completo da fonteRo, Yuhwan, Eojin Lee e Jung Ahn. "Evaluating the Impact of Optical Interconnects on a Multi-Chip Machine-Learning Architecture". Electronics 7, n.º 8 (27 de julho de 2018): 130. http://dx.doi.org/10.3390/electronics7080130.
Texto completo da fonteHuang, Hongmin, Zihao Liu, Taosheng Chen, Xianghong Hu, Qiming Zhang e Xiaoming Xiong. "Design Space Exploration for YOLO Neural Network Accelerator". Electronics 9, n.º 11 (16 de novembro de 2020): 1921. http://dx.doi.org/10.3390/electronics9111921.
Texto completo da fonteChen, Zhimei. "Hardware Accelerated Optimization of Deep Learning Model on Artificial Intelligence Chip". Frontiers in Computing and Intelligent Systems 6, n.º 2 (15 de dezembro de 2023): 11–14. http://dx.doi.org/10.54097/fcis.v6i2.03.
Texto completo da fonteBrennsteiner, Stefan, Tughrul Arslan, John Thompson e Andrew McCormick. "A Real-Time Deep Learning OFDM Receiver". ACM Transactions on Reconfigurable Technology and Systems 15, n.º 3 (30 de setembro de 2022): 1–25. http://dx.doi.org/10.1145/3494049.
Texto completo da fonteCho, Mannhee, e Youngmin Kim. "FPGA-Based Convolutional Neural Network Accelerator with Resource-Optimized Approximate Multiply-Accumulate Unit". Electronics 10, n.º 22 (19 de novembro de 2021): 2859. http://dx.doi.org/10.3390/electronics10222859.
Texto completo da fonteChoubey, Abhishek, e Shruti Bhargava Choubey. "A Promising Hardware Accelerator with PAST Adder". Advances in Science and Technology 105 (abril de 2021): 241–48. http://dx.doi.org/10.4028/www.scientific.net/ast.105.241.
Texto completo da fontede Sousa, André L., Mário P. Véstias e Horácio C. Neto. "Multi-Model Inference Accelerator for Binary Convolutional Neural Networks". Electronics 11, n.º 23 (30 de novembro de 2022): 3966. http://dx.doi.org/10.3390/electronics11233966.
Texto completo da fonteKang, Soongyu, Seongjoo Lee e Yunho Jung. "Design of Network-on-Chip-Based Restricted Coulomb Energy Neural Network Accelerator on FPGA Device". Sensors 24, n.º 6 (15 de março de 2024): 1891. http://dx.doi.org/10.3390/s24061891.
Texto completo da fonteCosatto, E., e H. P. Craf. "A neural network accelerator for image analysis". IEEE Micro 15, n.º 3 (junho de 1995): 32–38. http://dx.doi.org/10.1109/40.387680.
Texto completo da fonteKuznar, Damian, Robert Szczygiel, Piotr Maj e Anna Kozioł. "Design of artificial neural network hardware accelerator". Journal of Instrumentation 18, n.º 04 (1 de abril de 2023): C04013. http://dx.doi.org/10.1088/1748-0221/18/04/c04013.
Texto completo da fonteWang, Yuejiao, Zhong Ma e Zunming Yang. "Sequential Characteristics Based Operators Disassembly Quantization Method for LSTM Layers". Applied Sciences 12, n.º 24 (12 de dezembro de 2022): 12744. http://dx.doi.org/10.3390/app122412744.
Texto completo da fonteSeto, Kenshu. "A Survey on System-Level Design of Neural Network Accelerators". Journal of Integrated Circuits and Systems 16, n.º 2 (18 de agosto de 2021): 1–10. http://dx.doi.org/10.29292/jics.v16i2.505.
Texto completo da fontePark, Sang-Soo, e Ki-Seok Chung. "CONNA: Configurable Matrix Multiplication Engine for Neural Network Acceleration". Electronics 11, n.º 15 (29 de julho de 2022): 2373. http://dx.doi.org/10.3390/electronics11152373.
Texto completo da fonteWang, Hongzhe, Junjie Wang, Hao Hu, Guo Li, Shaogang Hu, Qi Yu, Zhen Liu, Tupei Chen, Shijie Zhou e Yang Liu. "Ultra-High-Speed Accelerator Architecture for Convolutional Neural Network Based on Processing-in-Memory Using Resistive Random Access Memory". Sensors 23, n.º 5 (21 de fevereiro de 2023): 2401. http://dx.doi.org/10.3390/s23052401.
Texto completo da fonteGowda, Kavitha Malali Vishveshwarappa, Sowmya Madhavan, Stefano Rinaldi, Parameshachari Bidare Divakarachari e Anitha Atmakur. "FPGA-Based Reconfigurable Convolutional Neural Network Accelerator Using Sparse and Convolutional Optimization". Electronics 11, n.º 10 (22 de maio de 2022): 1653. http://dx.doi.org/10.3390/electronics11101653.
Texto completo da fonteC., Dr Aarthi, e Kowsalya S. "Feed Forward Neural Network With Column-Wise Matrix–Vector Multiplication on FPGAs". International Research Journal of Computer Science 11, n.º 04 (5 de abril de 2024): 355–59. http://dx.doi.org/10.26562/irjcs.2024.v1104.42.
Texto completo da fonteHou, Jia, Zichu Liu, Zepeng Yang e Chen Yang. "Hardware Trojan Attacks on the Reconfigurable Interconnections of Field-Programmable Gate Array-Based Convolutional Neural Network Accelerators and a Physically Unclonable Function-Based Countermeasure Detection Technique". Micromachines 15, n.º 1 (19 de janeiro de 2024): 149. http://dx.doi.org/10.3390/mi15010149.
Texto completo da fonteDeng, Bao, e Hao Lv. "Research on Dynamic Reconfigurable Convolutional Neural Network Accelerator". Journal of Physics: Conference Series 1952, n.º 3 (1 de junho de 2021): 032045. http://dx.doi.org/10.1088/1742-6596/1952/3/032045.
Texto completo da fonteYAN, Jiale, Ying ZHANG, Fengbin TU, Jianxun YANG, Shixuan ZHENG, Peng OUYANG, Leibo LIU, Yuan XIE, Shaojun WEI e Shouyi YIN. "Research on low-power neural network computing accelerator". SCIENTIA SINICA Informationis 49, n.º 3 (1 de março de 2019): 314–33. http://dx.doi.org/10.1360/n112018-00282.
Texto completo da fonteKim, Doo Young, Jin Min Kim, Hakbeom Jang, Jinkyu Jeong e Jae W. Lee. "A neural network accelerator for mobile application processors". IEEE Transactions on Consumer Electronics 61, n.º 4 (novembro de 2015): 555–63. http://dx.doi.org/10.1109/tce.2015.7389812.
Texto completo da fonteGao, Chang, Antonio Rios-Navarro, Xi Chen, Shih-Chii Liu e Tobi Delbruck. "EdgeDRNN: Recurrent Neural Network Accelerator for Edge Inference". IEEE Journal on Emerging and Selected Topics in Circuits and Systems 10, n.º 4 (dezembro de 2020): 419–32. http://dx.doi.org/10.1109/jetcas.2020.3040300.
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