Artigos de revistas sobre o tema "Modeling of processor design"
Crie uma referência precisa em APA, MLA, Chicago, Harvard, e outros estilos
Veja os 50 melhores artigos de revistas para estudos sobre o assunto "Modeling of processor design".
Ao lado de cada fonte na lista de referências, há um botão "Adicionar à bibliografia". Clique e geraremos automaticamente a citação bibliográfica do trabalho escolhido no estilo de citação de que você precisa: APA, MLA, Harvard, Chicago, Vancouver, etc.
Você também pode baixar o texto completo da publicação científica em formato .pdf e ler o resumo do trabalho online se estiver presente nos metadados.
Veja os artigos de revistas das mais diversas áreas científicas e compile uma bibliografia correta.
Li, Lei, Hai-bin Shen, Kai Huang, Xiao-lang Yan, Han Sangil e Ahmed A Jerraya. "Distributed Memory Service Modeling in Multi-Processor Design". Journal of Electronics & Information Technology 30, n.º 11 (14 de abril de 2011): 2750–54. http://dx.doi.org/10.3724/sp.j.1146.2007.00596.
Texto completo da fonteEyerman, Stijn, e Lieven Eeckhout. "Probabilistic job symbiosis modeling for SMT processor scheduling". ACM SIGPLAN Notices 45, n.º 3 (5 de março de 2010): 91–102. http://dx.doi.org/10.1145/1735971.1736033.
Texto completo da fonteLee, Je-Hoon. "Power Modeling Framework for an Asynchronous Processor". Journal of Circuits, Systems and Computers 25, n.º 06 (31 de março de 2016): 1650057. http://dx.doi.org/10.1142/s0218126616500572.
Texto completo da fonteLIN, S., Y. CHEN, C. YU, Y. LIU e C. LEE. "Dynamic modeling and control structure design of an experimental fuel processor". International Journal of Hydrogen Energy 31, n.º 3 (março de 2006): 413–26. http://dx.doi.org/10.1016/j.ijhydene.2005.06.027.
Texto completo da fonteWu, Wei, Shu-Bo Yang, Jenn-Jiang Hwang e Xinggui Zhou. "Design, modeling, and optimization of a lightweight MeOH-to-H2 processor". International Journal of Hydrogen Energy 43, n.º 31 (agosto de 2018): 14451–65. http://dx.doi.org/10.1016/j.ijhydene.2018.05.135.
Texto completo da fonteSo, Hwisoo, Yohan Ko, Jinhyo Jung, Kyoungwoo Lee e Aviral Shrivastava. "gemV-tool: A Comprehensive Soft Error Reliability Estimation Tool for Design Space Exploration". Electronics 12, n.º 22 (8 de novembro de 2023): 4573. http://dx.doi.org/10.3390/electronics12224573.
Texto completo da fonteKumar, K. S., e J. H. Tracey. "Modeling and Description of Processor-Based Systems with DTMSII". IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 6, n.º 1 (janeiro de 1987): 116–27. http://dx.doi.org/10.1109/tcad.1987.1270254.
Texto completo da fonteMartin, Grant. "Multi-Processor SoC-Based Design Methodologies Using Configurable and Extensible Processors". Journal of Signal Processing Systems 53, n.º 1-2 (29 de novembro de 2007): 113–27. http://dx.doi.org/10.1007/s11265-007-0153-7.
Texto completo da fonteMartono e Zulfi. "Perancangan Aplikasi Point of Sale (POS) pada Karya Maju Jaya". Jurnal PROCESSOR 17, n.º 2 (28 de outubro de 2022): 114–24. http://dx.doi.org/10.33998/processor.2022.17.2.1266.
Texto completo da fonteOliveira, Marcio F. da S., Eduardo W. Brião, Francisco A. Nascimento e Flávio R. Wagner. "Model Driven Engineering for MPSoC Design Space Exploration". Journal of Integrated Circuits and Systems 3, n.º 1 (18 de novembro de 2008): 13–22. http://dx.doi.org/10.29292/jics.v3i1.277.
Texto completo da fonteFleury, M., A. C. Downton e A. F. Clark. "Modelling pipelines for embedded parallel processor system design". Electronics Letters 33, n.º 22 (1997): 1852. http://dx.doi.org/10.1049/el:19971249.
Texto completo da fonteLakhdara, Zakaria, e Salah Merniz. "A SysML and CLEAN Based Methodology for RISC Processor Micro-Architecture Design". International Journal of Embedded and Real-Time Communication Systems 6, n.º 1 (janeiro de 2015): 101–31. http://dx.doi.org/10.4018/ijertcs.2015010105.
Texto completo da fonteEeckhout, Lieven, Robert H. Bell Jr., Bastiaan Stougie, Koen De Bosschere e Lizy K. John. "Control Flow Modeling in Statistical Simulation for Accurate and Efficient Processor Design Studies". ACM SIGARCH Computer Architecture News 32, n.º 2 (2 de março de 2004): 350. http://dx.doi.org/10.1145/1028176.1006730.
Texto completo da fonteConte, T. M., K. N. Menezes, S. W. Sathaye e M. C. Toburen. "System-level power consumption modeling and tradeoff analysis techniques for superscalar processor design". IEEE Transactions on Very Large Scale Integration (VLSI) Systems 8, n.º 2 (abril de 2000): 129–37. http://dx.doi.org/10.1109/92.831433.
Texto completo da fontePrado, Bruno, Edna Barros, Thiago Figueredo e André Aziz. "HdSC: A Fast and Preemptive Modeling for on Host HdS Development". Journal of Integrated Circuits and Systems 7, n.º 1 (27 de dezembro de 2012): 61–71. http://dx.doi.org/10.29292/jics.v7i1.356.
Texto completo da fonteChakraborty, Bidesh, Mamata Dalui e Biplab K. Sikdar. "Design of a Reliable Cache System for Heterogeneous CMPs". Journal of Circuits, Systems and Computers 27, n.º 14 (23 de agosto de 2018): 1850219. http://dx.doi.org/10.1142/s0218126618502195.
Texto completo da fonteKnopf, George K., e Madan M. Gupta. "Design of a multitask neurovision processor". Journal of Mathematical Imaging and Vision 2, n.º 2-3 (novembro de 1992): 233–50. http://dx.doi.org/10.1007/bf00118592.
Texto completo da fonteGadag, Shiva P., Susan K. Patra, Volkan Ozguz, Phillipe Marchand e Sadik Esener. "Design and Analysis: Thermal Emulator Cubes for Opto-Electronic Stacked Processor". Journal of Electronic Packaging 124, n.º 3 (26 de julho de 2002): 198–204. http://dx.doi.org/10.1115/1.1481894.
Texto completo da fonteFleury, M., R. P. Self e A. C. Downton. "Large-Scale, Parallel Embedded Applications: A Hardware Design Model for Software Engineers". International Journal of Electrical Engineering & Education 38, n.º 4 (outubro de 2001): 348–67. http://dx.doi.org/10.7227/ijeee.38.4.8.
Texto completo da fonteReshadi, Mehrdad, Bita Gorjiara e Nikil D. Dutt. "Generic Processor Modeling for Automatically Generating Very Fast Cycle-Accurate Simulators". IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 25, n.º 12 (dezembro de 2006): 2904–18. http://dx.doi.org/10.1109/tcad.2006.882597.
Texto completo da fonteKim, Sung Je, e Young Man Cho. "Optimal design of a rapid thermal processor via physics-based modeling and convex optimization". Control Engineering Practice 10, n.º 11 (novembro de 2002): 1199–210. http://dx.doi.org/10.1016/s0967-0661(02)00098-9.
Texto completo da fonteUma, S., e P. Sakthivel. "Hardware Evaluation and Software Framework Construction for Performance Measurement of Embedded Processor". Journal of Computational and Theoretical Nanoscience 15, n.º 2 (1 de fevereiro de 2018): 586–94. http://dx.doi.org/10.1166/jctn.2018.7126.
Texto completo da fonteJain, Abhishek, e Richa Gupta. "Unified and Modular Modeling and Functional Verification Framework of Real-Time Image Signal Processors". VLSI Design 2016 (26 de setembro de 2016): 1–14. http://dx.doi.org/10.1155/2016/7283471.
Texto completo da fontePon Pushpa, S. Ewins, e Manamalli Devasikamani. "Schedulability Analysis for Rate Monotonic Algorithm-Shortest Job First Using UML-RT". Modelling and Simulation in Engineering 2014 (2014): 1–10. http://dx.doi.org/10.1155/2014/206364.
Texto completo da fonteYao, Wu-Sung. "Modeling and stabilization of eccentric gravity machinery". Advances in Mechanical Engineering 10, n.º 1 (janeiro de 2018): 168781401775178. http://dx.doi.org/10.1177/1687814017751782.
Texto completo da fonteZou, An, Huifeng Zhu, Jingwen Leng, Xin He, Vijay Janapa Reddi, Christopher D. Gill e Xuan Zhang. "System-level Early-stage Modeling and Evaluation of IVR-assisted Processor Power Delivery System". ACM Transactions on Architecture and Code Optimization 18, n.º 4 (31 de dezembro de 2021): 1–27. http://dx.doi.org/10.1145/3468145.
Texto completo da fonteChadha, Ankit, Shreyas Gaonkar e Aditi Desai. "Design, Modeling and Implementation of 8-bit Processor for Intelligent Automatic Chocolate Vending Machine (AVM)". International Journal of Computer Applications 89, n.º 17 (26 de março de 2014): 1–7. http://dx.doi.org/10.5120/15720-4549.
Texto completo da fonteZhang, Qi, e Wenhui Pei. "DSP Processer-in-the-Loop Tests Based on Automatic Code Generation". Inventions 7, n.º 1 (11 de janeiro de 2022): 12. http://dx.doi.org/10.3390/inventions7010012.
Texto completo da fonteOgbodo, Mark, Khanh Dang, Fukuchi Tomohide e Abderazek Abdallah. "Architecture and Design of a Spiking Neuron Processor Core Towards the Design of a Large-scale Event-Driven 3D-NoC-based Neuromorphic Processor". SHS Web of Conferences 77 (2020): 04003. http://dx.doi.org/10.1051/shsconf/20207704003.
Texto completo da fonteLiu, Shaohan, e Dake Liu. "Design Space Exploration of 1-D FFT Processor". Journal of Signal Processing Systems 90, n.º 11 (23 de julho de 2018): 1609–21. http://dx.doi.org/10.1007/s11265-018-1393-4.
Texto completo da fonteGarrett, James H., e Steven J. Fenves. "A knowledge-based standards processor for structural component design". Engineering with Computers 2, n.º 4 (dezembro de 1987): 219–38. http://dx.doi.org/10.1007/bf01276414.
Texto completo da fonteZiolek, Scott A., e Pieter C. Kruithof. "Human Modeling & Simulation: A Primer for Practitioners". Proceedings of the Human Factors and Ergonomics Society Annual Meeting 44, n.º 38 (julho de 2000): 825–27. http://dx.doi.org/10.1177/154193120004403839.
Texto completo da fonteDuan, Feng Yang, Li Min Chang e Ye Zhan. "Realization of the Detecting Method for Aircraft Digital Image Transmission System Based on Multi-Processor". Advanced Materials Research 490-495 (março de 2012): 2352–56. http://dx.doi.org/10.4028/www.scientific.net/amr.490-495.2352.
Texto completo da fonteSrinivasan, V. Prasanna, e A. P. Shanthi. "A BBN-Based Framework for Design Space Pruning of Application Specific Instruction Processors". Journal of Circuits, Systems and Computers 25, n.º 04 (2 de fevereiro de 2016): 1650028. http://dx.doi.org/10.1142/s0218126616500286.
Texto completo da fonteHamblen, James O. "Using Vhdl Based Modeling, Synthesis, and Simulation in an Introductory Computer Architecture Laboratory". International Journal of Electrical Engineering & Education 33, n.º 3 (julho de 1996): 251–60. http://dx.doi.org/10.1177/002072099603300306.
Texto completo da fonteSarigul, N., M. Jin, G. R. Kolar e H. A. Kamel. "Design of array processor software for nonlinear structural analysis". Computers & Structures 20, n.º 6 (1985): 963–74. http://dx.doi.org/10.1016/0045-7949(85)90016-1.
Texto completo da fonteUgwueze, Ogechukwu Kingsley, Chijindu C. V., Udeze C. C., Ahaneku A. M., Eneh N. J., Obinna M. Ezeja e Edward C. Anoliefo. "Modeling cache performance for embedded systems". Bulletin of Electrical Engineering and Informatics 10, n.º 5 (1 de outubro de 2021): 2910–20. http://dx.doi.org/10.11591/eei.v10i5.2459.
Texto completo da fonteKIM, H. Y. "Trace-Driven Performance Simulation Modeling for Fast Evaluation of Multimedia Processor by Simulation Reuse". IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences E88-A, n.º 12 (1 de dezembro de 2005): 3306–14. http://dx.doi.org/10.1093/ietfec/e88-a.12.3306.
Texto completo da fonteBAHN, JUN HO, SEUNG EUN LEE, YOON SEOK YANG, JUNGSOOK YANG e NADER BAGHERZADEH. "ON DESIGN AND APPLICATION MAPPING OF A NETWORK-ON-CHIP(NOC) ARCHITECTURE". Parallel Processing Letters 18, n.º 02 (junho de 2008): 239–55. http://dx.doi.org/10.1142/s0129626408003363.
Texto completo da fonteBai, Mingsian R., e Kwuen-Yieng Ou. "Design and Implementation of Electromagnetic Active Control Actuators". Journal of Vibration and Control 9, n.º 8 (agosto de 2003): 997–1017. http://dx.doi.org/10.1177/10775463030098006.
Texto completo da fonteDzitac, Pavel, e Md Mazid Abdul. "Modeling of an Object Manipulation Motion Planner and Grasping Rules". Applied Mechanics and Materials 278-280 (janeiro de 2013): 664–72. http://dx.doi.org/10.4028/www.scientific.net/amm.278-280.664.
Texto completo da fonteHaj Ahmad, Hanan, Ehab M. Almetwally e Dina A. Ramadan. "Investigating the Relationship between Processor and Memory Reliability in Data Science: A Bivariate Model Approach". Mathematics 11, n.º 9 (3 de maio de 2023): 2142. http://dx.doi.org/10.3390/math11092142.
Texto completo da fonteZhang, Zeng Nian, Zun Yi Wang, Mian Mian Chen e Jiong Shi. "Intelligent Transportation Video Detecting System Based on DSP". Applied Mechanics and Materials 701-702 (dezembro de 2014): 498–504. http://dx.doi.org/10.4028/www.scientific.net/amm.701-702.498.
Texto completo da fonteISKANDARANI, MAHMOUD Z. "MATHEMATICAL MODELING OF THE PROGRAMING FIELD IN A NEURAL SWITCH USING THE SEMI-INFINITE COPLANAR ELECTRODE APPROXIMATION". Advances in Complex Systems 09, n.º 03 (setembro de 2006): 193–207. http://dx.doi.org/10.1142/s021952590600080x.
Texto completo da fonteA S, Asif Ahmad. "A Cost Effective DVI interface on Virtex-5 FPGA Through Verilog HDL". INTERNATIONAL JOURNAL OF COMPUTERS & TECHNOLOGY 13, n.º 2 (12 de abril de 2014): 4230–36. http://dx.doi.org/10.24297/ijct.v13i2.2905.
Texto completo da fonteZaitsev, Vladimir, e Evgeniy Tsybaev. "Estimation of timing characteristics in real-time computer systems using Petri nets". Management of Development of Complex Systems, n.º 54 (2 de junho de 2023): 48–62. http://dx.doi.org/10.32347/2412-9933.2023.54.48-62.
Texto completo da fonteLee, Ki Dong, Bum Hee Lee e Myoung Sam Ko. "A comparative model-based analysis and design for multi-robot systems". Robotica 13, n.º 1 (janeiro de 1995): 65–76. http://dx.doi.org/10.1017/s0263574700017495.
Texto completo da fonteDiehl, Joao B., e Eduardo W. Bergamini. "The L language for parallel processor machines". SIMULATION 58, n.º 1 (janeiro de 1992): 49–61. http://dx.doi.org/10.1177/003754979205800108.
Texto completo da fonteYADAV, PRADEEP KUMAR, M. P. SINGH e KULDEEP SHARMA. "TASK ALLOCATION MODEL FOR RELIABILITY AND COST OPTIMIZATION IN DISTRIBUTED COMPUTING SYSTEM". International Journal of Modeling, Simulation, and Scientific Computing 02, n.º 02 (junho de 2011): 131–49. http://dx.doi.org/10.1142/s179396231100044x.
Texto completo da fonteBeaman, Brian, e Jean Audet. "High Current Testing and Simulation for Land Grid Array Sockets". International Symposium on Microelectronics 2017, n.º 1 (1 de outubro de 2017): 000659–62. http://dx.doi.org/10.4071/isom-2017-poster3_002.
Texto completo da fonte