Literatura científica selecionada sobre o tema "Memory transistor"
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Artigos de revistas sobre o assunto "Memory transistor"
Xie, Fangqing, Maryna N. Kavalenka, Moritz Röger, Daniel Albrecht, Hendrik Hölscher, Jürgen Leuthold e Thomas Schimmel. "Copper atomic-scale transistors". Beilstein Journal of Nanotechnology 8 (1 de março de 2017): 530–38. http://dx.doi.org/10.3762/bjnano.8.57.
Texto completo da fonteChoi, Young Jin, Jihyun Kim, Min Je Kim, Hwa Sook Ryu, Han Young Woo, Jeong Ho Cho e Joohoon Kang. "Hysteresis Behavior of the Donor–Acceptor-Type Ambipolar Semiconductor for Non-Volatile Memory Applications". Micromachines 12, n.º 3 (12 de março de 2021): 301. http://dx.doi.org/10.3390/mi12030301.
Texto completo da fonteKim, Woojo, Jimin Kwon e Sungjune Jung. "3D Integration of Flexible and Printed Electronics: Integrated Circuits, Memories, and Sensors". Journal of Flexible and Printed Electronics 2, n.º 2 (dezembro de 2023): 199–210. http://dx.doi.org/10.56767/jfpe.2023.2.2.199.
Texto completo da fonteKim, Ji-Hun, Hyeon-Jun Kim, Ki-Jun Kim, Tae-Hun Shim, Jin-Pyo Hong e Jea-gun Park. "3-Terminal Igzo FET Based 2T0C DRAM Combined Bit-Line Structure". ECS Meeting Abstracts MA2023-02, n.º 30 (22 de dezembro de 2023): 1561. http://dx.doi.org/10.1149/ma2023-02301561mtgabs.
Texto completo da fonteAl-shawi, Amjad, Maysoon Alias, Paul Sayers e Mohammed Fadhil Mabrook. "Improved Memory Properties of Graphene Oxide-Based Organic Memory Transistors". Micromachines 10, n.º 10 (25 de setembro de 2019): 643. http://dx.doi.org/10.3390/mi10100643.
Texto completo da fonteBrtník, Bohumil. "Assembling a Formula for Current Transferring by Using a Summary Graph and Transformation Graphs". Journal of Electrical Engineering 64, n.º 5 (1 de setembro de 2013): 334–36. http://dx.doi.org/10.2478/jee-2013-0050.
Texto completo da fonteGrudanov, Oleksandr. "Stability Parameters of Register File Bit Cell with Low Power Consumption Priority". Electronics and Control Systems 3, n.º 77 (27 de setembro de 2023): 40–46. http://dx.doi.org/10.18372/1990-5548.77.17963.
Texto completo da fonteFuller, Elliot J., Scott T. Keene, Armantas Melianas, Zhongrui Wang, Sapan Agarwal, Yiyang Li, Yaakov Tuchman et al. "Parallel programming of an ionic floating-gate memory array for scalable neuromorphic computing". Science 364, n.º 6440 (25 de abril de 2019): 570–74. http://dx.doi.org/10.1126/science.aaw5581.
Texto completo da fonteSrinivasarao, B. N., e K. Chandrabhushana Rao. "Design and Analysis of Area Efficient 128 Bytes SRAM Architecture". Journal of VLSI Design and Signal Processing 8, n.º 1 (30 de março de 2022): 19–26. http://dx.doi.org/10.46610/jovdsp.2022.v08i01.004.
Texto completo da fonteSeo, Yeongkyo, e Kon-Woo Kwon. "Ultra High-Density SOT-MRAM Design for Last-Level On-Chip Cache Application". Electronics 12, n.º 20 (12 de outubro de 2023): 4223. http://dx.doi.org/10.3390/electronics12204223.
Texto completo da fonteTeses / dissertações sobre o assunto "Memory transistor"
Nominanda, Helinda. "Amorphous silicon thin film transistor as nonvolatile device". Texas A&M University, 2008. http://hdl.handle.net/1969.1/86004.
Texto completo da fonteSarkar, Manju. "Lambda Bipolar Transistor (LBT) in Static Random Access Memory Cell". Thesis, Indian Institute of Science, 1995. https://etd.iisc.ac.in/handle/2005/124.
Texto completo da fonteSarkar, Manju. "Lambda Bipolar Transistor (LBT) in Static Random Access Memory Cell". Thesis, Indian Institute of Science, 1995. http://hdl.handle.net/2005/124.
Texto completo da fonteVagts, Christopher Bryan. "A single-transistor memory cell and sense amplifier for a gallium arsenide dynamic random access memory". Thesis, Monterey, California. Naval Postgraduate School, 1992. http://hdl.handle.net/10945/24038.
Texto completo da fonteThis thesis presents the design and layout of a Gallium Arsenide (GaAs) Dynamic Random Access Memory (DRAM) cell. Attempts have been made at producing GaAs DRAM cells, but these have dealt with modifications to the fabrication process, are expensive, and have met with little success. An eight-address by one-bit memory is designed, simulated, and laid out for a standard GaAs digital fabrication process. Three different configurations of RAM cells are considered: the Three-Transistor RAM Cell, the One-Transistor RAM Cell with a Diode and the One-Transistor RAM Cell with a capacitor. All are tested and compared using the circuit simulator HSPICE. The chosen DRAM design uses the One- Transistor RAM Cell with a parallel plate capacitor and a five-transistor differential sense amplifier that handles reading as well as refresh of the memory cells. The differential sense amplifier compares a dummy cell with a memory cell to perform a read. The required timing is presented and demonstrated with read, write, and refresh cycles. Actions to minimize charge leakage are also considered and discussed. The design is simulated for access rates of approximately five nanoseconds, but the basic design can work at much faster rates with little modification.
Chaudhary, Mahima. "Colloidal nanocrystals for optoelectronic devices optically controlled at the nanometric scale". Electronic Thesis or Diss., Université Paris sciences et lettres, 2022. http://www.theses.fr/2022UPSLS072.
Texto completo da fonteOptoelectronics is a rapidly growing technology field that involves the use of electronic devices to source, detect, and control light. These devices can be used in a variety of applications such as photoconductive switches, automatic access control systems, telecommunications, memory, and many others. Because this is such a broad field, the variety of devices that fall under optoelectronics is vast. In this, PhD thesis, I am particularily intrested in solution processed colloidal nanomaterials that can allow light-matter intraction. To begin, I first focused on colloidal synthesis. The work on this part yileds two different types of colloidal nanocrystals : (1) Er3+-doped NaYF4 nanocrystals, capable to absorb and up-convert short-wave infrared photons such as those with = 1.5 µm to visible photons; (2) carbon quantum dots (CQDs) with nitrogen-doping, capable to absorb UV photons and down-shift them into visible fluorescence. Upon obtaining the desired colloidal nanocrystals with suitable optical properties, I subsequently applied them into two type of optoelectronic devices: Photoconductive switches, which allow optical control over the magnitude and phase of microwave signals to be transmitted. To achieve microwave photoconductive switches functional at = 1.55 µm illumination, the above-mentioned Er3+-doped NaYF4 upconversion nanocrystals were deposited directly onto low-temperature-grown gallium arsenide (LT-GaAs) to achieve photoconductive switches. The properties of these devices were then characterized. Thanks to the photon upconversion properties of these nanocrystals, the hybrid photoconductive switch exhibit an ON/OFF ratio more than 2-fold higher in decibels than the control device without nanocrystals applied. (ii) Field-effect transistor (FET)-based optoelectronic memories. In this field, the charge storage medium plays a critical role to the memory’s performance. In this part, I harnessed the unique charge-trapping and charge-retention properties of the above-mentioned colloidal nitrogen-doped (N-doped) CQDs to achieve functional optoelectronic memories programmable by UV illumination and with a multilevel writing possibility. In particular, a long-lasting memory function can be achieved thanks to the vast hole trapping sites provided by these CQDs and the resultant photo-gating effect excercised on the graphene FET, while memory erasing can be achieved via a positive gate bias that provides sufficient carriers for charge recombination. The result of this PhD thesis highlights the engineering and chemical controls to obtain high-performance optoelectronic devices such as microwave photoconductive switches and all-carbon non-volatile FET-based optoelectronic memories through manipulating and harvesting the optical and electronic properties of colloidal nanomaterials
Almeida, Luciano Mendes. "Estudo de célula de memória dinâmica de apenas um transistor SOI de óxido enterrado ultrafino". Universidade de São Paulo, 2012. http://www.teses.usp.br/teses/disponiveis/3/3140/tde-18072013-144946/.
Texto completo da fonteIn this study was analyzed the behavior of one transistor called UTBOX (Ultra Thin Buried Oxide) FD SOI MOSFET (Fully Depleted Silicon-on-Insulator Metal- Oxide-Semiconductor Field-Effect-Transistor) working as a 1T-FBRAM (Single Transistor Floating Body Random Access Memory). This memory device is an evolution from conventional memories 1T1C-DRAM, however formed by only one transistor, the device itself is responsible for the storage of the information through the floating body effect. Thus two dimensional simulations were performed, where were obtained dynamic curves, and from these curves it was possible to extract and analyze some of the main parameters, such as, trigger drain voltage, sense margin current, read window, and the retention time, beyond the mechanisms in each state of memory (write, read and hold). Among the possible ways to program the data 1 in this technology were used the methods GIDL (Gate Induced Drain Leakage) and BJT (Bipolar Junction Transistor). By the GIDL method it was possible to operate the memory cell at high speed without spending significant power, showing that this method is very promising for low-power high-speed. Furthermore, greater stability was obtained in read operation when it is biased at point ZTC (zero-Temperature Coefficient) due to the current level of datum \'0\' remain stable even with temperature variation. By the BJT method, it was studied the influence of the silicon film thickness and the buried oxide thickness, and it was noted a strong dependence on minimum drain voltage for programming the data \'1\' as a function of both thicknesses. As the thickness of the silicon film becomes thinner, the trigger drain voltage increases due to stronger coupling. However, it was observed that the level of the trigger drain voltage can be modulated by the substrate bias in this way it is possible to operate the cell with lower voltage avoiding the damage and increasing the lifetime of the device. About the temperature, with its increase it was observed that the minimum drain voltage required to trigger the writing datum \'1\' decreased favoring the programming the cell. However the retention time is harmed (becomes smaller) due to the increment of leakage current in the PN junction. Analyzing the impact of the first and second gate on sense margin current and retention time, it was verified that depending on the voltage applied to the gate during the hold condition, the retention time may be limited by the generation or recombination of the carriers (holes). It was noted that there is a compromise between obtaining the best sense margin current and the best retention time. Since the retention is the most critical parameter, more attention should be given in order to obtain the optimization of this latter. It is concluded in this analysis that the best bias to retain the datum for longer time is the first interface being in accumulation mode and the second in depletion mode. In the study of biasing the drain during the read operation, it has been observed that the use of high drain voltage provides high sense margin, but at the same time, this polarization affect the data \'0\' due to high level of holes generation induced by impact ionization, which shortens the retention time and destroys the data \'0\' in multiple read operations. However, for low drain voltage during read operations it was possible to perform multiple read operations without losing the stored data and also higher retention time was obtained.
Hilgers, Brandon. "SRAM Compiler For Automated Memory Layout Supporting Multiple Transistor Process Technologies". DigitalCommons@CalPoly, 2015. https://digitalcommons.calpoly.edu/theses/1423.
Texto completo da fonteSasaki, Kátia Regina Akemi. "Propostas de melhorias de desempenho de célula de memória dinâmica utilizando um único transistor UTBOX SOI". Universidade de São Paulo, 2013. http://www.teses.usp.br/teses/disponiveis/3/3140/tde-26072013-173443/.
Texto completo da fonteIn this work, it was analyzed the behavior of a planar UTBOX FD SOI NMOSFET (Ultra-Thin-Buried-Oxide Fully-Depleted Silicon-on-Insulator Metal- Oxide-Semiconductor Field-Effect-Transistor), as a 1T-DRAM (Single Transistor Dynamic Random Access Memory) cell, focusing on the best biases and other proposals for enabling the 1T-DRAM applications. Therefore, it was analyzed the effects of different biases (gate, drain and substrate), as well as the influence of the concentration of a less doped source/drain extension region on the main parameters of this kind of memory. Thus, it was analyzed some of the main memory parameters such as the trigger drain voltage, the sense margin, the read window and the retention time, as well as the mechanisms operating in each state of the memory (writing, reading and holding). Finally, it were proposed some performance enhancements for the retention time of this kind of memory. It was observed that the increase in temperature facilitates the memory write decreasing the minimum drain bias and time required for writing, but reduces the sense margin. It was also verified that, despite the thinner silicon film and buried oxide increase the drain voltage required to activate the BJT effect (parasitic bipolar effect), a positive potential on the substrate may reduce this requirement (61% for back gate bias varying from 0 to 1,5V), being an alternative for solving the problem and allowing the use of smaller devices as a memory cell. Furthermore, it was seen that there can be a carriers generation or recombination, depending on the gate voltage during the holding state, degrading the bit \'0\' or \'1\'. Moreover, the optimization of substrate bias proved to be limited by enabling the writing state, without degrading the reading of \'0\'. The results also demonstrated the sense margin is less dependent on the substrate voltage than the retention time, therefore, the retention time was considered as a more critical parameter. With respect to the reading state, there was the presence of BJT effect also in this state, increasing the margin of sensitivity (60%) and reducing the retention time (66%) and the number of possible readings without updating the data (over 30 for 22 readings) in cases of higher drain bias. On the topic of the concentration of the source and drain extensions, the devices with source and drain extensions presented a generation rate lower (about 12 orders of magnitude), resulting in a retention time far longer than the reference one (about 3 orders of magnitude). About its downscaling, the retention time decreased for shorter channel lengths (almost 2 orders of magnitude), which is a limiting factor for 1T-DRAM future generations. Nevertheless, when it was compared to the conventional devices with source and drain extensions, theirs retention time increased (almost 1 order of magnitude), allowing the use of shorter channel lengths (30nm against 50nm of reference device) and lower back gate biases. Another proposal presented to improve the retention time was the pulsed back gate only during the writing \'1\' state, which resulted in an increase on the retention time by 17%. Finally, we also studied the band gap influence motivated by the use of new materials for the semiconductor film. It was observed that higher band gaps increase the retention time by up to 5 orders of magnitude, allowing a retention time closer to the current conventional DRAMs.
Boubaker, Aimen. "Modelisation des composants mono-electroniques : Single-Electron Transistor et Single-Electron Memory". Lyon, INSA, 2010. http://theses.insa-lyon.fr/publication/2010ISAL0046/these.pdf.
Texto completo da fonte[This work concerns the study of SET/SEM single electron memories for CMOS technologies. The first part presents a review of quantum and Coulomb blockade effects in electronic nanodevices. In a second part, we present the main electrical models proposed for single electron devices. A comparison between semiconductor-based and metall ic-based single electron transistors. The third part of the thesis presents the SET/SEM memory structure on the basis of SIMON simulations. The device consists on the coupling of a metallic SET operating at high temperature with a metalli c memory node. Finnaly, an optimized memory device has been proposed in the Ti/Tiüx system. The proposed memory is able to write and erase a discrete number of electrons varying from 0 to 7 at room temperature. This opens the possibility of multilevel memory circuits. Finally, we have studied the data retenti on performances of the memory in the last part of this thesis. After the first simulations with the Ti/Tiüx materials system, we have simulated various metallic systems such as Pt, Au, TiSi2, and NiSi. We have shown that finally, the Ti/Ti02 systems gives the best data retention performances even at high temperatures, up to 430K. . ]
CASULA, SILVIA. "Non-volatile organic memory devices: from design to applications". Doctoral thesis, Università degli Studi di Cagliari, 2015. http://hdl.handle.net/11584/266601.
Texto completo da fonteLivros sobre o assunto "Memory transistor"
Vagts, Christopher Bryan. A single-transistor memory cell and sense amplifier for a gallium arsenide dynamic random access memory. Monterey, Calif: Naval Postgraduate School, 1992.
Encontre o texto completo da fonteMaeda, Shigenobu. Teishōhi denryoku kōsoku MOSFET gijutsu: Takesshō shirikon TFT fukagata SRAM to SOI debaisu. Tōkyō: Sipec, 2002.
Encontre o texto completo da fonteVuillaume, D. Molecular electronics based on self-assembled monolayers. Editado por A. V. Narlikar e Y. Y. Fu. Oxford University Press, 2017. http://dx.doi.org/10.1093/oxfordhb/9780199533060.013.9.
Texto completo da fonteLaunay, Jean-Pierre, e Michel Verdaguer. The mastered electron: molecular electronics and spintronics, molecular machines. Oxford University Press, 2018. http://dx.doi.org/10.1093/oso/9780198814597.003.0005.
Texto completo da fonteForrest, Stephen R. Organic Electronics. Oxford University Press, 2020. http://dx.doi.org/10.1093/oso/9780198529729.001.0001.
Texto completo da fonteGang, Yung-jin. Ultra low voltage DRAM current sense amplifier with body bias techniques. 1998.
Encontre o texto completo da fonteHuster, Carl R. A parallel/vector Monte Carlo MESFET model for shared memory machines. 1992.
Encontre o texto completo da fonteLaunay, Jean-Pierre, e Michel Verdaguer. Electrons in Molecules. Oxford University Press, 2018. http://dx.doi.org/10.1093/oso/9780198814597.001.0001.
Texto completo da fonteAdvanced Technologies for Next Generation Integrated Circuits. Institution of Engineering & Technology, 2020.
Encontre o texto completo da fonteCapítulos de livros sobre o assunto "Memory transistor"
Julien, Levisse Alexandre Sébastien, Xifan Tang e Pierre-Emmanuel Gaillardon. "Innovative Memory Architectures Using Functionality Enhanced Devices". In Emerging Computing: From Devices to Systems, 47–83. Singapore: Springer Nature Singapore, 2022. http://dx.doi.org/10.1007/978-981-16-7487-7_3.
Texto completo da fonteLi, Mengyao, e Yating Zhang. "CHAPTER 17. Non-volatile Bipolar Transistor Memory". In Ambipolar Materials and Devices, 393–427. Cambridge: Royal Society of Chemistry, 2020. http://dx.doi.org/10.1039/9781788019279-00393.
Texto completo da fonteSugahara, Satoshi, Yusuke Shuto e Shuu'ichirou Yamamoto. "Spin-Transistor Technology for Spintronics/CMOS Hybrid Logic Circuits and Systems". In Nanomagnetic and Spintronic Devices for Energy-Efficient Memory and Computing, 65–90. Chichester, UK: John Wiley & Sons, Ltd, 2016. http://dx.doi.org/10.1002/9781118869239.ch3.
Texto completo da fonteLi, Yiming, Chih-Hong Hwang e Shao-Ming Yu. "Numerical Simulation of Static Noise Margin for a Six-Transistor Static Random Access Memory Cell with 32nm Fin-Typed Field Effect Transistors". In Computational Science – ICCS 2007, 227–34. Berlin, Heidelberg: Springer Berlin Heidelberg, 2007. http://dx.doi.org/10.1007/978-3-540-72590-9_33.
Texto completo da fonteYamazato, Masaaki, Alexander M. Grishin, Yukihiko Yamagata, Tomoaki Ikegami, Kenji Ebihara e Jagdish Narayan. "Superconducting YBa2Cu3O7-x—Ferroelectric PbZr0.52Ti0.48O3 Heterostructures for a Field Effect Transistor and a Nonvolatile Memory Device". In Advances in Superconductivity XI, 1305–8. Tokyo: Springer Japan, 1999. http://dx.doi.org/10.1007/978-4-431-66874-9_306.
Texto completo da fonteRawat, Bhawna, e Poornima Mittal. "Impact of High-Performance Transistor on Performance of Static Random Access Memory for Low-Voltage Applications". In Proceedings of Second International Conference on Computational Electronics for Wireless Communications, 369–77. Singapore: Springer Nature Singapore, 2023. http://dx.doi.org/10.1007/978-981-19-6661-3_33.
Texto completo da fonteBhowmik, Sonali, e Surajit Bari. "Design and Delay Analysis of Column Decoder Using NMOS Transistor at Nano Level for Semiconductor Memory Application". In Computational Advancement in Communication Circuits and Systems, 383–88. New Delhi: Springer India, 2015. http://dx.doi.org/10.1007/978-81-322-2274-3_42.
Texto completo da fonteAgrawal, Reeya, e Sangeeta Singh. "IoT-Based Designing of Single Bit Six-Transistor Static Random Access Memory Cell Architecture for Industrial Applications". In Internet of Things, 171–94. Boca Raton: Chapman and Hall/CRC, 2023. http://dx.doi.org/10.1201/9781003226888-13.
Texto completo da fonteMonazzah, Amir Mahdi Hosseini, Amir M. Rahmani, Antonio Miele e Nikil Dutt. "Exploiting Memory Resilience for Emerging Technologies: An Energy-Aware Resilience Exemplar for STT-RAM Memories". In Dependable Embedded Systems, 505–26. Cham: Springer International Publishing, 2020. http://dx.doi.org/10.1007/978-3-030-52017-5_21.
Texto completo da fonteSong, Young Suh, Youngjae Song, T. S. Arun Samuel, P. Vimala, Shubham Tayal, Ritam Dutta, Chandan Kumar Pandey, Abhishek Kumar Upadhyay, Ilho Myeong e Shiromani Balmukund Rahi. "TFET-based Memory Cell Design with Top-Down Approach". In Tunneling Field Effect Transistors, 223–34. Boca Raton: CRC Press, 2023. http://dx.doi.org/10.1201/9781003327035-12.
Texto completo da fonteTrabalhos de conferências sobre o assunto "Memory transistor"
Jung, Ilwoo, Byoungdeok Choi, Bonggu Sung, Daejung Kim, Ilgweon Kim, Hyoungsub Kim e Gyoyoung Jin. "Body Effect Measurement in DRAM Cell Transistor Using Memory Test System". In ISTFA 2016. ASM International, 2016. http://dx.doi.org/10.31399/asm.cp.istfa2016p0085.
Texto completo da fontePoghosyan, Armen R., Ruben K. Hovsepyan, Natella R. Aghamalyan, Yevgenia A. Kafadaryan, Hovhannes L. Ayvazyan e Hrachya G. Mnatsakanyan. "One-transistor memory element". In Photonic Fiber and Crystal Devices: Advances in Materials and Innovations in Device Applications XVI, editado por Shizhuo Yin e Ruyan Guo. SPIE, 2022. http://dx.doi.org/10.1117/12.2632105.
Texto completo da fontePal, Ashish, Krishna C. Saraswat, Aneesh Nainani, Zhiyuan Ye, Xinyu Bao e Errol Sanchez. "GaP source-drain vertical transistor on bulk silicon for 1-transistor DRAM application". In 2013 5th IEEE International Memory Workshop (IMW). IEEE, 2013. http://dx.doi.org/10.1109/imw.2013.6582132.
Texto completo da fonteFeng, Daohuan, Yi Jiang, Yunsong Qiu, Yuhong Zheng, Harry Kim, Jaewoo Kim, Jian Chu et al. "Vertical Channel Transistor (VCT) as Access Transistor for Future 4F2 DRAM Architecture". In 2023 IEEE International Memory Workshop (IMW). IEEE, 2023. http://dx.doi.org/10.1109/imw56887.2023.10145977.
Texto completo da fonteMartins, R., L. Pereira, P. Barquinha, N. Correia, G. Gonçalves, I. Ferreira, C. Dias e E. Fortunato. "Floating gate memory paper transistor". In OPTO, editado por Ferechteh H. Teherani, David C. Look, Cole W. Litton e David J. Rogers. SPIE, 2010. http://dx.doi.org/10.1117/12.841036.
Texto completo da fonteRuprecht, Michael W., Shengmin Wen e Rolf-P. Vollertsen. "Sample Preparation for Vertical Transistors in DRAM". In ISTFA 2002. ASM International, 2002. http://dx.doi.org/10.31399/asm.cp.istfa2002p0307.
Texto completo da fonteColvin, Jim B., e Anirban Roy. "Identification and Analysis of Parasitic Depletion Mode Leakage in a Memory Select Transistor". In ISTFA 2000. ASM International, 2000. http://dx.doi.org/10.31399/asm.cp.istfa2000p0247.
Texto completo da fonteQian, Kun, e Costas J. Spanos. "45nm transistor variability study for memory characterization". In SPIE Advanced Lithography, editado por Michael L. Rieger e Joerg Thiele. SPIE, 2010. http://dx.doi.org/10.1117/12.846704.
Texto completo da fonteSharif, Kazi Fatima, Riazul Islam, Satyendra N. Biswas e Voicu Groza. "4 Transistor and 2 memristor based memory". In 2017 IEEE Symposium on Computer Applications & Industrial Electronics (ISCAIE). IEEE, 2017. http://dx.doi.org/10.1109/iscaie.2017.8074946.
Texto completo da fonteGovli, Rishabh, Vivek Dixit e Bibhu Datta Sahoo. "1-Transistor-1-Memristor Multilevel Memory Cell". In 2018 IEEE 61st International Midwest Symposium on Circuits and Systems (MWSCAS). IEEE, 2018. http://dx.doi.org/10.1109/mwscas.2018.8624071.
Texto completo da fonte