Teses / dissertações sobre o tema "Memory security"
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Talhi, Chamseddine. "Memory-Constrained Security Enforcement". Doctoral thesis, Québec : Université Laval, 2007. http://www.theses.ulaval.ca/2007/24434/24434.pdf.
Texto completo da fonteCadar, Cristian. "Enhancing availability and security through boundless memory blocks". Thesis, Massachusetts Institute of Technology, 2004. http://hdl.handle.net/1721.1/33123.
Texto completo da fonteIncludes bibliographical references (leaves 49-52).
We present a new technique, boundless memory blocks, that automatically eliminates buffer overflow errors, enabling programs to continue to execute through memory errors without memory corruption. Buffer overflow vulnerabilities are caused by programming errors that allow an attacker to cause the program to write beyond the bounds of an allocated memory block to corrupt other data structures. The standard way to exploit a buffer overflow vulnerability involves a request that is too large for the buffer intended to hold it. The buffer overflow error causes the program to write part of the request beyond the bounds of the buffer, corrupting the address space of the program and causing the program to execute injected code contained in the request. Our boundless memory blocks compiler inserts checks that dynamically detect all out of bounds accesses. When it detects an out of bounds write, it stores the value away in a hash. Our compiler can then return the stored value as the result of an out of bounds read to that address. In the case of uninitialized addresses, our compiler simply returns a predefined value. We have acquired several widely used open source applications (Apache, Sendmail, Pine, Mutt, and Midnight Commander). With standard compilers, all of these applications are vulnerable to buffer overflow attacks as documented at security tracking web sites. Instead, our compiler enables the applications to execute successfully through buffer overflow attacks to continue to correctly service user requests without security vulnerabilities. We have also found that only one application contains uninitialized reads, which means that in most cases, the net effect of our compiler is to (conceptually) give each allocated memory block unbounded size and to eliminate out of bounds accesses as a programming error.
by Cristian Cadar.
M.Eng.
Chuang, Weihaw. "Maintaining safe memory for security, debugging, and multi-threading". Connect to a 24 p. preview or request complete full text in PDF format. Access restricted to UC campuses, 2006. http://wwwlib.umi.com/cr/ucsd/fullcit?p3223012.
Texto completo da fonteTitle from first page of PDF file (viewed September 21, 2006). Available via ProQuest Digital Dissertations. Vita. Includes bibliographical references (p. 164-172).
Sylve, Joseph T. "Android Memory Capture and Applications for Security and Privacy". ScholarWorks@UNO, 2011. http://scholarworks.uno.edu/td/1400.
Texto completo da fonteMarco, Gisbert Héctor. "Cyber-security protection techniques to mitigate memory errors exploitation". Doctoral thesis, Universitat Politècnica de València, 2016. http://hdl.handle.net/10251/57806.
Texto completo da fonte[ES] La creación de software supone uno de los retos más complejos para el ser humano ya que requiere un alto grado de abstracción. Aunque se ha avanzado mucho en las metodologías para la prevención de los fallos software, es patente que el software resultante dista mucho de ser confiable, y debemos asumir que el software que se produce no está libre de fallos. Dada la imposibilidad de diseñar o implementar sistemas libres de fallos, es necesario incorporar técnicas de mitigación de errores para mejorar la seguridad. La presente tesis realiza aportaciones en tres de las principales técnicas de mitigación de errores de corrupción de memoria: Stack Smashing Protector (SSP), Address Space Layout Randomisation (ASLR) y Automatic Software Diversification. SSP es una técnica de protección muy efectiva contra ataques de desbordamiento de buffer en pila, pero es sensible a ataques de fuerza bruta, en particular al peligroso ataque denominado byte-for-byte. Se ha propuesto una novedosa modificación del SSP, llamada RenewSSP, la cual elimina los ataques de fuerza bruta. Puede ser usada de manera completamente transparente con los programas existentes sin introducir sobrecarga. El RenewSSP es especialmente beneficioso en dos áreas de aplicación: Servidores de red (probado en Apache) y lanzadores de aplicaciones eficientes (probado en Android). ASLR es un concepto genérico, del cual hay multitud de diseños e implementaciones. Se han analizado las dos implementaciones más relevantes de Linux (Vanilla Linux y PaX patch), encontrándose en ambas tanto debilidades como elementos mejorables. Teniendo en cuenta las mejoras tecnológicas en el soporte a la ejecución (compiladores y librerías), se ha propuesto un nuevo diseño del ASLR, llamado ASLR-NG, el cual: maximiza la entropía, soluciona el problema de la fragmentación y elimina las debilidades encontradas. Al igual que la solución propuesta para el SSP, la nueva propuesta de ASLR es transparente para las aplicaciones y compatible a nivel binario sin introducir sobrecarga. ASLR-NG ha sido implementado como un parche del núcleo de Linux para la versión 4.1. La diversificación software es una técnica que cubre una amplia gama de fallos, incluidos los errores de memoria. La principal dificultad para aplicar esta técnica radica en la generación de las "variantes", que son programas que tienen un comportamiento idéntico entre ellos ante entradas normales, pero tienen un comportamiento diferenciado en presencia de entradas anormales. Se ha propuesto una novedosa forma de generar variantes de forma automática a partir de un mismo código fuente, empleando la emulación de sistemas. Una de las máximas de esta investigación ha sido la aplicabilidad de los resultados, por lo que se ha hecho especial hincapié en el desarrollo de prototipos sobre sistemas reales a la par que se llevaba a cabo el estudio teórico. Como resultado, las propuestas de esta tesis son directamente aplicables a sistemas reales, algunas de ellas ya están siendo explotadas en la práctica.
[CAT] La creació de programari suposa un dels reptes més complexos per al ser humà ja que requerix un alt grau d'abstracció. Encara que s'ha avançat molt en les metodologies per a la prevenció de les fallades de programari, és palès que el programari resultant dista molt de ser confiable, i hem d'assumir que el programari que es produïx no està lliure de fallades. Donada la impossibilitat de dissenyar o implementar sistemes lliures de fallades, és necessari incorporar tècniques de mitigació d'errors per a millorar la seguretat. La present tesi realitza aportacions en tres de les principals tècniques de mitigació d'errors de corrupció de memòria: Stack Smashing Protector (SSP), Address Space Layout Randomisation (ASLR) i Automatic Software Diversification. SSP és una tècnica de protecció molt efectiva contra atacs de desbordament de buffer en pila, però és sensible a atacs de força bruta, en particular al perillós atac denominat byte-for-byte. S'ha proposat una nova modificació del SSP, RenewSSP, la qual elimina els atacs de força bruta. Pot ser usada de manera completament transparent amb els programes existents sense introduir sobrecàrrega. El RenewSSP és especialment beneficiós en dos àrees d'aplicació: servidors de xarxa (provat en Apache) i llançadors d'aplicacions eficients (provat en Android). ASLR és un concepte genèric, del qual hi ha multitud de dissenys i implementacions. S'han analitzat les dos implementacions més rellevants de Linux (Vanilla Linux i PaX patch), trobant-se en ambdues tant debilitats com elements millorables. Tenint en compte les millores tecnològiques en el suport a l'execució (compiladors i llibreries), s'ha proposat un nou disseny de l'ASLR: ASLR-NG, el qual, maximitza l'entropia, soluciona el problema de la fragmentació i elimina les debilitats trobades. Igual que la solució proposada per al SSP, la nova proposta d'ASLR és transparent per a les aplicacions i compatible a nivell binari sense introduir sobrecàrrega. ASLR-NG ha sigut implementat com un pedaç del nucli de Linux per a la versió 4.1. La diversificació de programari és una tècnica que cobrix una àmplia gamma de fa\-llades, inclosos els errors de memòria. La principal dificultat per a aplicar esta tècnica radica en la generació de les "variants", que són programes que tenen un comportament idèntic entre ells davant d'entrades normals, però tenen un comportament diferenciat en presència d'entrades anormals. S'ha proposat una nova forma de generar variants de forma automàtica a partir d'un mateix codi font, emprant l'emulació de sistemes. Una de les màximes d'esta investigació ha sigut l'aplicabilitat dels resultats, per la qual cosa s'ha fet especial insistència en el desenrotllament de prototips sobre sistemes reals al mateix temps que es duia a terme l'estudi teòric. Com a resultat, les propostes d'esta tesi són directament aplicables a sistemes reals, algunes d'elles ja estan sent explotades en la pràctica.
Marco Gisbert, H. (2015). Cyber-security protection techniques to mitigate memory errors exploitation [Tesis doctoral no publicada]. Universitat Politècnica de València. https://doi.org/10.4995/Thesis/10251/57806
TESIS
Govindaraj, Rekha. "Emerging Non-Volatile Memory Technologies for Computing and Security". Scholar Commons, 2018. https://scholarcommons.usf.edu/etd/7674.
Texto completo da fonteVeca, Matthew. "Extracting Windows event logs using memory forensics". ScholarWorks@UNO, 2015. http://scholarworks.uno.edu/td/2119.
Texto completo da fonteBabecki, Christopher. "A Memory-Array Centric Reconfigurable Hardware Accelerator for Security Applications". Case Western Reserve University School of Graduate Studies / OhioLINK, 2015. http://rave.ohiolink.edu/etdc/view?acc_num=case1427381331.
Texto completo da fontePettersson, Stefan. "Visualizing Endpoint Security Technologies using Attack Trees". Thesis, Linköping University, Department of Computer and Information Science, 2008. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-15509.
Texto completo da fonteSoftware vulnerabilities in programs and malware deployments have been increasing almost every year since we started measuring them. Information about how to program securely, how malware shall be avoided and technological countermeasures for this are more available than ever. Still, the trend seems to favor the attacker. This thesis tries to visualize the effects of a selection of technological countermeasures that have been proposed by researchers. These countermeasures: non-executable memory, address randomization, system call interception and file integrity monitoring are described along with the attacks they are designed to defend against. The coverage of each countermeasure is then visualized with the help of attack trees. Attack trees are normally used for describing how systems can be attacked but here they instead serve the purpose of showing where in an attack a countermeasure takes effect. Using attack trees for this highlights a couple of important aspects of a security mechanism, such as how early in an attack it is effective and which variants of an attack it potentially defends against. This is done by the use of what we call defensive codes that describe how a defense mechanism counters a sub-goal in an attack. Unfortunately the whole process is not well formalized and depends on many uncertain factors.
Payne, Bryan D. "Improving host-based computer security using secure active monitoring and memory analysis". Diss., Georgia Institute of Technology, 2010. http://hdl.handle.net/1853/34852.
Texto completo da fonteYan, Chenyu. "Architectural support for improving security and performance of memory sub-systems". Diss., Atlanta, Ga. : Georgia Institute of Technology, 2008. http://hdl.handle.net/1853/26663.
Texto completo da fonteCommittee Chair: Milos Prvulovic; Committee Member: Gabriel Loh; Committee Member: Hyesoon Kim; Committee Member: Umakishore Ramachandran; Committee Member: Yan Solihin. Part of the SMARTech Electronic Thesis and Dissertation Collection.
Vaslin, Romain. "Hardware core for off-chip memory security management in embedded system". Lorient, 2008. http://www.theses.fr/2008LORIS119.
Texto completo da fonteWe offer a secure hardware architecture for system boot up, secure software execution and on field update. A new scheme is presented to guarantee dat confidentiality and integrity for off-chip memories. The architecture capabilities are extended to support on the fly security level management of data. The goal is to minimize the overhead due to security like logic area, performance, memory footprint and power consumption for the architecture. After careful evaluation through real time applications execution with this secure architecture, the next step was to provide an end to end solution. Toward th solution, a secure boot up mechanism is proposed in order to securely start applications from a flash memory. More techniques are also introduced to allow on field software update for later secure execution with the architecture. A complete set ofresults has been generated in order to underline the fact that the proposed solution matches with the current needs and constraints of embedded systems. For the first time the security cost in area, performance, memory and power has been evaluated for embedded systems with an end to end solution
Seong, Nak Hee. "A reliable, secure phase-change memory as a main memory". Diss., Georgia Institute of Technology, 2012. http://hdl.handle.net/1853/50123.
Texto completo da fonteAndrade, Ewerton Rodrigues. "Lyra2: password hashing scheme with improved security against time-memory trade-offs". Universidade de São Paulo, 2016. http://www.teses.usp.br/teses/disponiveis/3/3141/tde-26082016-150620/.
Texto completo da fontePara proteger-se de ataques de força bruta, sistemas modernos de autenticação baseados em senhas geralmente empregam algum Esquema de Hash de Senhas (Password Hashing Scheme - PHS). Basicamente, um PHS é um algoritmo criptográfico que gera uma sequência de bits pseudo-aleatórios a partir de uma senha provida pelo usuário, permitindo a este último configurar o custo computacional envolvido no processo e, assim, potencialmente elevar os custos de atacantes testando múltiplas senhas em paralelo. Esquemas tradicionais utilizados para esse propósito são o PBKDF2 e bcrypt, por exemplo, que incluem um parâmetro configurável que controla o número de iterações realizadas pelo algoritmo, permitindo ajustar-se o seu tempo total de processamento. Já os algoritmos scrypt e Lyra, mais recentes, permitem que usuários não apenas controlem o tempo de processamento, mas também a quantidade de memória necessária para testar uma senha. Apesar desses avanços, ainda há um interesse considerável da comunidade de pesquisa no desenvolvimento e avaliação de novas (e melhores) alternativas. De fato, tal interesse levou recentemente à criação de uma competição com esta finalidade específica, a Password Hashing Competition (PHC). Neste contexto, o objetivo do presente trabalho é propor uma alternativa superior aos PHS existentes. Especificamente, tem-se como alvo melhorar o algoritmo Lyra, um PHS baseado em esponjas criptográficas cujo projeto contou com a participação dos autores do presente trabalho. O algoritmo resultante, denominado Lyra2, preserva a segurança, eficiência e flexibilidade do Lyra, incluindo a habilidade de configurar do uso de memória e tempo de processamento do algoritmo, e também a capacidade de prover um uso de memória superior ao do scrypt com um tempo de processamento similar. Entretanto, ele traz importantes melhorias quando comparado ao seu predecessor: (1) permite um maior nível de segurança contra estratégias de ataque envolvendo trade-offs entre tempo de processamento e memória; (2) inclui a possibilidade de elevar os custos envolvidos na construção de plataformas de hardware dedicado para ataques contra o algoritmo; (3) e provê um equilíbrio entre resistância contra ataques de canal colateral (\"side-channel\") e ataques que se baseiam no uso de dispositivos de memória mais baratos (e, portanto, mais lentos) do que os utilizados em computadores controlados por usuários legítimos. Além da descrição detalhada do projeto do algoritmo, o presente trabalho inclui também uma análise detalhada de sua segurança e de seu desempenho em diferentes plataformas. Cabe notar que o Lyra2, conforme aqui descrito, recebeu uma menção de reconhecimento especial ao final da competição PHC previamente mencionada.
Trikalinou, Anna. "AMYNA: A Security Generator and Performance Estimator Framework Against Memory-Based Attacks". Wright State University / OhioLINK, 2014. http://rave.ohiolink.edu/etdc/view?acc_num=wright1418998019.
Texto completo da fonteKiriansky, Vladimir L. (Vladimir Lubenov) 1979. "Improving performance and security of indirect memory references on speculative execution machines". Thesis, Massachusetts Institute of Technology, 2019. https://hdl.handle.net/1721.1/122556.
Texto completo da fonteCataloged from PDF version of thesis.
Includes bibliographical references (pages 123-139).
Indirect memory references hobble efficient and secure execution on current processor architectures. Traditional hardware techniques such as caches and speculative execution are ineffective on demanding workloads, such as in-memory databases, machine learning, and graph analytics. While terabytes of DRAM are now available in public cloud machines, indirect memory references in large working sets often incur the full penalty of a random DRAM access. Furthermore, caches and speculative execution enable the recently discovered Spectre family of side-channel attacks, which allow untrusted neighbors in a public cloud to steal secrets. In this thesis, we introduce complementary software and hardware techniques to improve the performance of caches and speculative execution, and to block the largest attack class with low overhead. MILK is our C++ extension to improve data cache locality.
Milk's programming model preserves parallel program semantics and maps well to the Bulk-Synchronous Parallel (BSP) theoretical model. Within a BSP superstep, which may encompass billions of memory references, Milk captures the temporal and spatial locality of ideal infinite caches on real hardware and provides up to 4x speedup. CIMPLE is our domain specific language (DSL) to improve the effectiveness of speculative execution in discovering instruction level parallelism and memory level parallelism. Improving memory parallelism on current CPUs allows up to ten memory references in parallel to reduce the effective DRAM latency. Speculative execution is constrained by branch predictor effectiveness and can only uncover independent accesses within the hardware limits of instruction windows (up to 100 instructions). With Cimple, interleaved co-routines expose instruction and memory level parallelism close to ideal hardware with unlimited instruction windows and perfect predictors.
On in-memory database index data structures, Cimple achieves up to 6x speedup. DAWG is our secure cache architecture that prevents leaks via measuring the cache effects of speculative indirect memory references. Unlike performance isolation mechanisms such as Intel's Cache Allocation Technology (CAT), DAWG blocks both speculative and non-speculative side-channels by isolating cache protection domains. DAWG incurs no overhead over CAT for isolation in public clouds. DAWG also enables OS isolation with efficient sharing and communication via caches, e.g., in system calls.
by Vladimir Kiriansky.
Ph. D.
Ph.D. Massachusetts Institute of Technology, Department of Electrical Engineering and Computer Science
Peters, Timothy M. "DEFY: A Deniable File System for Flash Memory". DigitalCommons@CalPoly, 2014. https://digitalcommons.calpoly.edu/theses/1230.
Texto completo da fonteCase, Andrew. "Detecting Objective-C Malware through Memory Forensics". ScholarWorks@UNO, 2016. http://scholarworks.uno.edu/td/2132.
Texto completo da fonteChaulagain, Dewan. "Hybrid Analysis of Android Applications for Security Vetting". Bowling Green State University / OhioLINK, 2019. http://rave.ohiolink.edu/etdc/view?acc_num=bgsu1555608766287613.
Texto completo da fonteNemati, Hamed. "Secure System Virtualization : End-to-End Verification of Memory Isolation". Doctoral thesis, KTH, Teoretisk datalogi, TCS, 2017. http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-213030.
Texto completo da fonteQC 20170831
PROSPER
HASPOC
Priyanimal, Karunanayake Dinidu. "GEOPOLITICS OF FORGERY: LITERATURE, CULTURE AND MEMORY OF THE POSTCOLONIAL SOUTH ASIAN SECURITY STATE". Miami University / OhioLINK, 2019. http://rave.ohiolink.edu/etdc/view?acc_num=miami156354614875673.
Texto completo da fonteYoung, Vinson. "Hardware-assisted security: bloom cache – scalable low-overhead control flow integrity checking". Thesis, Georgia Institute of Technology, 2014. http://hdl.handle.net/1853/53994.
Texto completo da fonteShi, Weidong. "Architectural Support for Protecting Memory Integrity and Confidentiality". Diss., Georgia Institute of Technology, 2006. http://hdl.handle.net/1853/11460.
Texto completo da fonteKong, Jingfei. "ARCHITECTURAL SUPPORT FOR IMPROVING COMPUTER SECURITY". Doctoral diss., University of Central Florida, 2010. http://digital.library.ucf.edu/cdm/ref/collection/ETD/id/2610.
Texto completo da fontePh.D.
School of Electrical Engineering and Computer Science
Engineering and Computer Science
Computer Science PhD
McConnell, William Charles. "Visualizing Memory Utilization for the Purpose of Vulnerability Analysis". Thesis, Virginia Tech, 2008. http://hdl.handle.net/10919/33382.
Texto completo da fonteMaster of Science
Morrison, Matthew Arthur. "Theory, Synthesis, and Application of Adiabatic and Reversible Logic Circuits For Security Applications". Scholar Commons, 2013. https://scholarcommons.usf.edu/etd/5082.
Texto completo da fonteSylve, Joseph T. "Towards Real-Time Volatile Memory Forensics: Frameworks, Methods, and Analysis". ScholarWorks@UNO, 2017. http://scholarworks.uno.edu/td/2359.
Texto completo da fonteChapman, Erin Elizabeth. "A Survey and Analysis of Solutions to the Oblivious Memory Access Problem". PDXScholar, 2012. https://pdxscholar.library.pdx.edu/open_access_etds/891.
Texto completo da fonteBolignano, Pauline. "Formal models and verification of memory management in a hypervisor". Thesis, Rennes 1, 2017. http://www.theses.fr/2017REN1S026/document.
Texto completo da fonteA hypervisor is a software which virtualizes hardware resources, allowing several guest operating systems to run simultaneously on the same machine. Since the hypervisor manages the access to resources, a bug can be critical for the guest Oses. In this thesis, we focus on memory isolation properties of a type 1 hypervisor, which virtualizes memory using Shadow Page Tables. More precisely, we present a low-level and a high-level model of the hypervisor, and we formally prove that guest OSes cannot access or tamper with private data of other guests, unless they have the authorization to do so. We use the language and the proof assistant developed by Prove & Run. There are many optimizations in the low-level model, which makes the data structures and algorithms complexes. It is therefore difficult to reason on such a model. To circumvent this issue, we design an abstract model in which it is easier to reason. We prove properties on the abstract model, and we prove its correspondence with the low-level model, in such a way that properties proved on the abstract model also hold for the low-level model. The correspondence proof is valid only for low-level states which respect some properties. We prove that these properties are invariants of the low-level system. The proof can be divided into three parts : the proof of invariants preservation on the low-level, the proof of correspondence between abstract and low-level models, and proof of the security properties on the abstract level
Larmuseau, Adriaan. "Protecting Functional Programs From Low-Level Attackers". Doctoral thesis, Uppsala universitet, Avdelningen för datalogi, 2016. http://urn.kb.se/resolve?urn=urn:nbn:se:uu:diva-281318.
Texto completo da fonteSvetlana, Jakšić. "Types for Access and Memory Control". Phd thesis, Univerzitet u Novom Sadu, Fakultet tehničkih nauka u Novom Sadu, 2016. https://www.cris.uns.ac.rs/record.jsf?recordId=101762&source=NDLTD&language=en.
Texto completo da fonteУ тези су разматрана три проблема. Први је администрација и контролаправа приступа података у рачунарској мрежи са XML подацима, санагласком на безбедости посматраних података. Други је администрација икотрола права приступа подацима у рачунарској мрежи са RDF подацима,са нагласком на приватности посматраних података. Трећи је превенцијагрешака и цурења меморије, као и грешака у комуникацији генерисанимпрограмима написаних на језику Sing# у којима су присутни изузеци. За сватри проблема биће предложени формални модели и одговарајући типскисистеми помоћу којих се показује одсуство неповољних понашања тј.грешака у мрежама односно програмима.
U tezi su razmatrana tri problema. Prvi je administracija i kontrolaprava pristupa podataka u računarskoj mreži sa XML podacima, sanaglaskom na bezbedosti posmatranih podataka. Drugi je administracija ikotrola prava pristupa podacima u računarskoj mreži sa RDF podacima,sa naglaskom na privatnosti posmatranih podataka. Treći je prevencijagrešaka i curenja memorije, kao i grešaka u komunikaciji generisanimprogramima napisanih na jeziku Sing# u kojima su prisutni izuzeci. Za svatri problema biće predloženi formalni modeli i odgovarajući tipskisistemi pomoću kojih se pokazuje odsustvo nepovoljnih ponašanja tj.grešaka u mrežama odnosno programima.
Tardif, Florent. "Practical considerations on cryptanalytic time-memory trade-offs". Thesis, Rennes 1, 2019. http://www.theses.fr/2019REN1S118.
Texto completo da fonteA cryptanalytic time-memory trade-off (TMTO) is a technique that aims to reduce the time needed to perform a set of cryptanalysis attacks, such as inverting a one-way function. Such an inversion constitutes one of the main applications of TMTOs, which is password cracking. The technique relies on a large-scale pre-computation which outputs tables that allow to significantly speed up the attack's exhaustive search. The more memory is used by a TMTO, the faster the attack can be. In practice, the amount of memory available is often the limiting factor, so numerous approaches have been proposed to fit large tables in a restricted amount of memory. In this thesis, we focus on the rainbow tables variant, the most widely spread version of time-memory trade-offs. When the considered cryptographic problem is overwhelmingly sized, using an external memory is eventually needed. We analyse the relevance of using an external memory instead of RAM, and we state that it is fully suited for practical cases, which are identified. We then introduce a new technique, based on minimal perfect hash functions, whose storage complexity is better than any previous optimisation. Finally, we analyse and compare existing TMTO approaches as well as their combinations, along with our newly introduced MPHF rainbow technique. We are then able to provide a set of practical recommendations on how to configure the implementation of a TMTO in an optimal way
Oliveri, Andrea. "A Zero-Knowledge Approach to Memory Forensics". Electronic Thesis or Diss., Sorbonne université, 2023. http://www.theses.fr/2023SORUS312.
Texto completo da fonteThe rapid increase of embedded devices and IoT objects is leading to a multiplication of operating systems and processor architectures, which are generally not supported by current forensic tools and require considerable effort to adapt. To overcome this problem, we introduce the concept of zero-knowledge memory forensics: performing a memory forensic analysis without any knowledge of the underlying operating system. Assuming that we have performed a memory dump of the unknown operating system, using only information derived from the machine's hardware configuration, we claim that it is possible to reconstruct the kernel address space independently of the operating system. From these, it is possible to reconstruct kernel data structures in memory using only their topology
Rammal, Darine. "Memory safety for synchronous reactive programming". Electronic Thesis or Diss., Orléans, 2024. http://www.theses.fr/2024ORLE1002.
Texto completo da fonteSynchronous Reactive Languages are an excellent choice for IoT programming due to their clear system-environment interaction semantics. However, when it comes to safety- critial or resource-constrained systems, recent proposals like Fairthreads or ReactiveML face a well-known issue. Fairthreads' manual memory management can lead to errors, while ReactiveML's garbage collection ensures memory safety but introduces execution overhead. This thesis aims to address the memory safety issue by developing a reactive programming language specifically designed for real-time systems, incorporating cooperative threads and synchronous execution. Drawing from the robust type system of the Rust programming language, we propose a Rust-like type system for a kernel reactive programming language named MSSL. MSSL features a cooperative threading model and facilitates mutable data sharing between threads while preserving type and borrowing safety. To achieve this, we introduce a novel abstraction called Trc (Thread Reference Counting), which combines the ownership safety of Rust references with the reference counting mechanism of Rust smart pointers. Then, we present the semantics and type system of MSSL to demonstrate its capabilities in maintaining type safety, borrowing safety, and concurrency safety. Furthermore, we extend MSSL by introducing reactive extensions, incorporating the concept of signals that offer powerful, flexible, and reliable means of communication. Finally, we provide a Java implementation of the complete MSSL set, based on the semantic and typing rules of its type system
Sansurooah, Krishnun. "A forensics framework and method in the acquisition and extraction of data from NAND Flash memory storage chip". Thesis, Edith Cowan University, Research Online, Perth, Western Australia, 2015. https://ro.ecu.edu.au/theses/1725.
Texto completo da fonteArslan, Aydin Ulku. "The Effects Of Coherence Of The Image Used In The Graphical Password Scheme In Terms Of Usability And Security". Master's thesis, METU, 2012. http://etd.lib.metu.edu.tr/upload/12614612/index.pdf.
Texto completo da fonteStacy (1973) reported that the objects in a coherent image were recognized and identified more efficiently and quickly than the objects in a jumbled image in which the jumbled image was created by dividing the coherent image into sections and changing the position of the sections without rotating them. The study was designed to experimentally examine the differences in usability and security of the graphical password scheme by manipulating the coherence of the displayed image. Sixty-three volunteers participated in the main experiment. The participants were divided into groups according to the type of image they were presented in the password creation (either coherent-image or jumbled-image) task. Each participant created a graphical password and three days after the first session (i.e., second session) s/he tried to remember it in order to authenticate to the system. The results revealed that in the proposed graphical password scheme, using coherent image has more advantages over jumbled image in terms of usability and security.
Ruhault, Sylvain. "Security analysis for pseudo-random number generators". Thesis, Paris, Ecole normale supérieure, 2015. http://www.theses.fr/2015ENSU0014/document.
Texto completo da fonteIn cryptography, randomness plays an important role in multiple applications. It is required in fundamental tasks such as key generation and initialization vectors generation or in key exchange. The security of these cryptographic algorithms and protocols relies on a source of unbiased and uniform distributed random bits. Cryptography practitioners usually assume that parties have access to perfect randomness. However, quite often this assumption is not realizable in practice and random bits are generated by a Pseudo-Random Number Generator. When this is done, the security of the scheme depends of course in a crucial way on the quality of the (pseudo-)randomness generated. However, only few generators used in practice have been analyzed and therefore practitioners and end users cannot easily assess their real security level. We provide in this thesis security models for the assessment of pseudo-random number generators and we propose secure constructions. In particular, we propose a new definition of robustness and we extend it to capture memory attacks and side-channel attacks. On a practical side, we provide a security assessment of generators used in practice, embedded in system kernel (Linux /dev/random) and cryptographic libraries (OpenSSL and Java SecureRandom), and we prove that these generators contain potential vulnerabilities
Sharma, Niti. "Impact of Increased Cache Misses on Runtime Performance of MPX-enabled Programs". Thesis, Virginia Tech, 2019. http://hdl.handle.net/10919/89914.
Texto completo da fonteMaster of Science
Low level programming languages like C and C++ are primary choices to write low-level systems software such as operating systems, virtual machines, embedded software, and performance-critical applications. But these languages are considered as unsafe and prone to memory safety errors. Intel introduced a new technique- Memory Protection Extensions(MPX) to protect against these memory errors. But prior research found that applications supported with MPX have increased runtimes(slowdowns). In our research, we analyze these slowdowns for different input sizes(medium and large) in 15 benchmark applications. Based on the input sizes, the average slowdowns range from 140% to 144%. We then examine if there is a correlation between increase in cache misses under MPX and the slowdowns. A hardware cache is a component that stores data so that future requests for that data can be served faster. Hence, cache miss is a state where the data requested for processing by a component or application is not found in the cache. Whenever a cache miss happen, the processor waits for the data to be fetched from the next cache level or from main memory before it can continue to execute. This wait influences the runtime performance of the application. Our evaluations find that 10 out of 15 applications which have increased runtimes, also have increase in cache misses. This shows a positive correlation between these two parameters. Along with that, we also found that increase in instruction size in MPX protected applications also has a direct correlation with the runtime degradation. We also quantify these relationships with a statistical measure called correlation coefficient.
Pan, Xiang. "Designing Future Low-Power and Secure Processors with Non-Volatile Memory". The Ohio State University, 2017. http://rave.ohiolink.edu/etdc/view?acc_num=osu1492631536670669.
Texto completo da fonteBozzio, Mathieu. "Security and implementation of advanced quantum cryptography : quantum money and quantum weak coin flipping". Electronic Thesis or Diss., Université Paris-Saclay (ComUE), 2019. http://www.theses.fr/2019SACLT045.
Texto completo da fonteHarnessing the laws of quantum theory can drastically boost the security of modern communication networks, from public key encryption to electronic voting and online banking. In this thesis, we bridge the gap between theory and experiment regarding two quantum-cryptographic tasks: quantum money and quantum weak coin flipping. Quantum money exploits the no-cloning property of quantum physics to generate unforgeable tokens, banknotes, and credit cards. We provide the first proof-of-principle implementation of this task, using photonic systems at telecom wavelengths. We then develop a practical security proof for quantum credit card schemes, in which the bank can remotely verify a card even in the presence of a malicious payment terminal. We finally propose a setup for secure quantum storage of the credit card, using electromagnetically-induced transparency in a cloud of cold cesium atoms. Quantum weak coin flipping is a fundamental cryptographic primitive, which helps construct more complex tasks such as bit commitment and multiparty computation. It allows two distant parties to flip a coin when they both desire opposite outcomes. Using quantum entanglement then prevents any party from biasing the outcome of the flip beyond a certain probability. We propose the first implementation for quantum weak coin flipping, which requires a single photon and linear optics only. We provide the complete security analysis in the presence of noise and losses, and show that the protocol is implementable on the scale of a small city with current technology. We finally propose a linear-optical extension of the protocol to lower the coin bias
Nimgaonkar, Satyajeet. "Secure and Energy Efficient Execution Frameworks Using Virtualization and Light-weight Cryptographic Components". Thesis, University of North Texas, 2014. https://digital.library.unt.edu/ark:/67531/metadc699986/.
Texto completo da fonteBennett, Joshua. "The memory of the Holocaust as a point of state ontological (in)security : A comparative discursive analysis of the United Kingdom and Poland". Thesis, Uppsala universitet, Hugo Valentin-centrum, 2020. http://urn.kb.se/resolve?urn=urn:nbn:se:uu:diva-413283.
Texto completo da fonteBhatt, Manish. "Leveraging Relocations in ELF-binaries for Linux Kernel Version Identification". ScholarWorks@UNO, 2018. https://scholarworks.uno.edu/td/2528.
Texto completo da fonteThames, John Lane. "Advancing cyber security with a semantic path merger packet classification algorithm". Diss., Georgia Institute of Technology, 2012. http://hdl.handle.net/1853/45872.
Texto completo da fonteThakur, Neha S. "Forensic Analysis of WhatsApp on Android Smartphones". ScholarWorks@UNO, 2013. http://scholarworks.uno.edu/td/1706.
Texto completo da fonteOuattara, Frédéric. "Primitives de sécurité à base de mémoires magnétiques". Thesis, Montpellier, 2020. http://www.theses.fr/2020MONTS072.
Texto completo da fonteMagnetic memories (MRAM) are one of the emerging non-volatile memory technologies that have experienced rapid development over the past decade. One of the advantages of this technology lies in the varied fields of application in which it can be used. In addition to its primary function of storing information, MRAM is nowadays used in applications such as sensors, RF receivers and hardware security. In this thesis, we are interested in the use of MRAMs in the design of elementary hardware security primitives. Initially, an exploration in the design of TRNG (True Random Number Generator) based on STT-MRAM (Spin Transfert Torque MRAM) type memories was carried out with the aim of producing a demonstrator and proving its effectiveness for secure applications. Random extraction methods in STT and TAS (Thermally Assisted Switching) memories are presented. We have thus evaluated these magnetic memories within the framework of TRNGs but also for the generation of PUFs (Physically Unclonable Functions) on physical devices
Almeida, Leonardo de Campos. "Lyra: uma função de derivação de chaves com custos de memória e processamento configuráveis". Universidade de São Paulo, 2016. http://www.teses.usp.br/teses/disponiveis/3/3141/tde-29062016-085500/.
Texto completo da fonteThis document presents Lyra, a password-based key derivation scheme based on cryptographic sponges. Lyra was designed to be strictly sequential, providing strong security even against attackers that use multiple processing cores, such as FPGAs or GPUs. At the same time, it is very simple to implement in software and allows legitimate users to tune its memory and processing costs according to the desired level of security. We compare Lyra with scrypt, showing how this proposal provides a higher security level and overcomes limitations of scrypt. If the attacker wishes to perform a low-memory attack against the algorithm, the processing cost grwos expontetialy, while in scrypt, this growth is only quadratic. In addition, for an identical processing time, Lyra allows for a higher memory usage than its counterparts, further increasing the cost of brute force attacks.
Buret, Pierrick. "Sécurité temps réel dans les systèmes embarqués critiques". Thesis, Limoges, 2015. http://www.theses.fr/2015LIMO0140/document.
Texto completo da fonteSatellites are real-time embedded systems and will be used more and more in the world. Become essential for the geo-location, meteorology or communications across the planet, these systems are increasingly in demand. Due to the influx of requests, the designers of these products are designing a more and more complex hardware and software part. Thanks to the evolution of terrestrial equipment, the aero-space field is turning to new technologies such as caches, multi-core, and hypervisor. The integration of these new technologies bring new technical challenges. In effect, it is necessary to improve the performance of these systems by reducing the cost of manufacturing and the production time. One of the major advantages of these technologies is the possibility of reducing the overall number of satellites in space while increasing the number of operators. Multiple clients softwares may be together today in a same satellite. The ability to integrate multiple customers on the same satellite, with the increasing complexity of the system, makes a number of malicious acts possible. These acts were once considered as hypothetical. Become a priority today, the study of the vulnerability of such systems become major. In this paper, we present first work a quick exploration of the field of malicious acts on onboard system and more specifically those carried out on satellite system. Once the risk presentation we will develop some particular points, such as the problematic real-time. In this thesis we are particularly interested in the security of space hypervisors. We will develop precisely 2 lines of research. The first axis is focused on the development of production technics and implementing a control system of a satellite temporal characteristics. The objective is to adapt an existing system to the constraints of the new highly complex systems. We confront the difficulty of measuring the temporal characteristics running on a satellite system. For this we use an optimization method called dynamic analysis and genetic algorithm. Based on trends, it can automatically search for the worst execution time of a given function. The second axis improves the technical knowledge on a satellite in operation and enables decision making in case of malicious act. We propose specifically a physical solution to detect anomalies in the management of internal memory to the satellite. Indeed, memory is an essential component of system operation, and these common properties between all clients makes them particularly vulnerable to malicious acts. Also, know the number of memory access enables better scheduling and better predictability of a real time system. Our component allows the detection and interpretation of a potential attack or dependability problem. The work put in evidence the complementarity of the two proposed work. Indeed, the measure of the number of memory access that can be measured via a genetic algorithm whose shape is similar to the program seeking the worst execution time. So we can expand our work of the first part with the second
Ouaarab, Salaheddine. "Protection du contenu des mémoires externes dans les systèmes embarqués, aspect matériel". Thesis, Paris, ENST, 2016. http://www.theses.fr/2016ENST0046/document.
Texto completo da fonteDuring the past few years, computer systems (Cloud Computing, embedded systems...) have become ubiquitous. Most of these systems use unreliable or untrusted storage (flash, RAM...)to store code or data. The confidentiality and integrity of these data can be threaten by hardware (spying on the communication bus between the processing component and the storage component) or software attacks. These attacks can disclose sensitive information to the adversary or disturb the behavior of the system. In this thesis, in the context of embedded systems, we focused on the attacks that threaten the confidentiality and integrity of data that are transmittedover the memory bus or that are stored inside the memory. Several primitives used to protect the confidentiality and integrity of data have been proposed in the literature, including Merkle trees, a data structure that can protect the integrity of data including against replay attacks. However, these trees have a large impact on the performances and the memory footprint of the system. In this thesis, we propose a solution based on variants of Merkle trees (hollow trees) and a modified cache management mechanism to greatly reduce the impact of the verification of the integrity. The performances of this solution have been evaluated both theoretically and in practice using simulations. In addition, a proof a security equivalence with regular Merkle treesis given. Finally, this solution has been implemented in the SecBus architecture which aims at protecting the integrity and confidentiality of the content of external memories in an embedded system. A prototype of this architecture has been developed and the results of its evaluation are given
Ouaarab, Salaheddine. "Protection du contenu des mémoires externes dans les systèmes embarqués, aspect matériel". Electronic Thesis or Diss., Paris, ENST, 2016. http://www.theses.fr/2016ENST0046.
Texto completo da fonteDuring the past few years, computer systems (Cloud Computing, embedded systems...) have become ubiquitous. Most of these systems use unreliable or untrusted storage (flash, RAM...)to store code or data. The confidentiality and integrity of these data can be threaten by hardware (spying on the communication bus between the processing component and the storage component) or software attacks. These attacks can disclose sensitive information to the adversary or disturb the behavior of the system. In this thesis, in the context of embedded systems, we focused on the attacks that threaten the confidentiality and integrity of data that are transmittedover the memory bus or that are stored inside the memory. Several primitives used to protect the confidentiality and integrity of data have been proposed in the literature, including Merkle trees, a data structure that can protect the integrity of data including against replay attacks. However, these trees have a large impact on the performances and the memory footprint of the system. In this thesis, we propose a solution based on variants of Merkle trees (hollow trees) and a modified cache management mechanism to greatly reduce the impact of the verification of the integrity. The performances of this solution have been evaluated both theoretically and in practice using simulations. In addition, a proof a security equivalence with regular Merkle treesis given. Finally, this solution has been implemented in the SecBus architecture which aims at protecting the integrity and confidentiality of the content of external memories in an embedded system. A prototype of this architecture has been developed and the results of its evaluation are given