Artigos de revistas sobre o tema "Memory and power applications"
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Zhang, Kaiqiang, Dongyang Ou, Congfeng Jiang, Yeliang Qiu e Longchuan Yan. "Power and Performance Evaluation of Memory-Intensive Applications". Energies 14, n.º 14 (6 de julho de 2021): 4089. http://dx.doi.org/10.3390/en14144089.
Texto completo da fonteKumar, S., M. Santhanalakshmi e R. Navaneethakrishnan. "Content addressable memory for energy efficient computing applications". Scientific Temper 14, n.º 02 (6 de junho de 2023): 430–36. http://dx.doi.org/10.58414/scientifictemper.2023.14.2.30.
Texto completo da fonteTyler, Neil. "Tempo Targets Low-Power Chips for AI Applications". New Electronics 52, n.º 13 (9 de julho de 2019): 7. http://dx.doi.org/10.12968/s0047-9624(22)61557-8.
Texto completo da fonteKumar Lamba, Anil, e Anuradha Konidena. "IoT Applications: Analysis of MTCMOS Cache Memory Architecture in a Processor". Journal of Futuristic Sciences and Applications 2, n.º 1 (2019): 24–33. http://dx.doi.org/10.51976/jfsa.211905.
Texto completo da fonteZuo, Ze Yu, Wei Hu, Rui Xin Hu, Heng Xiong, Wen Bin Du e Xiu Cai. "Efficient Scratchpad Memory Management for Mobile Multimedia Application". Advanced Materials Research 748 (agosto de 2013): 932–35. http://dx.doi.org/10.4028/www.scientific.net/amr.748.932.
Texto completo da fonteBirla, Shilpi. "Variability aware FinFET SRAM cell with improved stability and power for low power applications". Circuit World 45, n.º 4 (4 de novembro de 2019): 196–207. http://dx.doi.org/10.1108/cw-12-2018-0098.
Texto completo da fonteMarchal, P., J. I. Gomez, D. Atienza, S. Mamagkakis e F. Catthoor. "Power aware data and memory management for dynamic applications". IEE Proceedings - Computers and Digital Techniques 152, n.º 2 (2005): 224. http://dx.doi.org/10.1049/ip-cdt:20045077.
Texto completo da fonteK, Bharathi, e Vijayakumar S. "QCA Design of Encoder for Low Power Memory Applications". International Journal of Electronics and Communication Engineering 3, n.º 11 (25 de novembro de 2016): 13–15. http://dx.doi.org/10.14445/23488549/ijece-v3i11p114.
Texto completo da fonteFang, Juan, Jiajia Lu, Mengxuan Wang e Hui Zhao. "A Performance Conserving Approach for Reducing Memory Power Consumption in Multi-Core Systems". Journal of Circuits, Systems and Computers 28, n.º 07 (27 de junho de 2019): 1950113. http://dx.doi.org/10.1142/s0218126619501135.
Texto completo da fonteYadav, Pradeep Singh, e Harsha Jain. "Review of 6T SRAM for Embedded Memory Applications". Indian Journal of VLSI Design 3, n.º 1 (30 de março de 2023): 24–30. http://dx.doi.org/10.54105/ijvlsid.a1217.033123.
Texto completo da fonteKumar, Anurag, e Sheo Kumar. "Memory Architecture: Low-Power Single-Bit Cache". Journal of Futuristic Sciences and Applications 3, n.º 2 (2020): 64–72. http://dx.doi.org/10.51976/jfsa.322007.
Texto completo da fontePal, Srijani, Divya S. Salimath, Banusha Chandran, A. Anita Angeline e V. S. Kanchana Bhaaskaran. "Low Power Memory System Design Using Power Gated SRAM Cell". IOP Conference Series: Materials Science and Engineering 1187, n.º 1 (1 de setembro de 2021): 012008. http://dx.doi.org/10.1088/1757-899x/1187/1/012008.
Texto completo da fonteSantoro, Giulia, Giovanna Turvani e Mariagrazia Graziano. "New Logic-In-Memory Paradigms: An Architectural and Technological Perspective". Micromachines 10, n.º 6 (31 de maio de 2019): 368. http://dx.doi.org/10.3390/mi10060368.
Texto completo da fonteAkdemir, Bayram, e Hasan Üzülmez. "Providing Security of Vital Data for Conventional Microcontroller Applications". Applied Mechanics and Materials 789-790 (setembro de 2015): 1059–66. http://dx.doi.org/10.4028/www.scientific.net/amm.789-790.1059.
Texto completo da fonteTabbassum, Kavita, Shahnawaz Talpur e Noor-u.-Zaman Laghari. "Managing Scratchpad Memory Architecture for Lower Power Consumption Using Programming Techniques". Asian Journal of Applied Science and Engineering 9, n.º 1 (18 de maio de 2020): 79–86. http://dx.doi.org/10.18034/ajase.v9i1.31.
Texto completo da fonteL, Saranya, Abinaya Inbamani, Nivedita A e Arulanantham D. "Power Reduction in 4T DRAM Cell Using Low Power Topologies". ECS Transactions 107, n.º 1 (24 de abril de 2022): 5569–75. http://dx.doi.org/10.1149/10701.5569ecst.
Texto completo da fonteDatti, VenkataRamana, e Dr P. V. Sridevi. "A Novel Ternary Content Addressable Memory Cell". International Journal of Engineering & Technology 7, n.º 4.24 (27 de novembro de 2018): 67. http://dx.doi.org/10.14419/ijet.v7i4.24.21857.
Texto completo da fonteXue, Xingsi, Aruru Sai Kumar, Osamah Ibrahim Khalaf, Rajendra Prasad Somineni, Ghaida Muttashar Abdulsahib, Anumala Sujith, Thanniru Dhanuja e Muddasani Venkata Sai Vinay. "Design and Performance Analysis of 32 × 32 Memory Array SRAM for Low-Power Applications". Electronics 12, n.º 4 (7 de fevereiro de 2023): 834. http://dx.doi.org/10.3390/electronics12040834.
Texto completo da fonteKonig, R., U. Maurer e R. Renner. "On the Power of Quantum Memory". IEEE Transactions on Information Theory 51, n.º 7 (julho de 2005): 2391–401. http://dx.doi.org/10.1109/tit.2005.850087.
Texto completo da fonteFarrahi, Amir H., Gustavo E. Téllez e Majid Sarrafzadeh. "Exploiting Sleep Mode for Memory Partitioning and Other Applications". VLSI Design 7, n.º 3 (1 de janeiro de 1998): 271–87. http://dx.doi.org/10.1155/1998/50491.
Texto completo da fonteZhan, Ming, Zhibo Pang, Kan Yu e Hong Wen. "Reverse Calculation-Based Low Memory Turbo Decoder for Power Constrained Applications". IEEE Transactions on Circuits and Systems I: Regular Papers 68, n.º 6 (junho de 2021): 2688–701. http://dx.doi.org/10.1109/tcsi.2021.3068623.
Texto completo da fonteSingh, Pooran, B. S. Reniwal, V. Vijayvargiya, V. Sharma e S. K. Vishvakarma. "Dynamic Feedback Controlled Static Random Access Memory for Low Power Applications". Journal of Low Power Electronics 13, n.º 1 (1 de março de 2017): 47–59. http://dx.doi.org/10.1166/jolpe.2017.1470.
Texto completo da fonteGuchang, Han, Huang Jiancheng, Sim Cheow Hin, Michael Tran e Lim Sze Ter. "Switching methods in magnetic random access memory for low power applications". Journal of Physics D: Applied Physics 48, n.º 22 (6 de maio de 2015): 225001. http://dx.doi.org/10.1088/0022-3727/48/22/225001.
Texto completo da fonteSalamy, Hassan, e Semih Aslan. "Pipelined-Scheduling of Multiple Embedded Applications on a Multi-Processor-SoC". Journal of Circuits, Systems and Computers 26, n.º 03 (21 de novembro de 2016): 1750042. http://dx.doi.org/10.1142/s0218126617500426.
Texto completo da fonteLai, Chun Sing, Zhekang Dong e Donglian Qi. "Memristive Devices and Systems: Modeling, Properties and Applications". Electronics 12, n.º 3 (2 de fevereiro de 2023): 765. http://dx.doi.org/10.3390/electronics12030765.
Texto completo da fonteGnawali, Krishna Prasad, Seyed Nima Mozaffari e Spyros Tragoudas. "Low Power Spintronic Ternary Content Addressable Memory". IEEE Transactions on Nanotechnology 17, n.º 6 (novembro de 2018): 1206–16. http://dx.doi.org/10.1109/tnano.2018.2869734.
Texto completo da fonteKOUGIA, STAMATIKI, ALEXANDER CHATZIGEORGIOU e SPIRIDON NIKOLAIDIS. "EVALUATING POWER EFFICIENT DATA-REUSE DECISIONS FOR EMBEDDED MULTIMEDIA APPLICATIONS: AN ANALYTICAL APPROACH". Journal of Circuits, Systems and Computers 13, n.º 01 (fevereiro de 2004): 151–80. http://dx.doi.org/10.1142/s0218126604001313.
Texto completo da fonteKrishna, R., e Punithavathi Duraiswamy. "Low leakage decoder using dual-threshold technique for static random-access memory applications". Indonesian Journal of Electrical Engineering and Computer Science 30, n.º 3 (1 de junho de 2023): 1420. http://dx.doi.org/10.11591/ijeecs.v30.i3.pp1420-1427.
Texto completo da fonteYook, Chan-Gi, Jung Nam Kim, Yoon Kim e Wonbo Shim. "Design Strategies of 40 nm Split-Gate NOR Flash Memory Device for Low-Power Compute-in-Memory Applications". Micromachines 14, n.º 9 (7 de setembro de 2023): 1753. http://dx.doi.org/10.3390/mi14091753.
Texto completo da fonteBirla, Shilpi. "FinFET SRAM cell with improved stability and power for low power applications." Journal of Integrated Circuits and Systems 14, n.º 2 (25 de agosto de 2019): 1–8. http://dx.doi.org/10.29292/jics.v14i2.57.
Texto completo da fonteRhee, Chae Eun, Seung-Won Park, Jungwoo Choi, Hyunmin Jung e Hyuk-Jae Lee. "Power-Time Exploration Tools for NMP-Enabled Systems". Electronics 8, n.º 10 (28 de setembro de 2019): 1096. http://dx.doi.org/10.3390/electronics8101096.
Texto completo da fonteBanerjee, Writam. "Challenges and Applications of Emerging Nonvolatile Memory Devices". Electronics 9, n.º 6 (22 de junho de 2020): 1029. http://dx.doi.org/10.3390/electronics9061029.
Texto completo da fonteTripathi, Tripti, D. S. Chauhan e S. K. Singh. "Low leakage SRAM cell for ULP applications". International Journal of Engineering & Technology 7, n.º 4 (24 de setembro de 2018): 2521. http://dx.doi.org/10.14419/ijet.v7i4.14028.
Texto completo da fonteZHAO, WEISHENG, RAPHAEL MARTINS BRUM, LIONEL TORRES, JACQUES-OLIVIER KLEIN, GILLES SASSATELLI, DAFINÉ RAVELOSONA e CLAUDE CHAPPERT. "SPINTRONIC MEMORY-BASED RECONFIGURABLE COMPUTING". SPIN 03, n.º 04 (dezembro de 2013): 1340010. http://dx.doi.org/10.1142/s2010324713400109.
Texto completo da fonteFanariotis, Anastasios, Theofanis Orphanoudakis e Vassilis Fotopoulos. "Reducing the Power Consumption of Edge Devices Supporting Ambient Intelligence Applications". Information 15, n.º 3 (12 de março de 2024): 161. http://dx.doi.org/10.3390/info15030161.
Texto completo da fonteChang, Meng-Fan, Mary Jane Irwin e Robert Michael Owens. "Power-Area Trade-Offs in Divided Word Line Memory Arrays". Journal of Circuits, Systems and Computers 07, n.º 01 (fevereiro de 1997): 49–67. http://dx.doi.org/10.1142/s021812669700005x.
Texto completo da fonteDawwd, Shefa, e Suha Nori. "Reduced Area and Low Power Implementation of FFT/IFFT Processor". Iraqi Journal for Electrical and Electronic Engineering 14, n.º 2 (1 de dezembro de 2018): 108–19. http://dx.doi.org/10.37917/ijeee.14.2.3.
Texto completo da fonteMaciel, Nilson, Elaine Marques, Lírida Naviner, Yongliang Zhou e Hao Cai. "Magnetic Tunnel Junction Applications". Sensors 20, n.º 1 (24 de dezembro de 2019): 121. http://dx.doi.org/10.3390/s20010121.
Texto completo da fonteKotb, Youssef, Islam Elgamal e Mohamed Serry. "Shape Memory Alloy Capsule Micropump for Drug Delivery Applications". Micromachines 12, n.º 5 (6 de maio de 2021): 520. http://dx.doi.org/10.3390/mi12050520.
Texto completo da fonteChen, Ying-Chen, Szu-Tung Hu, Chih-Yang Lin, Burt Fowler, Hui-Chun Huang, Chao-Cheng Lin, Sungjun Kim, Yao-Feng Chang e Jack C. Lee. "Graphite-based selectorless RRAM: improvable intrinsic nonlinearity for array applications". Nanoscale 10, n.º 33 (2018): 15608–14. http://dx.doi.org/10.1039/c8nr04766a.
Texto completo da fonteHayashikoshi, Masanori, Hideyuki Noda, Hiroyuki Kawai, Yasumitsu Murai, Sugako Otani, Koji Nii, Yoshio Matsuda e Hiroyuki Kondo. "Low-Power Multi-Sensor System with Power Management and Nonvolatile Memory Access Control for IoT Applications". IEEE Transactions on Multi-Scale Computing Systems 4, n.º 4 (1 de outubro de 2018): 784–92. http://dx.doi.org/10.1109/tmscs.2018.2827388.
Texto completo da fonteTakagi, Shinichi, Kasidit Toprasertpong, Kent Tahara, Eishin Nako, Ryosho Nakane, Zeyu Wang, Xuan Luo, Tsung-En Lee e Mitsuru Takenaka. "(Invited) HfZrO-Based Ferroelectric Devices for Lower Power AI and Memory Applications". ECS Transactions 104, n.º 4 (1 de outubro de 2021): 17–26. http://dx.doi.org/10.1149/10404.0017ecst.
Texto completo da fonteTakagi, Shinichi, Kasidit Toprasertpong, Kent Tahara, Eishin Nako, Ryosho Nakane, Zeyu Wang, Xuan Luo, Tsung-En Lee e Mitsuru Takenaka. "(Invited) HfZrO-Based Ferroelectric Devices for Lower Power AI and Memory Applications". ECS Meeting Abstracts MA2021-02, n.º 30 (19 de outubro de 2021): 909. http://dx.doi.org/10.1149/ma2021-0230909mtgabs.
Texto completo da fonteBanerjee, Writam, Sheikh Ziaur Rahaman, Amit Prakash e Siddheswar Maikap. "High-κ Al2O3/WOxBilayer Dielectrics for Low-Power Resistive Switching Memory Applications". Japanese Journal of Applied Physics 50, n.º 10S (1 de outubro de 2011): 10PH01. http://dx.doi.org/10.7567/jjap.50.10ph01.
Texto completo da fonteBalestra, Francis. "Multi-gate Devices for High Performance, Ultra Low Power and Memory Applications". ECS Transactions 25, n.º 7 (17 de dezembro de 2019): 77–90. http://dx.doi.org/10.1149/1.3203945.
Texto completo da fonteBarradas, Filipe M., Pedro M. Tome, Telmo R. Cunha e Jose C. Pedro. "Compensation of Power Amplifier Long-Term Memory Behavior for Pulsed Radar Applications". IEEE Transactions on Microwave Theory and Techniques 67, n.º 12 (dezembro de 2019): 5249–56. http://dx.doi.org/10.1109/tmtt.2019.2940185.
Texto completo da fonteHansoo Kim e In-Cheol Park. "High-performance and low-power memory-interface architecture for video processing applications". IEEE Transactions on Circuits and Systems for Video Technology 11, n.º 11 (2001): 1160–70. http://dx.doi.org/10.1109/76.964782.
Texto completo da fonteWang, Chen, Xiuli Zhao, Hao Liu, Xin Chao, Hao Zhu e Qingqing Sun. "A High-Density Memory Design Based on Self-Aligned Tunneling Window for Large-Capacity Memory Application". Electronics 10, n.º 16 (13 de agosto de 2021): 1954. http://dx.doi.org/10.3390/electronics10161954.
Texto completo da fonteRao, M. V. Nageswara, Mamidipaka Hema, Ramakrishna Raghutu, Ramakrishna S. S. Nuvvula, Polamarasetty P. Kumar, Ilhami Colak e Baseem Khan. "Design and Development of Efficient SRAM Cell Based on FinFET for Low Power Memory Applications". Journal of Electrical and Computer Engineering 2023 (7 de junho de 2023): 1–13. http://dx.doi.org/10.1155/2023/7069746.
Texto completo da fonteStruharik, Rastislav, e Vuk Vranjković. "Striping input feature map cache for reducing off-chip memory traffic in CNN accelerators". Telfor Journal 12, n.º 2 (2020): 116–21. http://dx.doi.org/10.5937/telfor2002116s.
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