Teses / dissertações sobre o tema "Intégration des mots"
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Ji, Hyungsuk. "Étude d'un modèle computationnel pour la représentation du sens des mots par intégration des relations de contexte". Phd thesis, Grenoble INPG, 2004. http://tel.archives-ouvertes.fr/tel-00008384.
Texto completo da fonteMamy, Nina. "La condition des femmes originaires d'Afrique de l'Ouest en France entre enfermement et émancipation : éléments de réflexions sociopolitique et juridique". Thesis, Dijon, 2016. http://www.theses.fr/2016DIJOD004.
Texto completo da fonteNo abstract
Meyer, Jeanne. "Discours, discrimination sociolangagière et insertion professionnelle : les rapports complexes entre les mises en mots des accents et des attitudes linguistiques et / ou langagières". Phd thesis, Université Rennes 2, 2011. http://tel.archives-ouvertes.fr/tel-00681613.
Texto completo da fonteDumont, Benjamin. "Etude et intégration de jonctions ultra-fines pour les technologies CMOS 45 nm et en deçà". Lyon, INSA, 2007. http://www.theses.fr/2007ISAL0035.
Texto completo da fonteAl, Khoury Michel. "Intégration de filtres Radio Fréquences en technologie intégrée Silicium". Limoges, 2011. https://aurore.unilim.fr/theses/nxfile/default/8d644bc8-5cd6-464f-a4e4-4ac00c82ac27/blobholder:0/2011LIMO4038.pdf.
Texto completo da fonteWireless communications have evolved rapidly over the past twenty years. The design of these systems face some challenges: production cost, components integration techniques, size reduction, etc. Since many years, monolithic technology and specifically the manufacturing processes of silicon circuits (CMOS and BiCMOS) offer an opportunity to overcome such difficulties. Nowadays, they allow the integration of several RF and mixed functions on a single chip. However, the design of some RF functions is still a problem. This is the case of RF filters which constitute the essential elements of GSM telecommunications system. The demanded requirements by these filters lead to study solutions of active filters because passive structures (cavity, dielectric or SAW - Surface Acoustic Wave) do not allow better performance in term of insertion losses, selectivity, size reduction and frequency tuning. In this thesis, supported by an ANR contract (SRAMM project - Systèmes de Réception Adaptatifs Multimodes Multistandards), we were interested in the study of a new topology for active LC filter using Q-enhanced inductors. Our research analysis also consisted in defining a methodology for modeling three coupled inductors and using it to implement tunable LNA filter circuit useable in GSM3G system
Charron, Patrice. "Intégration du sol sabin : la mesure agraire de Manius Curius Dentatus". Master's thesis, Université Laval, 1992. http://hdl.handle.net/20.500.11794/28956.
Texto completo da fonteBidal, Gregory. "Intégration et caractérisation de nouveaux modules technologiques pour les applications CMOS à basse consommation". Grenoble INPG, 2009. http://www.theses.fr/2009INPG0082.
Texto completo da fonteMobile multimedia applications are requiring new CM OS technological solutions in order to improve the performance/consumption trade-off. Since devices dimensions are entering into the nanoscale era, parasitic phenomenon are becoming less and less negligible. This work deals with the study, the fabrication and the characterization of new technological modules that are suitable for reducing leakage components and for boosting carriers transport. Chapter 1 is a review of the state-of-the-art. Chapter 2 presents technological integration of each module and their co-integrability. Chapter 3 gives an overview of electrical performances finally discussed in circuits and SRAM perspectives. Last, in depth characterization of transport relevant parameters su ch as mobility and velocity is detailed in chapter 4. The latter tries to give the main transport limitations for each architecture
Gensolen, Fabrice. "Architecture et conception de rétines silicium CMOS : intégration de la mesure du mouvement global dans un imageur". Montpellier 2, 2006. http://www.theses.fr/2006MON20182.
Texto completo da fonteHaffner, Thibault. "Elaboration et intégration de nanofils GeSn pour la réalisation de dispositifs nanoélectroniques basse consommation". Thesis, Université Grenoble Alpes, 2020. https://tel.archives-ouvertes.fr/tel-03066536.
Texto completo da fonteSince the 1960's, technological development has been mainly driven by the miniaturization of components and follows the famous Moore's law. Indeed, miniaturization brought many advantages at the start. Lower switching time, more compact systems, lower supply voltage, and therefore, transistors consuming less, etc. However, this approach has started to falter in recent years. Indeed, the limits of miniaturization began to appear and the overall power consumption of the circuits began to increase which limits the realization of the systems. It then becomes necessary to develop low-consumption components, such as tunnel effect transistors. These transistors have, to date, a major defect which is their currents in the on state, much weaker than the MOSFETs. This current depends mainly on the architecture of the transistor as well as on the gap width of the source material.In this thesis, we propose to develop and study nanowires and heterostructures based on the germanium-tin alloy. The $ Ge_{1-x}Sn_x $ is an alloy of column IV which has a very small gap, less than 0.66 eV with the particularity of passing from an indirect gap to a direct gap from a concentration 10% of tin, which is favorable to tunnel effect transistors. Nanowires were developed by chemical vapor deposition using the vapor-liquid-solid mechanism and physicochemical analyzes such as X-ray spectroscopy and nano-Auger spectroscopy were used to characterize them. Hypotheses have been put forward in order to understand the mechanisms involved in the growth of GeSn nanowires and to better control their development. Axial heterostructures which will serve as basic materials for the realization of tunnel effect transistors are presented and detailed. We then present the study of the GeSn/dielectric interface in order to improve the performance of MOS capacities on GeSn, and therefore, to improve nanoelectronic devices. Chemical treatments were applied to the GeSn surface, and XPS and pAR-XPS analyzes were conducted to determine the effectiveness of the treatments. In order to improve the performance of the MOS capacities, we deposited a stack formed of an interfacial layer followed by a dielectric with high permittivity, such as $ HfO_2$, in order to obtain a low interface trap density. Finally, the integration and study of tunnel effect transistors based on heterostructures are presented. We first present the technological development stages developed in order to produce nanoelectronic devices. The doping levels of the heterostructures were evaluated by means of resistivity measurements. The performances of tunnel effect transistors were evaluated using electrical measurements and were compared with the current state of the art
M'Lembakani, T'Hengua Félicien. "ÉVALUATION ET AMÉLIORATION DES CAPACITÉS MOTRICES D'ENFANTS INFIRMES MOTEURS CÉRÉBRAUX CONGOLAIS ÂGES DE 6 Â 15 ANS". Doctoral thesis, Universite Libre de Bruxelles, 2018. http://hdl.handle.net/2013/ULB-DIPOT:oai:dipot.ulb.ac.be:2013/264367.
Texto completo da fonteDoctorat en Sciences de la motricité
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Gatet, Laurent. "Intégration de Réseaux de Neurones pour la Télémétrie Laser". Phd thesis, Toulouse, INPT, 2007. http://oatao.univ-toulouse.fr/7595/1/gatet.pdf.
Texto completo da fonteKalieu, Christian. "Surgissement, prolifération et intégration des motos-taxis dans les villes camerounaises : les exemples de Douala et Bafoussam". Thesis, Brest, 2016. http://www.theses.fr/2016BRES0078/document.
Texto completo da fonteDuring the last decades, daily urban and rural displacements in Cameroonian towns have suffered from an increase of motorcycle taxis in traffic flow. Those taxis are now considered the major mode of urban transport. This current predominance of two-wheelers in the urban landscape generates an explosive growth of pollution, road traffic accidents and public spending. The most direct and profound impact of this mutation is the increase of motorcycle accidents. Motorcycles are consequently the cause of violent conflicts among road users on the public highway. Our research has two goals: the first one is improving people's awareness of what is at stake concerning the motorcycle system and his negative effect in urban mobility, and the second one is giving food for thought in order to improve relations between motorcycle taxis and the other road users. We also want to help find solutions to manage and integrate motorcycles and their commercial use in the city. To do so, we will focus on urban, instructive, sociological and political approaches and on appropriate urban planning
Salimy, Siamak. "Développement, intégration et modélisation de composants passifs intégrés en couches minces dans une filière CMOS". Nantes, 2010. http://archive.bu.univ-nantes.fr/pollux/show.action?id=20bf03cd-b6fe-4f96-bb0f-365e5de32250.
Texto completo da fonteIn this thesis we present the development of a high density integrated passive technology. The aim is to integrate thin film passive components in the Back End of Line of an industrial CMOS technology by introducing limited additional steps. We propose to report all the electrical performance constraints of the components on the materials characteristics. The tree main steps to develop the integrated passives in O. 5µ-CMOS technology are presented. The first level of our study is focused closer to the material, and is applied in the case of MIM capacitors. The electrical characterization of TixTayO dielectrics thin film is performed from MOS capacitors to validate the material electrical performances before starting its process integration to realize the MIM capacitors. Secondly, the interface between the material and the component is studied. Based on the thin film resistors, we propose an integration schema for TiNxOy resistive thin film in the metallization layers of the CMOS technology. The electrical characteristics of the resistors are measured and validated via experiments. The last step of the study is focused on the integrated component level and its electrical modeling a new scalable, physical and analytical enhanced simple-П model of spiral inductors in CMOS technology is proposed. The entire model elements are determined under quasi-static approximations to obtain a fully scalable model from the geometrical and technological properties of the inductors. In this thesis, the bases for the development of integrated passive component in a CMOS technology are presented
Billaud, Mathilde. "Intégration de semi-conducteurs III-V sur substrat Silicium pour les transistors n-MOSFET à haute mobilité". Thesis, Université Grenoble Alpes (ComUE), 2017. http://www.theses.fr/2017GREAT010/document.
Texto completo da fonteThe replacement of the silicon channel by III-V materials is investigated to increase the electron mobility in the channel and reduce the power consumption. In order to decrease the cost and to take advantage of the microelectronic silicon platform, III-V transistors must be built on Silicon substrates. However, the lattice parameter mismatch between Silicon and the III-V layers leads to a high defects density in the channel and reduces the carrier mobility. This thesis aims to realize III-V transistors on silicon substrate in the CEA-Leti microelectronic clean room. In the frame of this PhD, two integration process are elaborated to realize In0,53Ga0,47As tri-gate transistors on silicon: the molecular bonding of an InGaAs layer grown on a InP substrate, and the direct epitaxy of InGaAs on a silicon substrate. The fabrication steps for InGaAs transistors were developed, taking into account the clean room contamination restriction. InGaAs surface treatment and high-permittivity dielectric deposition by ALD are studied in order to reduce the density of interface states (Dit) and to optimize the EOT. XPS analysis and C(V) measurement are performed at the scale of a 300mm Silicon substrate
Arnal, Vincent. "Intégration et caractérisation des performances de l'isolation par cavités des interconnexions en cuivre pour les technologies CMOS sub 90 nm". Chambéry, 2002. http://www.theses.fr/2002CHAMS010.
Texto completo da fonteSignal transmission along interconnects become critical in integrated circuits due to the increase of components density and clock frequency. Indeed, signal propagation time and crosstalk between adjacent lines are drivung performances and may generate logical faults. To overcome these limitations, copper interconnects have to be isolated by low permittivity dielectrics, known as "low k", instead of silicon oxide which relative dielectric constant is 4,2. In this study, we have developed a new approach where conventional dielectrics, for instance silicon oxide, continue to be integrated. But in this case, the non-conformal PECVD deposition process is taken into advantage to create cavities where they are really needed ie : between lines which are the most close. The major goal of the technique is to obtain an equivalent dielectric insulation with a permittivity below 2 by creating cavities between metal lines. This method is feasible if a selective and local integration of cavities is applied, making the deposition process uniform whatever dimensions of the circuit are. For that, a specific lithographiy mask is used, it defines placement of cavities in respect with design rules preliminary defined. The integration is carried out in a copper damascene architecture with several levels in order to check electrical parameters and reliability of interconnects. To characterize performances of a such insulation technique, coupling capacitances between lines are simulated and measured in order to extract an equivalent permittivity. Characterization continues by the study of signal propagation in isolated and coupled transmission lines in frequency domain up to 40 GHz. Insulation by cavity impacts significantly the reduction of crosstalk and crosstalk induced delay in comparison with homogeneous dielectrics. These results demonstrate the great potential of the technique to achieve required performances for sub 90 nm CMOS technologies
Grelu, Carloman. "Intégration de transistors haute tension en technologie CMOS 0,13 µm pour la gestion d'énergie des systèmes portables". Lyon, INSA, 2005. http://theses.insa-lyon.fr/publication/2005ISAL0065/these.pdf.
Texto completo da fonteMobile applications require to develop high voltage (20 V) switching devices with higher performances in combination with the lowest cost as possible. In this context, due to their lower fabrication cost, new Drift-MOSFET architectures were integrated into a 0. 13 µm CMOS technology, to replace the commonly used Diffused-MOSFETs. Based on results from a theoretical analysis on power losses in switching applications, several Drift-MOSFET releases were implemented to reduce both switching and heat's Joule losses. Main technological improvements consist of reducing both channel and gate to drain overlap lengths and of finally adding a dummy gate above the drain. These evolutions enable to reduce the linear resistance Ron and the average gate capacitance Cgg, which are respectively accountable to heat’s Joule losses and switching losses. We developed a small signal model for the gate capacitance in switching mode to express the average gate capacitance Cgg as a function of control drain (Vdd) and gate (Vgg) biases. The final expression of Cgg is linearly dependent of Vdd/Vgg ratio. By coupling this model to a specific measurement protocol, as close as possible of real operating conditions, we can easier compare devices performances taking into account Miller effect impact on switching losses. Results reveal that some Drift-MOSFETs releases present comparable performances to DMOS in addition to a more cost effective. The dummy gated Drift-MOSFET release presents best performances than DMOS and especially a very low Miller effect sensitivity. This study enables to do the statement of the different competitors for 20 V switching applications and to underline the necessity to take into account Miller effect for future technologies with lower command gate biases Vgg and then higher Vdd/Vgg ratios
Bourennane, Abdelhakim. "Etude et conception de structures bidirectionnelles en courant et en tension commandées par MOS". Toulouse 3, 2004. http://www.theses.fr/2004TOU30098.
Texto completo da fonteThis thesis work deals with the design of new MOS gated ac switch structures for ac mains applications, using functional integration. These devices are intended to replace the triac in ac mains applications. Indeed, the triac is a current controlled device requiring moderate amount of control power compared to voltage controlled devices. To develop new structures, the MOS controlled bidirectional devices proposed in the state of th art were analysed and their advantages as well as their drawbacks were highlighted. The first structure that we proposed is a MOS-riac that allows to have a triac structure with high input impedance and a voltage controlled structure. This structure is analysed using 2D simulations, designed, realised and we gave some experimental results. The second structure is a voltage and current bidirectional MOS-thyristor device. This structure uses a new type of triggering mode in the third quadrant of operation. Indeed, this mode of triggering is used for the first time in power semiconductor devices. To check that the lateral IGBT is capable of supplying the necessary current to turn-on the vertical thyristor, a lateral IGBT and a vertical thyristor were realised separately. The characterisation of these two components showed that it is possible to obtain the desired operation by integrating monolithically these two components. The third and last structure we proposed is also a bidirectional MOS controlled device. .
Lenoble, Damien. "Étude, réalisation et intégration de jonctions P+/N ultra-fines pour les technologies CMOS inférieures à 0,18 micromètre". Toulouse, INSA, 2000. http://www.theses.fr/2000ISAT0041.
Texto completo da fonteToni, Kotchikpa Arnaud. "Conception et intégration d'un convertisseur buck en technologie 28 nm CMOS orientée plateformes mobiles". Thesis, Lyon, 2019. http://www.theses.fr/2019LYSEI049.
Texto completo da fonteThis thesis work consists into the design of a 3 states buck converter targeting the improvement of dynamic regulation of microprocessors supplies. The topology of the converter is, at first, implemented in IBMCMOS 180 nm technology to validate the transient performances of the3 states regulator. The prototype in 180 nm, uses an input voltage of 3.6V and outputs a voltage in the range of 0.8V to 2V. Its response to load transients shows about 1% of undershoot and 2 % of overshoot, proving a good dynamic behavior for a simple structure compared to state of the art.The 3 states converter is then integrated in 28 nm CMOS HPM (technologymostly used for microprocessors desgn). The experimental results on the prototype confirm the performances in terms of energy and area savings, aswell as dynamic response. The chip delivers 0.5V to 1.2V from a 1.8V supply,and shows a 90% peak efficiency. The measurements of dynamic regulation show less than 5% of noise on the processor supply and 10 mV/ns outputvoltage switching for DVFS purpose
Pillet, Nicolas. "Conception et intégration de convertisseurs analogique/numérique, compacts, à bas bruit, adaptés aux capteurs CMOS destinés à la détection de particules chargées". Strasbourg, 2010. https://publication-theses.unistra.fr/public/theses_doctorat/2010/PILLET_Nicolas_2010.pdf.
Texto completo da fonteDevelopment of CMOS sensors has grown exponentially in the world of instrumentation in the past years because of their ability to integrate a sensitive element and the associated readout electronics on the same substrate at a low price. The CMOS-ILC team of IPHC has developed matrix of CMOS pixels for detectors used in particle physics for the last ten years. While using this kind of detectors for trajectometry, it could be interesting to raise the spatial resolution of the detectors. It could be fulfilled by implementing analog to digital converter (ADC) in the bottom of the column’s matrix. These ADCs must response to very strong constraint in term of dimension, conversion speed and power consumption. Three prototypes of ADCs with different architectures have been developed in order to respond to these specifications. The first one is a double numerical ramp ADC, the second one is a successive approximation ADC and the last one is an ADC with a progressive resolution. Three chips with these different architectures have been submitted and tested. The results have led to a comparison of the different technics in use in this particular field
Javerliac, Virgile. "Développement d'un modèle compact de la jonction tunnel magnétique de première génération et son intégration dans la réalisation d'architectures logiques reprogrammables hybrides magnétique-CMOS". Grenoble INPG, 2006. http://www.theses.fr/2006INPG0146.
Texto completo da fonteWhereas in standard CMOS logic the circuit functionality is fixed, in hardware programmable logic circuits it is possible to adapt the functionality to the circuit environment. Ln this thesis, we study highlyreconfigurable circuits which combine CMOS and nano magnetic MRAM-Like technologies. MRAM having recently demonstrated his potential in terms of speed, endurance and non-volatility, we transfert the concept to FPGA circuits. The simulation of such magnetic CMOS hybrid architectures requires at first the development of a SPICE-Like model of the magnetic tunnel junction, which is the building block of the MRAM cell. This model is further implemented into a standard microelectronic cad flow. Finally, an FPGA architecture combining speed and non-volatility is proposed and throughfully modeled
Fourment, Sabine. "Intégration multifonctionnelle dans un microsystème optique : application à un capteur de déplacement". Toulouse 3, 2003. http://www.theses.fr/2003TOU30064.
Texto completo da fonteIn Micro Optical Electromechanical Systems (MOEMs), functional integration paves the way for miniaturized systems, an increase in the functionality of current optic systems and the emergence of new systems. This integration relies on the design and development of collective, low cost technological processes using microelectronics on silicon. This work consists in miniaturizing a long range and nanometer resolved displacement sensor based on diffractive and interferometric phenomena. First, the interest and feasibility of integration of optic and electronic functions on silicon platform, using conventional CMOS technology is discussed. In the second part, an ultimate level of integration, based on original principle of interferometric detection, is proposed. First, the compatibility of standard CMOS technology with the sensor specifications is demonstrated, in particular in the photodetection domain. Then, we present the study of optoASICs including photodiodes and signal processing. Support card design, the component transfer onto this card and integration of the whole assembly into a compact and functional package are described and a prototype is fabricated
Schanen, Jean-Luc. "Intégration de la compatibilité électromagnetique dans la conception de convertisseurs statiques en électronique de puissance". Grenoble INPG, 1994. https://hal.archives-ouvertes.fr/tel-01907791.
Texto completo da fonteRibot, Pascal. "Développement et réalisation de structures Silicium et Silicium-Germanium par RTCVD et leur intégration dans les technologies BiCMOS et CMOS avancées". Université Joseph Fourier (Grenoble), 2001. http://www.theses.fr/2001GRE10051.
Texto completo da fonteMbow, Ndeye Awa. "Conception et intégration en technologie CMOS d'un circuit de lecture et d'identification de coïncidences à résolution temporelle de l'ordre de la nanoseconde destiné à l'imagerie biomédicale". Strasbourg, 2009. https://publication-theses.unistra.fr/restreint/theses_doctorat/2009/MBOW_Ndeye_Awa_2009.pdf.
Texto completo da fonteThe sequencing of the human genome and the genome of the mouse has shown that among the 30,000 genes that have human and mouse, only 300 are different. This remarkable similarity makes possible to study the development of diseases such as cardiovascular disease, cancer, neurodegenerative diseases, namely Alzheimer's or Parkinson's disease on mice. Thus, mouse models representing the human diseases have been multiplied. Molecular imaging which couples both anatomical and functional information has become an indispensable tool in biomedical research. One of the main researches of ImaBio's group of the Hubert Curien Pluridisciplinary Institute (IPHC) is developing a preclinical multimodal imaging system named AMISSA (A Multimodality Imaging System for Small Animal) and dedicated to small animal. This multimodal technology research is an innovative solution to biology issues. For the PET (Positron Emission tomography) modalities that should be integrated in the platform AMISSA, the number of channels (6144) of the proposed system and the size of the object imaged that will be fit on a diameter of 6 cm require an integrated electronic readout. The PET imaging system is designed to achieve a spatial resolution of 1 mm3 with detection efficiency better than 15%. Due to the geometry considered for the detector, its readout electronic should be able to achieve a large dynamic range from a few femto Coulombs to 104 pC for the measure of charges and an accurate measurement of the arrival time of signal with a precision better than 1 ns to make a narrow time coincidence window in order to reduce random coincidences. My contribution in this project is to participate in the development of this dedicated electronic module detection of the micro PET and also to characterize it. An ASIC prototype of 10 channels named IMOTEPA for the charge measurement and another of 16 channels named IMOTEPD dedicated to time stamp the photons have been developed in AMS CMOS 0. 35 µm. These two chips allowed us to validate separately the analogue part and the digital one of the photodetector's readout electronic. The final objective is to reach a single ASIC performing simultaneously both of these functions. Measured Integral Non-Linearity (INL) less than 3%, a crosstalk around 0. 2% for IMOTEPA and also jitter of about 120 ps RMS and Differential Non-Linearity of about ±0. 35 LSB for IMOTEPD, meet the specifications. These measures allow integrating a 64 channels prototype named IMOTEPAD which is under development in the laboratory. This manuscript provides a description of the ASICs IMOTEPA and IMOTEPD and presents the measurement results associated to them
Merhej, Mouawad. "Intégration 3D des transistors à nanofils de silicium-germanium sur puces CMOS". Thesis, Université Grenoble Alpes (ComUE), 2018. http://www.theses.fr/2018GREAT050.
Texto completo da fonteThe work of this thesis deals with the idea of demonstrating that the growth of nanowires between two predefined electrodes and more particularly the horizontal growth inside the oxide trenches can be used in the context of a 3D integration. This would help to directly manufacture the active semiconductor layers of a MOS transistor in the upper levels of a CMOS chip while respecting the thermal budget, and without resorting to chip bonding steps. During this project, we focused on the development and optimization of the "nanodamascene" process implemented to guide SiGe nanowires in oxide trenches directly on SiO2/Si substrate. Apart from this integration technique, we have also used the dielectrophoresis technique to orient and localize nanowires dispersed in a liquid solution between predefined electrodes. The results of these studies made it possible in the first place to manufacture nanowire channel transistors on the oxide, with a goal of which will be to demonstrate the possibility of establishing a transistor in the BEOL of a CMOS chip
Philippe, Justine. "Intégration hétérogène de systèmes communicants CMOS-SOI en gamme millimétrique sur substrat flexible". Thesis, Lille 1, 2017. http://www.theses.fr/2017LIL10178/document.
Texto completo da fonteThe ability to realize flexible circuits integrating sensing, signal processing, and communicating capabilities is of central importance for the development of numerous nomadic applications requiring foldable, stretchable and large area electronics. A large number of these applications currently rely on organic electronics, but new fabrication methods permitted to realize flexible mechanically and electrically efficient devices. Besides the transfert on flexible substrates offers many advantages (mechanical flexibility, preservation of original properties, possible heterogeneous integration). In this work, a solution has been developed, based on thinning and transfert onto flexible substrate (metal, glass) of high frequency (HF) CMOS devices initially patterned on conventional silicon-on-insulator (SOI) wafers. This transfer process first enables the fabrication of high performance electronics on metal, with n-MOSFETs featuring characteristic frequencies fT/fmax as high as 165/188 GHz. Secondly, the use of materials other than plastic permit to modify the original properties of a device in terms of thermal dissipation or harmonic distorsions for example, demonstrating flexibility, high performance and stability
Bosch, Daphnée. "Simulation, fabrication et caractérisation électrique de transistors MOS avancés pour une intégration 3D monolithique". Thesis, Université Grenoble Alpes, 2020. http://www.theses.fr/2020GRALT077.
Texto completo da fonteNowadays, Microelectronics industry must handle a real “data deluge” and a growing demand of added functionalities due to the new market sector of Internet Of Things, 5G but also Artificial Intelligence... At the same time, energy becomes a major issue and new computation paradigms emerge to break the traditional Von-Neumann architecture. In this context, this PhD manuscript explores both 3D monolithic integration and nano-electronic devices for In-Memory Computing. First, 3D monolithic integration is not seen only as an alternative to Moore’s law historic scaling but also to leverage circuit diversification. The advantages of this integration are analysed in depth and in particular an original top-tier Static Random Access Memories (SRAM) assist is proposed, improving significantly SRAM stability and performances without area overhead. In a second time, an original transistor architecture, called junctionless, suitable for 3D-monolithic integration is studied in detail. Devices are simulated, fabricated and electrically characterised for mixed digital/analog applications. In particular, the impact of channel doping density on mismatch is tackled. Also, low temperature (<500°C) junctionless bricks are developed and device optimization trade-off are discussed. In a third time, an innovative 3D structure combining state of the art devices: junctionless stacked Silicon nanowires and Resistive Random Access Memories (RRAM) is envisioned. This technology is proved to enable In-Memory Boolean operations through a so-called “scouting logic” approach
Boisvert, Alexandre. "Conception d'un circuit d'étouffement pour photodiodes à avalanche en mode Geiger pour intégration hétérogène 3D". Mémoire, Université de Sherbrooke, 2014. http://hdl.handle.net/11143/6153.
Texto completo da fonteAimadeddine, Mohamed. "Intégration et caractérisation de diélectriques poreux à très basse permittivité pour les interconnexions de circuits cmos sub-45nm". Grenoble INPG, 2008. http://www.theses.fr/2008INPG0025.
Texto completo da fonteLn order to achieve IC performance for sub 45nm nodes, porous Ultra Low-K (ULK) SiOCH dielectrics are integrated as interline dielectrics for interconnects. However, damascene Integration steps induce physico-chemical modification of the ULK dielectrics leading to a loss in performance and reliability after Integration. Ln order to tackle these issues, ULK modified interfaces need ta be stabilized. For that purpose, two different approac:hes are considered. On the one hand, post patterning plasma based treatments are studi. Ed. On the other hand, thin liner deposition on the modified SiOCH interfaces approach is explored. The impact of these approaches on the electrical performance and reliability of the interconnect is investigated. Besides, the electrical behaviour of the interconnect structure is studied. The effect of the SiOCH porosity on the conduction mechanism and the dielectric breakdown are examined
Boyer, Flore. "Intégration de contacts compatibles CMOS sur matériaux III-V pour des applications photoniques sur silicium en 300 mm". Thesis, Université Grenoble Alpes, 2020. http://www.theses.fr/2020GRALT068.
Texto completo da fonteIn the present context of the Big Data era, the requirement for higher density data transmission is of the utmost importance, since the demand in terms of data exchange has been growing for over 20 years. As a result, innovative means of communications have inevitably emerged, such as optical devices and interconnections. The later consist in technologies such as emitters (laser) and receptors (photodetector), made from III-V materials and integrated onto 300 mm CMOS Si-based circuitry: this what Silicon photonics is about. The latter indeed offers the possibility to meet the growing demand in data exchange, while (i) leveraging the benefits offered by the maturity of the 300~mm CMOS Si fab-line, such as high-volume production and low cost, combined with (ii) the use of optical circuitry made from III-V materials, granting reduced power consumption and high-performance chips. In the scope of optimizing the performances of such optoelectronic circuit, an innovative integration scheme has been developed in collaboration with STMicroelectronics and CEA-Leti. It consists in the full integration of the III-V emitter, which is a III-V/Si hybrid laser, onto a silicon wafer in a 300-mm CMOS-compatible clean room. One of the key components required for such integration is the development of CMOS-compatible contacts on both n-InP and p- In0.53Ga0.47As, which are the n- and p- contact layers of the III-V/Si hybrid laser, necessary for the generation and amplification of the optical signal. In this way, the goal of this PhD thesis lies in the development of these innovative contacts, meeting specific requirements, and allowing the full integration of the III-V/Si hybrid laser onto a 300 mm Silicon Photonics wafer. In this way, the eligibility of four metallization, hence eight systems, are thoroughly investigated. The systems are namely Ni/InP, Ni/In0.53Ga0.47As, Ni0.9Pt0.1/InP, Ni0.9Pt0.1/In0.53Ga0.47As, Ti/InP and Ti/ In0.53Ga0.47As. To do so, the formation phase sequence, layer morphology, element distribution and electrical properties of the enounced systems are studied. In addition, a reliability study has been performed on the systems, providing valuable and exclusive information regarding the evolution of the properties of the systems throughout subsequent process steps such as W-plug-filling and Back-End-Of-Line, as well as throughout the emulation of long-term thermal stress. Ultimately, a promising and reliable metallization is proposed for the full integration of the III-V/Si hybrid laser onto a 300~mm Si fab-line
Duchaine, Julian. "Caractérisation de l'implantation par immersion plasma avec pulsion(r) et intégration dans la fabrication de transistors FD-SOI et Trigate". Toulouse 3, 2012. http://www.theses.fr/2012TOU30197.
Texto completo da fonteThe industry of microelectronics will update regularly its "roadmap" for its international technological developments. The development of new technological processes is accelerating, driven by the need for portable electronics, personal computers with more powerful, telecommunications and multimedia, as well as the very important development of electronics in the automobile world. This race requires the integration of implantation processes with low energy and high dose (based on components). To meet the demand of industrial, IBS has developed its own prototype of plasma immersion ion implanter (PULSION (r)). This type of tool is very attractive to manufacturers because it offers performance and production rates (wafer / hour) with a lower manufacturing cost than conventional implanter (ion beam). This thesis aims to characterize the processes of P-type implantation by plasma immersion using the tool installed at the LETI "PULSION "to integrate in the manufacture of new transistors generations (FD-SOI ultimate Trigate for nano-wires). Many experimental studies have been performed to understand the physical and chemical mechanisms involved during the plasma immersion implantation. Understanding these mechanisms is much more complicated than ion beam implantation because the substrate is constantly immersed in the plasma and all ion species are implanted into the substrate. So, we observed different behavior of the implanted boron atoms between the two implantation techniques. The plasma and implantation conditions were optimized in order to integrate Pulsion (r) processes in the manufacture of FD-SOI and Trigate transistors. The first results show that plasma immersion implantation provides, on planar components (FD-SOI), the same electrical performance as ion beam implanter. Against by performance improved significantly on Trigate transistors. Further developments processes should improve again its performance
Carmignani, Corentin. "Conception, réalisation et caractérisation des propriétés électriques d'un capteur silicium micro-nano permettant une Co intégration CMOS / nano objets". Thesis, Université Grenoble Alpes (ComUE), 2018. http://www.theses.fr/2018GREAT043/document.
Texto completo da fonteSince the beginning of the third millennium, domains such as automotive, medical, food industry or consumer electronics (smartphone, computer, Hi-Fi etc.) are increasingly demanding more electronics chips. Needs have evolved so that, chips have to embed multiple function and diversification has become the new paradigm of electronics researches. At the same time, new biological objects with very specific and diverse properties are discovered and studied. Some are considered as ultimate solution to answer new microelectronics challenges. Moreover, there is a scale similarity between the finest transistors and biological objects. We asked ourselves the question: Can we use this similarity to create hybrid device? First, we investigated the application of nano biological object as interconnections. Despite of research the electrical characterization of biological object is still difficult to manage unlike standard materials as semi-conductors, so we developed an easy to use electrical characterization platform. Some biological object naturally reacts with dangerous or pathogenic agents and could be custom manufactured as proteins. This kind of object can be useful to create new hybrid sensors. We worked on design, manufacturing and characterization of 3D hybrid sensors based on silicon nanowires driven by a CMOS circuit. Then we investigated, with a simulation study, the possibility to detect a fine electric charge with a silicone nanowire which is a current area of interest in sensors research
Burgardt, Infanti Rúbia. "L’engagement social chez le bébé de 4-5 mois en situation de dialogue avec des partenaires familiers et étrangers : vers une approche intégrative". Thesis, Paris 10, 2017. http://www.theses.fr/2017PA100090/document.
Texto completo da fonteThe main objective of this thesis is to find out whether, beyond linguistic and social preferences for their native language and its users, infants younger than 6 months become involved with the rhythms and dialogical opportunities of speech. We chose to study the communicative behavior of infants aged 4 to 5 months because this constitutes a pivotal period for the integration of communicative competence. On the one hand, turn-taking is still a predominant type of organization in social interaction, and on the other hand, infants at this age are still more interested in social partners than in solitary object exploration. Furthermore, this period is usually thought to precede enculturation or the possibility of cultural learning. Yet, by 5 months, infants behave differently with a native language speaker than with a foreign language speaker and with a familiar person than with a stranger. This thesis includes 3 studies aimed at gaining insight into the social engagement of infants in situations of real and potential communication with social partners. The first study focuses on differences in vocal turn-taking organization between Brazilian and French cultural contexts. The second study’s aim is to shed light on the various expressive modalities infants use responsively in both cultural contexts during pauses between maternal utterances. In the third study, which is experimental, we wanted to know whether a French infant would have different expectations when faced with a French-speaking interlocutor compared with an interlocutor speaking a foreign language (Brazilian in this case). Overall, this thesis also makes a case for a more integrative approach to the study of infant communication, away from a dualist vision separating the body from thought, familiarity from novelty and innate from learned behavior and moving towards a more holistic perspective on humans beings
Cheng, Jun. "Intégration monolithique de matériaux III-V et de Ge sur Si en utilisant des buffers oxydes cristallins". Phd thesis, Ecole Centrale de Lyon, 2010. http://tel.archives-ouvertes.fr/tel-00565337.
Texto completo da fonteMeneghin, Grégory. "Intégration en technologie BiCMOS et caractérisation d'un convertisseur de fréquence de réception pour un radar automobile en bande W assurant des communications inter-véhicules". Toulouse 3, 2013. http://thesesups.ups-tlse.fr/2708/.
Texto completo da fonteThanks to the developments realized over the last decade, the nanoscale silicon technologies have become very competitive with III-V for millimeter-wave applications exceeding 100 GHz. The exclusive high integration levels of the silicon make it particularly well suited to design complex systems. In this thesis the background example of a W-band automotive impulse radar with inter-vehicle wireless data link is used to evaluate the capabilities of SiGe BiCMOS technology for the design of W-band zero-IF down-conversion mixer. When a zero-IF down-converter has to be designed, the passive mixer represents the best choice thanks to its absence of flicker noise. This mixer employs NMOS transistors in any Si-based technology. Among its benefits, one has to highlight its large linearity and a low noise figure equaling its conversion losses. Whereas it is widely used in low-power RF zero-IF receivers, the frequency limitations of this topology are not well-defined. The first part of this work evaluates the feasibility of this topology up to the W-band using a 0. 13 µm SiGe BiCMOS technology. The geometry of NMOS device is widely discussed regarding conversion losses and linearity. These results are then employed to design a 79 GHz down-converter including the RF and LO drivers as well as the IF amplifier. Finally, a test-bench is also developed to characterize the designed down-converter. Experimental results indicate state-of-the-art performances with a conversion gain of 14. 5 dB at an optimal center frequency of 76 GHz, a double-sideband noise figure of 6. 3 dB and an output compression point of -10dBm. These results, close to the electrical simulations, validate the whole design methodology
Nguyen, Roselyne. "Un système multi-agent pour la machine à dicter vocale MAUD : conception et intégration d'une source de connaissances phonologiques". Nancy 1, 1996. http://www.theses.fr/1996NAN10321.
Texto completo da fonteHeini, Sébastien. "Conception et intégration d’un capteur à pixels actifs monolithiques et de son circuit de lecture en technologie CMOS submicronique pour les détecteurs de position du futur". Strasbourg, 2009. http://www.theses.fr/2009STRA6045.
Texto completo da fonteThe thesis work, presented in this manuscript, was carried out for the development of the CMOS sensors which are foreseen to equip future vertex detector of the CBM experiment at FAIR (GSI, Darmstadt). First, we present new ionising particles detection circuits working in current mode: PhotoFETs. They were developed in order to improve the performances of the CMOS sensors, in particular the sensitivity and readout speed. Second, we present a new architecture of Double ramp Analogue-to-Digital Converter (ADC) with 4 bits resolution. Its integration into the CMOS sensors imposes specific constraints on the design of ADC: minimal material budget (layout size), severe limits on the power consumption and the conversion time. This contribution succeeded in good experimental results which open interesting perspectives for the integration of PhotoFETs and Double Ramp ADC in to CMOS sensors, in particular by using Very Deep Submicronic technologies and 3D technology
Tant, Gauthier. "Etude et intégration en SOI d’amplificateurs de puissance reconfigurables pour applications multi-modes multi-bandes". Thesis, Université Grenoble Alpes (ComUE), 2015. http://www.theses.fr/2015GREAT101/document.
Texto completo da fonteThis work focuses on the study and integration of a reconfigurable multi-mode multi-band power amplifier (MMPA) supporting 2G/3G/4G at several frequency bands in SOI CMOS 130nm technology. Current hybrid MMPA modules take advantage of multiple technologies, in particular GaAs for power devices. This adds to the cost and complexity of radiofrequency front-end modules. The original solution presented in this thesis is a significant step toward the integration of MMPA compared to the state of the art and initial results illustrates the relevance of the proposed architecture. A study on PA efficiency under 3G / 4G modulated signals is also presented by comparing load and supply modulation PA architectures.First, the context and state of the art are presented. A design methodology based on the study of different operating classes is then presented, which allows pre-sizing of power cells and optimal load impedance determination for high efficiency reconfigurable PA design.The proposed PA design methodology led to the implementation of PA demonstrators integrated in SOI CMOS 130nm technology. The first demonstrator is a two stage reconfigurable MMPA operating from 700MHz to 900MHz and supporting saturated and linear modes. The power stage comprises two SOI LDMOS power cells that are activated according to the desired mode. Tunable matching networks based on switched capacitor arrays allow optimization of the MMPA performance according to the mode and band. The measured prototype delivers up to 35dBm of output power in saturated mode with more than 58% efficiency. In linear mode, the measured output power exceeds 30dBm with efficiency higher than 47%. Compared to initial simulations, some differences were observed. In particular, underestimation of losses associated with MOM capacitors and sub-optimal interconnections are the root cause of the observed discrepancies.The second demonstrator is a passive load modulation PA architecture. It includes a SOI LDMOS power cell and a tunable matching network made of high power binary weighted switched capacitor arrays. The tunable matching network allows presenting an optimal load trajectory to the PA in order to maximize its back-off efficiency. Measured efficiency enhancement is higher than 55% compared to a fixed load configuration for 7dB to 11dB power back-offs
To, Duc Ngoc. "Circuit de pilotage intégré pour transistor de puissance". Thesis, Université Grenoble Alpes (ComUE), 2015. http://www.theses.fr/2015GRENT017/document.
Texto completo da fonteThis thesis work focuses on the design, modelling and the implementation of integrated gate drivers for power transistors based on CMOS coreless transformer. The main objectives of thesis are the design, modeling and characterization of coreless transformer in two technologies CMOS 0.35 µm bulk and CMOS 0.18 µm SOI, as well as the design and the characterization of two integrated gate drivers in these two technologies. The results of thesis allow us to validate our proposal models for coreless transformer: 2D electrical model and 3D electromagnetic model. Moreover, one CMOS bulk isolated gate driver which monolithically integrates the coreless transformer, the secondary side control circuit for power transistors has been fabricated and validated for both high side and low side configuration in a Buck converter. Finally, a CMOS SOI isolated gate driver is designed; integrates in one single chip the external control, the coreless transformer and the close gate driver circuit for power transistors. This one-chip solution presents a numerous advantages in term of interconnect parasitic, energy consumption, silicon surface consumption, and EMI with a high level of galvanic isolation. The perspectives of this SOI gate driver are multiple, on the one hand, are the 3D assemblies between gate driver/power transistors and on the other hand, are the multiple-switch converter
Le, Thanh Long. "Isolation galvanique intégrée pour nouveaux transitors de puissance". Thesis, Université Grenoble Alpes (ComUE), 2015. http://www.theses.fr/2015GREAT105/document.
Texto completo da fonteThis works proposes an approach of optical galvanic isolation between the control parts on one side and the power transistors and their associated drivers on the other side. This thesis consists of three chapters. After a literature review and the proposition of our approach in the first chapter, the design of the control chip and the different developed functions will be seen in detail in the second chapter. The practical results and performance achievements will be presented with several integrated photodetectors and signal processing circuit in CMOS technology. In the last chapter of the thesis, an integrated optically floating power supply will be investigated. The benefits of this approach will be discussed. These fabricated chips are manufactured in standard CMOS AMS C35 technology for first prototypes and transferred in SOI Xfab 018 CMOS technology to test these functions at high temperature. The implementation of the optically control circuit in a power converter will be presented to validate the operation of our "gate driver"
Cerba, Tiphaine. "Intégration de matériaux III-V à base d’arséniures et d’antimoniures pour la réalisation de transistors TriGate et NW à haute mobilité". Thesis, Université Grenoble Alpes (ComUE), 2018. http://www.theses.fr/2018GREAT082/document.
Texto completo da fonteThe transistors’s miniaturization evolved through technological nodes with the successive introduction of new materials (high k) and new architectures (FinFET, NWFET). For the advanced technological nodes, a new break in material is considered to replace the silicon of the conduction channel with high mobility materials (2D, III-V). III-V materials are good candidates to address a solution to this problem thanks to their n-type (InGaAs, InAs, InSb)or p-type (GaSb) high mobility. During this PhD, a particular interest has been given to the InAs/GaSb pair of materials, which offers an additional advantage by its lattice parameter agreement making it possible to access n-type and p-type high mobility layers in the same structure.Nowadays, the growth of III-V materials directly on (001) -Si 300mm substrates is a challenge of major interest to develop industrial platforms compatible processes. These growths remain complex because of defects formation: antiphase boundaries, dislocations, cracks; generated respectively by the difference in polarity, lattice mismatch and difference in thermal expansion coefficient, between the silicon and III-V materials. In this PhD, we present a first demonstration of GaSb growth by MOVPE directly on nominal (001) -Si 300mm substrate compatible with industrial platforms. The GaSb layers have a sub-1nm surface roughness, and an equal to MBE state of the art crystalline quality. The growth of a InAs layer then allowed the realization of an InAs FinFET multi-channel demonstrator. The latter was developed via a high resolution alternative lithographic technique based on the use of block copolymer. This simple method for producing conduction channels makes it possible to access a high density of wires, of small dimensions, and in only five manufacturingsteps
Emboras, Alexandros. "Intégration en technologie CMOS d'un modulateur plasmonique à effet de champ CMOS Integration of a field effect plasmonic modulator". Phd thesis, Université de Grenoble, 2012. http://tel.archives-ouvertes.fr/tel-00848107.
Texto completo da fonteRousseau, Maxime. "Impact des technologies d'intégration 3D sur les performances des composants CMOS". Phd thesis, Université Paul Sabatier - Toulouse III, 2009. http://tel.archives-ouvertes.fr/tel-00441653.
Texto completo da fontePinel, Stéphane. "Conception et réalisation d'assemblages 3D ultra-compacts par empilement de structures amincies". Toulouse 3, 2000. http://www.theses.fr/2000TOU30138.
Texto completo da fonteAmouroux, Julien. "Procédé de croissance et caractérisation avancée de nanocristaux de silicium pour une intégration dans les mémoires non-volatiles". Thesis, Aix-Marseille, 2013. http://www.theses.fr/2013AIXM4766/document.
Texto completo da fonteBy their performance and reliability, Flash technology is, today, the reference in nonvolatile memory . However, these memories being on track to reach their miniaturization limits , several alternative devices are currently being considered by the industrial sector, to anticipate market demands in the coming years .Since 2003, studies have been conducted on the replacement of the polysilicon floating gate by silicon nanocrystals in flash memory with nanocrystals to sustain this memory technology memory. Process flow modifications for nanocrystal integration allows a reduction of manufacturing costs, improving of reliability and miniaturization of devices . Integration of nanocrystals in a flash-like memory cell is therefore a challenge for the industry to extend the limits of miniaturization of the memory architecture based on the MOS transistor, historical device of the semiconductor industry.This manuscript presents the results of my thesis on the silicon nanocrystals growth process and morphological characterization for integration in a nonvolatile memory. The objectives of the thesis are :- Transfer of the manufacturing process of the silicon nanocrystals growth from CEA LETI plant to STMicroelectronics Rousset ;- Integration of nanocrystals in a non-volatile memory cell;- Optimization of manufacturing processes for industrialization ;- Development of tools to characterize the process chain ;- Physical and physico-chemical study of advanced silicon nanocrystals . and morphological characterization for integration in a nonvolatile memory
Prieto, herrera Rafael. "Développement d'une solution de répartition de la chaleur émise par les points chauds en co-intégration avec les technologies CMOS". Thesis, Université Grenoble Alpes (ComUE), 2018. http://www.theses.fr/2018GREAT113/document.
Texto completo da fonteWe witness today an explosion of nomadic technologies. Portable devices have become the main tool that people use to connect with the rest of the world. The microelectronics embedded in these devices is the technology that drives this process. The pace of development of these technologies is such that the versatility of portable devices today were science fiction only 10 years ago.The functionalities that will be integrated in the coming years cannot be imagined yet. These features will imply an increase of the computing demands, and consequently, of the heat dissipated inside them. The trend leads to complex stacks with heterogeneous modules of heat dissipating layers.These technologies will be integrated in everyday life. Internet of Things, as we call it, will demand an increasing amount of independent low footprint devices that will be connected. Heat dissipation strategies must therefore be compatible with increasingly smaller dimensions. Compact packages demand is growing rapidly, not only because of telephones and tablets, but also because of the massive introduction of electronics into in everyday life devices.The objective of the thesis is to study the integration of heat-spreaders in compact packages to enhance its thermal performance. This work goes deeply in the characterization of the thermal performance of carbon-base heat spreaders. Heat-spreaders are able to extract the heat produced in hot spots and transport it along its surface.In order to study the heat spreading phenomenon, a methodology that takes into account the multi-level nature of heat dissipation has been implemented. The objective is to be able to focus on the interaction between the heat-spreader and each one of the elements of the package stack. Two test vehicles have been re-used from previous works. A specific test vehicle was also design in order to emulate the thermal behavior of imaging sensors.The thesis is based on two main axes: Integration studies and thermal studies. The integration studies take into account the constraints derived from the implementation of heat spreaders in compact packages. Firstly, we focus on the implementation processes within an industrial process. Latelly, we study the thermomechanical effects of heat spreaders and the impact on the integrity of high frequency signals.Thermal studies are aimed to characterize the performance gain derived from this heat spreader integration. The thermal phenomena are analyzed with measurements and simulations. First at silicon and interface level, then at package level, finally we focus on the effects in image sensor die and package.In the light of the results it can be said that carbon based materials are the most interesting alternative for large-scale implementation of heat spreaders in compact packages. This implementation will be driven by the research of new functionalities and performances in compact packages. The heat spreader will have to perform while maintaining a minimal footprint. The combination of carbon layers at all package levels, along with reduced thermal interface thickness will be the trend in the coming years for this type of device.This thesis is part of a tripartite collaboration between the CEA-LETI of Grenoble, the G2Elab laboratory of the INP Grenoble and STMicroelectronics in Crolles
Saracco, Émeline. "Fabrication et co-intégration de transistors n-MOS à base de nanofils de silicium et de transistors p-MOS à base de nanofils de germanium". Grenoble INPG, 2010. http://www.theses.fr/2010INPG0120.
Texto completo da fonteIn order to manage the microelectronic challenges in terms if miniaturization, performances and consumption, new alternatives to the Silicon planar integration are now studied. The 3D co-integration of Silicon nanowires for nMOS transistors and Ge nanowires for pMOS are particularly interesting. This CMOS structure has many advantages : the choice of materials allows optimization of the transport properties to the whole structure. First, high integration density si possible due to the small size of the nanowires. Secondly, high current per unit area can be obtained through a vertical stack of channels. Finally, the use of a gate-all-around structure allows for a perfect electrostatic control channel. This thesis focuses on the fabrication of two kinds of nanowires by an innovating top-down technique. Suspended horizontal Si nanowires were first fabricated. The study of their oxidation highlighted effects of size and aspect ratio. A predictive simulation tool was implemented to simulate the oxidation of Si nanowires. A process for integrating Ge-rich SiGe nanowires on one or more levels was then proposed. The Ge content, nanowire size and morphology, can be tuned thanks to oxidation parameters. These nanowires are cristalline and continuous along the nanowire length. However, the SiGe nanowires bent after their release, which is an obstacle to their integration. Therefore, new innovative methods have been implemented to limit this blending, using sSOI substrates and SiGeC layers. Finally, the features of the oxidation of SiGe nanowires were analyzed through the use of experimental and numerical simulation. The specific phenomena to be taken into account during the oxidation of the different kinds of SiGe nanowires are then detailed
Comyn, Rémi. "Développement de briques technologiques pour la co-intégration par l'épitaxie de transistors HEMTs AlGaN/GaN sur MOS silicium". Thesis, Université Côte d'Azur (ComUE), 2016. http://www.theses.fr/2016AZUR4098.
Texto completo da fonteThe monolithic integration of heterogeneous devices and materials such as III-N compounds with silicon (Si) CMOS technology paves the way for new circuits applications and capabilities for both technologies. However, the heteroepitaxy of such materials on Si can be challenging due to very different lattice parameters and thermal expansion coefficients. In addition, contamination issues and thermal budget constraints on CMOS technology may prevent the use of standard process parameters and require various manufacturing trade-offs. In this context, we have investigated the integration of GaN-based high electron mobility transistors (HEMTs) on Si substrates in view of the monolithic integration of GaN on CMOS circuits
Coudrain, Perceval. "Contribution au développement d'une technologie d'intégration tridimensionnelle pour les capteurs d'images CMOS à pixels actifs". Toulouse, ISAE, 2009. http://www.theses.fr/2009ESAE0005.
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