Artigos de revistas: "High density interconnection PCBs"

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Cauwe, Maarten, Bart Vandevelde, Chinmay Nawghane, Marnix Van De Slyeke, Erwin Bosman, Joachim Verhegge, Alexia Coulon e Stan Heltzel. "High-Density Interconnect Technology Assessment of Printed Circuit Boards for Space Applications". Journal of Microelectronics and Electronic Packaging 17, n.º 3 (1 de julho de 2020): 79–88. http://dx.doi.org/10.4071/imaps.1212898.

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Abstract High-density interconnect (HDI) printed circuit boards (PCBs) and associated assemblies are essential to allow space projects to benefit from the ever increasing complexity and functionality of modern integrated circuits such as field-programmable gate arrays, digital signal processors and application processors. Increasing demands for functionality translate into higher signal speeds combined with an increasing number of input/outputs (I/Os). To limit the overall package size, the contact pad pitch of the components is reduced. The combination of a high number of I/Os with a reduced pitch places additional demands onto the PCB, requiring the use of laser-drilled microvias, high-aspect ratio core vias, and small track width and spacing. Although the associated advanced manufacturing processes have been widely used in commercial, automotive, medical, and military applications, reconciling these advancements in capability with the reliability requirements for space remains a challenge. Two categories of the HDI technology are considered: two levels of staggered microvias (basic HDI) and (up to) three levels of stacked microvias (complex HDI). In this article, the qualification of the basic HDI technology in accordance with ECSS-Q-ST-70-60C is described. At 1.0-mm pitch, the technology passes all testing successfully. At .8-mm pitch, failures are encountered during interconnection stress testing and conductive anodic filament testing. These failures provide the basis for updating the design rules for HDI PCBs.

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Bernhard, T., L. Gregoriades, S. Branagan, L. Stamp, E. Steinhäuser, R. Schulz e F. Brüning. "Nanovoid Formation at Cu/Cu/Cu Interconnections of Blind Microvias: A Field Study". International Symposium on Microelectronics 2019, n.º 1 (1 de outubro de 2019): 000492–502. http://dx.doi.org/10.4071/2380-4505-2019.1.000492.

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Abstract A key factor for a high electrical reliability of multilayer High Density Interconnection Printed Circuit Boards (HDI PCBs) is the thermomechanical stability of stacked microvia interconnections. With decreasing via sizes and higher numbers of interconnected layers, the structural integrity of these interconnections becomes a critical factor and is a topic of high interest in current research. The formation of nanovoids and inhibited Cu recrystallization across the interfaces are the two main indications of a weak link from the target pad to the filled via. Based on TEM/EDX measurements on a statistically relevant number of stacked and blind microvias produced in the industrial field, different types of nanovoid phenomena are revealed at the Cu/Cu/Cu junction. The types of nanovoids were categorized relating to the time of appearance (before or after thermal treatment), the affected interfaces or layers and the impact on the Cu recrystallization. The main root causes for each void type are identified and the expected impact on the thermomechanical stability of the via junction is discussed.

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Petrosyants, Konstantin O., e Anton A. Popov. "Experimental Investigation of Temperature-Current Rise in Fine PCB Copper Traces on Polyimide, Aluminium and Ceramic (Al₂O₃) Substrates". Advanced Materials Research 739 (agosto de 2013): 155–60. http://dx.doi.org/10.4028/www.scientific.net/amr.739.155.

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Three types of copper traces for PCBs were investigated: 1) 2.5 μm thin film lines (Ti;Cu;Ni) on aluminium and ceramic (Al2O3) substrates; 2) 2.5 μm thin film lines (Ti;Cu;Ni;Au) on ceramic (Al2O3) substrates; 3) 15 μm traces (Cu;Ni) on polyimide substrate for high density interconnection PCBs. The width of all types of traces was varying in the range of 100-500 μm. The set of temperature-current diagrams for different PCB scenarios are presented and analyzed. The temperature caused by Joule heating was measured using IR camera Flir A40 with macrolens. For different cases the current was set in the range of 0.1-3 A; the measured temperature was in the range of 20-140 °C. The close agreement between the results measured and simulated with ELCUT software tool was achieved.

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Ji, Linxian, Chong Wang, Shouxu Wang, Wei He, Dingjun Xiao e Ze Tan. "Multiphysics coupling simulation of RDE for PCB manufacturing". Circuit World 41, n.º 1 (2 de fevereiro de 2015): 20–28. http://dx.doi.org/10.1108/cw-09-2014-0037.

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Purpose – The purpose of this paper is to optimize experimental parameters and gain further insights into the plating process in the fabrication of high-density interconnections of printed circuit boards (PCBs) by the rotating disc electrode (RDE) model. Via metallization by copper electrodeposition for interconnection of PCBs has become increasingly important. In this metallization technique, copper is directly filled into the vias using special additives. To investigate electrochemical reaction mechanisms of electrodeposition in aqueous solutions, using experiments on an RDE is common practice. Design/methodology/approach – An electrochemical model is presented to describe the kinetics of copper electrodeposition on an RDE, which builds a bridge between the theoretical and experimental study for non-uniform copper electrodeposition in PCB manufacturing. Comsol Multiphysics, a multiphysics simulation platform, is invited to modeling flow field and potential distribution based on a two-dimensional (2D) axisymmetric physical modeling. The flow pattern in the electrolyte is determined by the 2D Navier–Stokes equations. Primary, secondary and tertiary current distributions are performed by the finite element method of multiphysics coupling. Findings – The ion concentration gradient near the cathode and the thickness of the diffusion layer under different rotating velocities are achieved by the finite element method of multiphysics coupling. The calculated concentration and boundary layer thicknesses agree well with those from the theoretical Levich equation. The effect of fluid flow on the current distribution over the electrode surface is also investigated in this model. The results reveal the impact of flow parameters on the current density distribution and thickness of plating layer, which are most concerned in the production of PCBs. Originality/value – By RDE electrochemical model, we build a bridge between the theoretical and experimental study for control of uniformity of plating layer by concentration boundary layer in PCB manufacturing. By means of a multiphysics coupling platform, we can accurately analyze and forecast the characteristic of the entire electrochemical system. These results reveal theoretical connections of current density distribution and plating thickness, with controlled parameters in the plating process to further help us comprehensively understand the mechanism of copper electrodeposition.

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Avitabile, Gianfranco, Antonello Florio, Vito Leonardo Gallo, Alessandro Pali e Lorenzo Forni. "An Optimization Framework for the Design of High-Speed PCB VIAs". Electronics 11, n.º 3 (6 de fevereiro de 2022): 475. http://dx.doi.org/10.3390/electronics11030475.

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Signal integrity represents a key issue in all modern electronic systems, which are strongly dominated by the extreme component density usually employed on PCBs and the associated increase in the interconnection density. The use of multi-layer structures with microstrips connected by various types of Vertical Interconnect Accesses (VIAs) calls for design strategies that reduce the impedance mismatch and signal attenuation. The paper proposes a thorough analysis of the effects associated with the VIA geometry and presents a parametric evaluation of them. The obtained results represent the starting point for a possible design procedure that manages the geometric aspects of differential VIAs, aiming to optimize their electrical performance while reducing their occupation of PCB area. The optimization technique considers a differential VIA as a four-port circuit whose characteristics are evaluated with suitable Figures of Merit (FoMs), thus striving for an optimal design obtained with closed-loop iterations. The analysis is performed in both the time (TDR: Time-Domain Reflectometry) and frequency domains (S and Z parameters), thus allowing a dramatic reduction in the number of cases to be analyzed. The procedure is thoroughly described and validated using simulation results.

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Bernhard, T., S. Branagan, R. Schulz, F. Brüning, L. Stamp, K. Wurdinger e S. Kempa. "The Formation of Nano-voids in electroless Cu Layers". MRS Advances 4, n.º 41-42 (2019): 2231–40. http://dx.doi.org/10.1557/adv.2019.336.

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ABSTRACTThe electrical reliability of multilayer high density interconnection printed circuit boards (HDI-PCBs) is mainly affected by the thermo-mechanical stability of stacked micro via interconnections. Here, a critical failure mode is the stress related crack between the electrolytically filled via and the target pad, commonly known as target pad separation. The junction includes two Cu-Cu-interfaces, one between the target Cu pad and the thin electroless Cu layer and the second between electroless Cu and electrolytic Cu. In this paper we will show that state-of-the-art electroless Cu plating processes are able to provide solid, completely recrystallized and highly reliable stacked via junctions. Defect free interfaces were achieved by using ionic Pd-activators and electroless Cu baths with a cyanide based stabilizer system. Cyanide free electroless Cu baths tend more to the formation of nanometer sized defects, discovered via Transmission Electron Microscopy (TEM). In this case a precise adjustment of single stabilizer components is mandatory to achieve defect free layers. The defects are hollow and were identified as “nano voids”. A critical density of these nano voids weakens the interface, predefines the crack path and reduces the overall reliability of the junction. A precise localization of the nano voids within the junction was enabled by detecting the Ni-containing electroless Cu layer via TEM-Ni mapping. Slower volume exchange of the electroless Cu solution within the blind micro via (BMV) substantially increases the nano void density. The ability of nano voids to migrate and coalesce at elevated temperatures was investigated as well.

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He, Huirong, Jida Chen, Shengtao Zhang, Minhui Liao, Lingxing Li, Wei He, Yuanming Chen e Shijin Chen. "Fabrication and surface treatment of fine copper lines for HDI printed circuit board with modified full-additive method". Circuit World 43, n.º 3 (7 de agosto de 2017): 131–38. http://dx.doi.org/10.1108/cw-02-2017-0004.

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Purpose This paper aims to propose a modified full-additive method (MFAM) to fabricate fine copper lines for high density interconnection (HDI) printed circuit boards (PCBs). In addition, the surface of the fine copper lines is treated with a brown oxidation process to obtain good adhesion between the copper and the dielectric resin. Design/methodology/approach Fine copper lines fabricated by MFAM were observed to evaluate the undercut quality, in comparison to undercut quality of copper lines fabricated by the semi-additive method and the subtractive method. The effect of the thickness of the dry film on the quality of the copper plating was investigated to obtain the regular shape of fine lines. The fine copper lines treated with the brown oxidation process were also examined to generate a coarse surface microstructure to improve the adhesion between the copper and the dielectric resin. The cross section and surface of as-fabricated fine copper lines were characterized using an optical microscope, a scanning electron microscope and an atomic force microscope. Findings MFAM has the potential to fabricate high-performance fine copper lines for HDI PCBs. Undercut of as-fabricated fine copper lines could be prevented to meet the design requirement of impedance. In addition, fine copper lines exhibit enough adhesive force to laminate with dielectric resin after the brown oxidation process. Originality/value MFAM, with the advantages of high efficiency and being a facile process, is developed to fabricate high-quality fine copper lines for industrial HDI PCB manufacture.

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Shearer, Catherine, Ken Holcomb e Jim Haley. "Shrinking Package Footprint by Embedding Top-Side Real Estate Using Core-to-Core Joining". Additional Conferences (Device Packaging, HiTEC, HiTEN, and CICMT) 2015, DPC (1 de janeiro de 2015): 001982–2014. http://dx.doi.org/10.4071/2015dpc-tha22.

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The electronics industry trend continues to be to continually increase capability and performance within an existing or smaller footprint. Shoehorning all of the required components onto the exterior surface of the PCB has become an increasingly difficult puzzle. The use of stacked microvias instead of plated through holes and stacked ICs in various configurations has freed up some real estate. The use of ever smaller passive devices also saves space, but reintroduces old issues such as tombstoning. The ideal solution would be to provide ‘surface’ real estate within the architecture of the circuit board – like moving items from a desk to a bookshelf – by embedding components into the board. In this paper, an alternative strategy is presented for embedded components. Sub-PCB constructions are built and populated on both sides, and then are joined using an interposer with sintering conductive paste interconnects. Sintering paste z-axis interconnections have been successfully used in this type of core-to-core joining for many years. The combination of the sintering paste interconnect and an interposer element is the key to enabling this architecture. This manufacturing strategy presents a number of advantages. The board may be broken down into logical substructures such as high density, core or RF portions. Each of the sub-PCBs can be fabricated according to best manufacturing practices for that portion of the circuit board rather than trying to fabricate a single complicated board. Yield losses from sequential process steps and multiple laminations may be reduced. The embedded components may be assembled onto the sub-PCBs using conventional solder reflow technology. The component placement can facilitate point-of-source architecture for high electrical performance. The process flow and some laboratory demonstrations of this technique will be presented in this paper.

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Hübner, Henning, Christian Ohde e Dirk Ruess. "Upscaling panel size for Cu plating on FOPLP (Fan Out Panel Level Packaging) applications to reduce manufacturing cost". International Symposium on Microelectronics 2018, n.º 1 (1 de outubro de 2018): 000037–42. http://dx.doi.org/10.4071/2380-4505-2018.1.000037.

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Abstract Electrolytic metal deposition is a key process step in the manufacturing of vertical and horizontal interconnections used in today's PCBs and IC substrates on one hand and advanced packaging applications on the other hand. Historically both application areas were clearly defined and separated by different requirements in feature sizes and substrate formats. PCBs and IC substrates were based on organic large scale substrates with rather large features while advanced packaging technology is wafer based with the capability to incorporate fine features down to a few microns. The ever increasing demand of higher performance, lower cost and thinner end user devices like smartphones require intense developments and innovation in all areas of the electronic component design including the substrate and chip packaging. Latest manufacturing technologies in both areas like fan-out wafer level packaging and advanced substrates are constantly emerging and promise to be a critical piece to meet these requirements. As a consequence both areas are currently merging while creating a new application segment. This segment combines the request of small feature sizes with the manufacturability on large scale substrates. Obviously many of the traditional process technologies like plating and available equipment cannot be easily adopted and need certain developments, adaptions and improvements. In this respect, a key challenge in the area of electrolytic metal deposition is the combination of various challenging requirements: creation of feature sizes down to 2μm L/S with heterogeneous feature density on large substrates up to 600mm at excellent metal thickness uniformity and high plating speed. The paper presents latest studies and conclusions in critical performance areas of the plating process such as electrolyte fluid dynamics, impact of anode design, pulse reverse rectification and newly designed electrolytes. Finally latest test results of optimized process conditions will be discussed in detail with different feature sizes providing data of within die and within substrate uniformity. All tests are done on panel level, both organic and glass substrates. The latest findings and achievements of the discussed panel based plating process technology will support the industry to develop panel based packaging processes that meet both technical and commercial requirements.

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Katahira, Takayoshi, Ilkka Kartio, Hiroshi Segawa, Michimasa Takahashi e Katsumi Sagisaka. "Vertically high-density interconnection for mobile application". Microelectronics Reliability 46, n.º 5-6 (maio de 2006): 756–62. http://dx.doi.org/10.1016/j.microrel.2005.07.001.

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Umarji, G. G., S. A. Ketkar, G. J. Phatak, T. Seth, U. P. Mulik e D. P. Amalnerkar. "Photoimageable silver paste for high density interconnection technology". Materials Letters 59, n.º 4 (fevereiro de 2005): 503–9. http://dx.doi.org/10.1016/j.matlet.2004.10.034.

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Vrana, M., A. Van Calster, R. Vanden Berghe** e K. Allaert. "Interconnection Technology for Advanced High Density Thick Films". Microelectronics International 13, n.º 3 (dezembro de 1996): 5–8. http://dx.doi.org/10.1108/13565369610800322.

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Selvakumar, Kandaswamy, Senthamilselvan Bavithra, Sekaran Suganya, Firdous Ahmad Bhat, Gunasekaran Krishnamoorthy e Jagadeesan Arunakaran. "Effect of Quercetin on Haematobiochemical and Histological Changes in the Liver of Polychlorined Biphenyls-Induced Adult Male Wistar Rats". Journal of Biomarkers 2013 (1 de outubro de 2013): 1–12. http://dx.doi.org/10.1155/2013/960125.

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Polychlorinated biphenyls exposure damages the rat liver cells. Hematological parameters such as hemoglobin, packed cell volume, red-blood cells, white-blood cells, neutrophils, platelet counts, and RBC indices were significantly decreased. Polymorphs, eosinophil counts, and erythrocyte sedimentation rate were significantly increased. Serum liver enzymes such as aspartate transaminase, alanine transaminase, alkaline phosphatase, and gamma-glutamyl transferase were increased by PCBs treatment. Serum lipid profiles such as cholesterol, triglycerides, low-density lipoproteins and very-low-density lipoproteins were increased in PCBs-treated rats. High-density lipoprotein, total protein, albumin, globulin levels, and albumin/globulin ratio were also decreased after PCB exposure. Then levels of sodium, potassium, chloride, and bicarbonate were also altered. Serum glucose levels were increased along with total bilirubin after PCBs exposure. Simultaneous quercetin supplementation significantly protected the PCBs-induced changes of hematobiochemical parameters. Thus, quercetin shows a protective role against PCBs-induced alterations in the hematological and biochemical parameters.

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HONDA, Susumu. "Importance of Environmental-Friendly High Density Packaging and Interconnection". Journal of Japan Institute of Electronics Packaging 1, n.º 4 (1998): 257–58. http://dx.doi.org/10.5104/jiep.1.257.

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Jahns, Jürgen, e Bruno Acklin. "Integrated planar optical imaging system with high interconnection density". Optics Letters 18, n.º 19 (1 de outubro de 1993): 1594. http://dx.doi.org/10.1364/ol.18.001594.

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Fjelstad, Joseph. "Interconnection strategies for high‐density printed circuits – an overview". Circuit World 28, n.º 1 (março de 2002): 6–9. http://dx.doi.org/10.1108/03056120210407685.

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Yu, Changyuan, Michael R. Wang, Alberto J. Varela e Bing Chen. "High-density non-diffracting beam array for optical interconnection". Optics Communications 177, n.º 1-6 (abril de 2000): 369–76. http://dx.doi.org/10.1016/s0030-4018(00)00583-6.

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Takahashi, Kenji, Mitsuo Umemoto, Naotaka Tanaka, Kazumasa Tanida, Yoshihiko Nemoto, Yoshihiro Tomita, Masamoto Tago e Manabu Bonkohara. "Ultra-high-density interconnection technology of three-dimensional packaging". Microelectronics Reliability 43, n.º 8 (agosto de 2003): 1267–79. http://dx.doi.org/10.1016/s0026-2714(03)00167-7.

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Sang-Pil Han, In-Kui Cho, Sung-Hwan Hwang, Woo-Jin Lee e Seung-Ho Ahn. "A high-density two-dimensional parallel optical interconnection module". IEEE Photonics Technology Letters 17, n.º 11 (novembro de 2005): 2448–50. http://dx.doi.org/10.1109/lpt.2005.857250.

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Broadbent, E. K., J. M. Flanner e W. G. M. Van den Hoek. "High-density high-reliability tungsten interconnection by filled interconnect groove metallization". IEEE Transactions on Electron Devices 35, n.º 7 (julho de 1988): 952–56. http://dx.doi.org/10.1109/16.3350.

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Gong, Hua, Adam T. Woolley e Gregory P. Nordin. "3D printed high density, reversible, chip-to-chip microfluidic interconnects". Lab on a Chip 18, n.º 4 (2018): 639–47. http://dx.doi.org/10.1039/c7lc01113j.

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Nechay, Bettina, Megan Snook, Harold Hearne, Ty McNutt, Victor Veliadis, Sharon Woodruff, R. S. Howell, David Giorgi, Joseph White e Stuart Davis. "High-Yield 4H-SiC Thyristors for Wafer-Scale Interconnection". Materials Science Forum 717-720 (maio de 2012): 1171–74. http://dx.doi.org/10.4028/www.scientific.net/msf.717-720.1171.

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Modern power conditioning systems require large active area devices which can support high currents. Though the breakdown and thermal properties of SiC make it an excellent choice for power switching applications, active area size is currently limited due to material and processing defects. One alternative is to parallel discrete diced die to achieve large active areas. However, this increases cost and complexity through dicing, soldering, and forming multiple wire bonds. Furthermore, paralleling discrete devices increases package volume/weight and reduces power density. To overcome these issues and achieve devices of high current switching capabilities, thyristors were designed and fabricated for the purpose of wafer-scale interconnection - which avoids the need of dicing and bonding and can achieve significant current density improvement over the paralleled diced device approach. Discrete thyristors fabricated for interconnection exhibited excellent yields and good uniformity of both blocking and on-state characteristics, showing great promise for large-scale interconnection.

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Mlynarczuk, J., R. Amarowicz e J. Kotwica. "Effect of polychlorinated biphenyls (Aroclor-1248) on the secretory function of bovine luteal cells affected by LH, noradrenaline and high density lipoproteins". Veterinární Medicína 48, No. 10 (30 de março de 2012): 267–74. http://dx.doi.org/10.17221/5779-vetmed.

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The corpus luteum (CL), formed from the ruptured follicle, is required for the course of normal cyclicity and the duration of pregnancy in females. The influence of a mixture of polychlorinated biphenyls – PCBs (Aroclor-1248) – on the secretory function of CL (dispersed bovine luteal cells) during different stages of the estrous cycle was studied. The cells (1.2 × 105/ml) were pre-incubated for 24 h and were then treated with 10, 100 or 500 ng/ml of PCBs. A􀄞er 24, 48, 72, 96 or 144 h luteinizing hormone (LH; 100 ng/ml; positive control) was added to the medium. The most evident impaired secretion of progesterone was measured after 72 h of incubation with PCBs and this time was selected for the further experiments. In Exp. 2 high density lipoproteins (HDL), as a source of cholesterol (25 μg), increased progesterone secretion from luteal cells; PCBs enhanced this effect in mid and late stage of the estrous cycle. PCBs had no effect on the stimulatory influence of LH, which itself stimulated progesterone secretion. In Exp. 3 PCBs (500 ng/ml) decreased progesterone secretion from the early CL and increased stimulatory effect of noradrenaline (NA) on progesterone secretion from mid CL. Aroclor-1248 stimulated oxytocin (OT) secretion from all stages of CL development. NA alone increased OT secretion from mid and late CL and moreover, it amplified effect by Aroclor on CL from all studied stages of their development. We conclude that the mixture of PCBs, commercially available as Aroclor-1248, can directly impair the function of bovine CL and thus it can affect the estrous cycle duration or embryo development.

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Bao, Wen-Tao, Bin-Zhang Fu, Ming-Yu Chen e Li-Xin Zhang. "A High-Performance and Cost-Efficient Interconnection Network for High-Density Servers". Journal of Computer Science and Technology 29, n.º 2 (março de 2014): 281–92. http://dx.doi.org/10.1007/s11390-014-1430-0.

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Kondo, Kazuo, Kunio Shinohara e Keisuke Fukui. "Shape Evolution of High density Interconnection Bumps Used For Microprocessor." KAGAKU KOGAKU RONBUNSHU 22, n.º 3 (1996): 534–41. http://dx.doi.org/10.1252/kakoronbunshu.22.534.

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Wang, Hongjie, Weidong Huang, Fei Geng, Yuan Lu, Bo Zhang, Wen Yin e Haidong Wang. "A cost effective PoP structure with high I/O density". Additional Conferences (Device Packaging, HiTEC, HiTEN, and CICMT) 2014, DPC (1 de janeiro de 2014): 000768–85. http://dx.doi.org/10.4071/2014dpc-tp15.

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Package-on-package (PoP) structure is widely used in smart phones and tablets in which memory package is directly attached to the top of the application processor. As the market demands more speed and bandwidth, memory devices need more than 1000 I/Os to support future requirements. However← since the package size also becomes smaller and smaller, finer I/O pitch is absolutely required. Although using some new technology can achieve finer I/O pitch, it increases the manufacturing cost. Using traditional mature technology can reduce manufacturing cost, but has limitation in finer I/O pitch. So, it demands a reasonable balance between design, process and cost to develop an applicable PoP structure. In this paper we proposed a novel and cost effective PoP interconnection structure and a multi-layer PoP model. The PoP interconnection was formed by the solder ball on the top package connected to the solder bumps on the bottom package. The solder bump was made of a smaller solder ball attached on a Cu stud bump on the top of bottom substrate. The Cu stud bump was made through wire bonding machines and was coined so that the small solder ball can be attached to it. Using film assist molding technology, a half of the solder ball is exposed outside of molding compound, which can be connected with the solder ball of the top package through reflow process. This PoP interconnection structure was named solder bump through molding (BTM). A three layer PoP vehicle package was designed in our experiments. The top package was a wire bonding BGA, the middle and bottom packages were both flip chip BGA with BTM interconnection structure. The package size of these three packages was 10×10mm2 and ball pitch was 0.4mm. The assembly process of top package was as normal as other wire bonding BGA. The assembly processes of middle and bottom packages were as follows: The Cu stud bumps were first bonded to the top surface of the substrate using wire bonding machines. Small solder balls were attached to the top of Cu stud bumps using stencil tool and then reflowed. After solder bumps were made, all chips were flip bonded to the substrates. Then, using film assist molding and MUF technology, the chips were encapsulated and Cu stud bumps were half exposed. After all the packages were ready, the package stacking and reflow was performed one by one from top to the bottom and the overall three layer PoP was formed. C-scan test and cross section analysis showed that the encapsulation had no voids in most samples. Electrical test results showed the interconnection was good. Reliability study will be also discussed in this paper, which is still in research now. In BTM structure, both Cu stud and solder ball attach can be easily realized. The ball pitch can be 0.4mm or smaller and the process is also applicable for more layer PoP. Thus, BTM PoP structure provides a good solution considering the balance among cost, performance and manufacturing for 3D package. Acknowledgments The authors acknowledge the support of National Science and Technology Major Project (Project numberï¼š2013ZX02501003).

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Fjelstad, Joseph, Konstantine Karavakis e Belgacem Haba. "Manufacture of high density interconnection substrates by co‐lamination of inner layers and programmed interconnection joining layers". Circuit World 25, n.º 3 (setembro de 1999): 9–12. http://dx.doi.org/10.1108/03056129910268927.

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Ohta, Koushi, Kiyokazu Yasuda, Michiya Matsushima e Kozo Fujimoto. "Numerical Analysis of Self-Organizing Interconnection Process by 3 Dimensional Flow Dynamics". Solid State Phenomena 124-126 (junho de 2007): 543–46. http://dx.doi.org/10.4028/www.scientific.net/ssp.124-126.543.

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The growing importance of high integration on electronics demands novel interconnection methods replacing high-cost solder bumping or less reliable conductive adhesives. Self-organizing interconnection process using resin containing solder fillers has a possibility to achieve high-density joints satisfying both needs. Numerical study visualized the process and revealed that surface tension of molten fillers and resin viscosity determine the speed of conductive path formation.

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ODAIRA, Hiroshi, Kenji SASAOKA, Eiji IMAMURA e Kazuyasu TANAKA. "Development of High Density PWB by a New Layer Interconnection Method." Journal of Japan Institute for Interconnecting and Packaging Electronic Circuits 11, n.º 2 (1996): 106–12. http://dx.doi.org/10.5104/jiep1995.11.106.

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Pfistner, P., T. Blank, M. Caselle, P. F. v. Wintzingerode, M. Weber, J. M. Heuser e C. J. Schmidt. "Novel high-density interconnection technology for the CBM Silicon Tracking System". Journal of Instrumentation 14, n.º 09 (30 de setembro de 2019): P09027. http://dx.doi.org/10.1088/1748-0221/14/09/p09027.

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Chakravorty, K. K., C. P. Chien, J. M. Cech, M. H. Tanielian e P. L. Young. "High-density interconnection using photosensitive polyimide and electroplated copper conductor lines". IEEE Transactions on Components, Hybrids, and Manufacturing Technology 13, n.º 1 (março de 1990): 200–206. http://dx.doi.org/10.1109/33.52871.

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Choi, Choon-Gi, Sang-Pil Han e Myung-Yung Jeong. "Two-dimensional polymeric optical waveguides for high-density parallel optical interconnection". Optics Communications 235, n.º 1-3 (maio de 2004): 69–73. http://dx.doi.org/10.1016/j.optcom.2004.02.078.

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Song, In-Hyouk, e Taehyun Park. "Connector-Free World-to-Chip Interconnection for Microfluidic Devices". Micromachines 10, n.º 3 (27 de fevereiro de 2019): 166. http://dx.doi.org/10.3390/mi10030166.

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In the development of functional lab-on-a-chip (LOC), there is a need to produce a reliable and high pressure connection between capillary tubes and microfluidic devices for carrying fluids. The current technologies still have limitations in achieving ideal interconnection since they are bulky, expensive or complicated. In this paper, a novel connector-free technique using an interference fit mechanism is introduced for world-to-chip interconnection. The proposed technique has considerable potential for replacing current interconnection tools for microfluidic devices due to the advantages including no chemical contamination, easy plugging, enough strength to sustain pressure, high density integration, simple and rapid integration.

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DISHON, G. J., S. M. BOBBIO, M. A. PENNINGTON, R. F. LIPSCOMB, N. KOOPMAN e S. NANGALIA. "Micro-Interconnection Technology. Fluxless Flip Chip Solder Joining for High Density Interconnect." Journal of Japan Institute for Interconnecting and Packaging Electronic Circuits 10, n.º 6 (1995): 390–93. http://dx.doi.org/10.5104/jiep1995.10.390.

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Buck, T. J. "Advanced Discrete Wiring Technology: A Solution for High Density Sub‐nanosecond Interconnection". Circuit World 14, n.º 2 (janeiro de 1988): 4–10. http://dx.doi.org/10.1108/eb043946.

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Blumbergs, Ervins, Vera Serga, Andrei Shishkin, Dmitri Goljandin, Andrej Shishko, Vjaceslavs Zemcenkovs, Karlis Markus, Janis Baronins e Vladimir Pankratov. "Selective Disintegration–Milling to Obtain Metal-Rich Particle Fractions from E-Waste". Metals 12, n.º 9 (1 de setembro de 2022): 1468. http://dx.doi.org/10.3390/met12091468.

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Various metals and semiconductors containing printed circuit boards (PCBs) are abundant in any electronic device equipped with controlling and computing features. These devices inevitably constitute e-waste after the end of service life. The typical construction of PCBs includes mechanically and chemically resistive materials, which significantly reduce the reaction rate or even avoid accessing chemical reagents (dissolvents) to target metals. Additionally, the presence of relatively reactive polymers and compounds from PCBs requires high energy consumption and reactive supply due to the formation of undesirable and sometimes environmentally hazardous reaction products. Preliminarily milling PCBs into powder is a promising method for increasing the reaction rate and avoiding liquid and gaseous emissions. Unfortunately, current state-of-the-art milling methods also lead to the presence of significantly more reactive polymers still adhered to milled target metal particles. This paper aims to find a novel and double-step disintegration–milling approach that can provide the formation of metal-rich particle size fractions. The morphology, particle fraction sizes, bulk density, and metal content in produced particles were measured and compared. Research results show the highest bulk density (up to 6.8 g·cm−3) and total metal content (up to 95.2 wt.%) in finest sieved fractions after the one-step milling of PCBs. Therefore, about half of the tested metallic element concentrations are higher in the one-step milled specimen and with lower adhered plastics concentrations than in double-step milled samples.

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Chen, Chi-Han, Kuan-Chung Lu, Chang-Ying Hung, Pao-Nan Lee, Meng-Jen Wang, Chih-Pin Hung, Ho-Ming Tong e Tzyy-Sheng Horng. "GHz High Frequency TSV for 2.5D IC Packaging". International Symposium on Microelectronics 2012, n.º 1 (1 de janeiro de 2012): 001215–20. http://dx.doi.org/10.4071/isom-2012-thp62.

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TSV (Through Silicon Via) is the key enabling technology for 2.5D & 3D IC stacking solution in FCBGA (Flip Chip Ball Grid Array). As the 2.5D interposer design pushing toward smaller & shorter via due to high I/O density and high frequency requirement, the electrical performance of thinner interposer is therefore much more challenging in low signal loss performance for high frequency application and process. From the structure point of view, the silicon interposer is an additive layer between top side chip(s) and bottom side substrate, it is therefore an additional electrical interconnection which affects the signal propagation between chip(s) and substrate. Therefore, the performance of the TSV insertion loss in silicon interposer becomes critical, especially for above GHz application. Real measurement is conducted to validate the electrical performance of TSV interconnection up to 67GHz, and the wideband scalable model of TSV is also proposed and compared with the measured data. The measurement of this TSV structure has demonstrated the advantages with low parasitic capacitance and low insertion loss at high frequency. Full validated reliability test is also presented to verify interposer fabrication, assembly process optimization, and interconnection stability of the 2.5D IC package.

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Das, Rabindra, J. M. Lauffer e F. D. Egitto. "Versatile Z-Axis Interconnection for High Performance Electronics". Additional Conferences (Device Packaging, HiTEC, HiTEN, and CICMT) 2013, DPC (1 de janeiro de 2013): 001033–50. http://dx.doi.org/10.4071/2013dpc-wa13.

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The demand for high-performance, lightweight, portable computing power for next generation packaging is driving the industry toward miniaturization at a rate not seen before. Electronic packaging is evolving to meet the demands of higher functionality in ever smaller packages. To accomplish this, new packaging needs to be able to integrate more dies with greater function, higher I/O counts, smaller die pad pitches, and greater heat densities, while being pushed into smaller and smaller footprints. New packaging designs are emerging that require joining (stacking) of multiple packages, joining of different size packages, and flexibility and/or rigidity to accommodate requirements related to size, weight, and complexity. This paper presents a novel Z-axis interconnect approach for extending performance beyond the limits imposed by traditional approaches. Specifically, metal-to-metal z-axis electrical interconnection among substrates (sub-composites) of the same or varying size, or among flexible and rigid elements (rigid-flex), to form a single structure is described. The structure employs an electrically conductive medium to interconnect thin coreless substrates. The substrates are built in parallel, aligned, and laminated to form a variety of multilayer, high density structures including rigid, rigid-rigid, rigid-flex, stacked packages, or RF substrates. The Z-interconnect based structures offer many advantages over more conventional build-up technologies, for example, an increase in metal layer counts without the cumulative yield loss of sequential (build up) processing, placement of flex elements into any layer of the substrate, the opportunity for multiple flex layers within a rigid-flex substrate, the ability to connect multiple multilayer substrates of varying size, and the ability to connect between any two arbitrary metal layers within the rigid region without the use of plated through holes (PTHs), allowing for increased wiring density, and reduction or elimination of via stubs that cause signal attenuation, In addition, multilayer rigid-flex packages for a variety of applications are being developed. Several classes of flexible materials that can be used to form high-performance flexible packaging are discussed. Materials, including polyimides, PTFE, liquid crystal polymer (LCP), have been used to develop multilayer rigid-flex packages. The process allows fabrication of Z-interconnect conductive joints having diameters in the range of 55–500 microns. Via or component pitches down to 150 microns have been demonstrated. The processes and materials used to achieve smaller feature dimensions, satisfy stringent registration requirements, and achieve robust electrical interconnections are discussed. A number of RF structures have been designed and built with Z-interconnect technology, affording the flexibility to place wide signals, narrow signals and grounds and clearances only where needed. Electrically, S-parameter measurements revealed low loss at multi-gigahertz frequencies and the insertion loss for narrow, short lines and wide, long lines are similar. The electrically conductive adhesive used to form Z-interconnect shows good signal transmission to 25GHz. Z-interconnect substrates provide unique solutions for next generation complex packaging. Collectively, the results suggest that Z-interconnect technology may be attractive for a range of applications, not only where miniaturization is required, such as consumer products, but also in high performance large-area microelectronics such as supercomputers, radio frequency structures, etc.

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Cho, James S. H., Ho-Kyu Kang, S. Simon Wong e Yosi Shacham-Diamand. "Electroless Cu for VLSI". MRS Bulletin 18, n.º 6 (junho de 1993): 31–38. http://dx.doi.org/10.1557/s0883769400047308.

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Interconnection technology is a key factor in the continual advancement of integrated systems. The rapid increase in device density and circuit complexity through scaling demands a similar increase in the interconnection density. Traditionally, this is achieved by reducing the metal pitch as well as gradually increasing the number of interconnection levels. As the width and spacing of interconnections are scaled down to submicron dimensions at the chip level and micron dimensions at the board level, signal delay, crosstalk, electromigration, and stress-induced migration become important concerns.Cu holds promise as an alternative metallization material to Al alloy due to its low resistivity and ability to reliably carry high-current densities. Cu has a bulk resistivity of 1.68 μΩ-cm, whereas Al has a bulk resistivity of 2.65 μΩ-cm. The only metal with a resistivity lower than Cu is Ag. Since Cu has a melting point and atomic weight both higher than Al, it is expected to have better resistance to electromigration, although properties such as grain structure and resistance to corrosion at high temperatures may also affect electromigration characteristics.

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Xiong, Zhijiang. "A Design of Bare Printed Circuit Board Defect Detection System Based on YOLOv8". Highlights in Science, Engineering and Technology 57 (11 de julho de 2023): 203–9. http://dx.doi.org/10.54097/hset.v57i.10002.

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As electronic products develop towards miniaturization and digitization, printed circuit boards (PCBs) also develop towards high density and high precision. In the manufacturing process of PCBs, some PCBs with defects will be produced, and these defects often lead to circuit failure, so defect detection technology is an indispensable part of PCB manufacturing technology. Aiming at the problems of low efficiency and accuracy of traditional image recognition and classification technology, A PCB defect detection algorithm is proposed based on YOLOv8 in this paper. For these five PCB defects, the neural network in deep learning was used to identify and classify PCB defects. The prediction accuracy of YOLOv8 model after training is close to 97%, and it is compared with the accuracy of other algorithms to prove the effectiveness and feasibility of the model. In addition, the object detection image user interface is also established in this paper, which can realize image detection more conveniently.

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Lan, Kuibo, Zhihui Pei, Yibo Zhang, Kailiang Zhang, Xuejiao Chen e Guoxuan Qin. "Investigation on growth and electronic characteristics of vertical carbon nanotubes". Modern Physics Letters B 33, n.º 04 (10 de fevereiro de 2019): 1950042. http://dx.doi.org/10.1142/s0217984919500428.

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Carbon nanotubes (CNTs) as interconnects in integrated circuits (ICs) which are vertically aligned in growth with high tube density and long tube length are required. In this paper, we present a method to improve the height of CNTs. High-resolution transmission electron microscopic (TEM) images confirm CNTs top growth mode. By cutting and modifying the top of CNTs, the influences of different radii of apertures on interconnect resistance were studied. According to the analysis, we proposed a novel growth mechanism to improve growth height of CNTs interconnection structure and the top contact resistances of pre-cutting and post-cutting CNTs interconnection structure were forecasted. The result demonstrates that the electronic performances of the post-cutting CNTs interconnection structure with platinum (Pt)-protected layer are better than the ones of pre-cutting CNTs interconnection structure. The resistivity of the post-cutting CNTs interconnection structure with Pt-protected layer is [Formula: see text], which is much less than that of post-cutting CNTs interconnect structure [Formula: see text]. In what follows, the resistance of the contacted area of pre-cutting CNTs interconnection structure is 31 [Formula: see text], which is much less than that of post-cutting CNTs interconnection structure 439 [Formula: see text]. This constitutes a significant step to realize longer CNTs interconnects with complementary metal oxide semiconductor (CMOS) contact modules.

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Cai, Jiawei, Long Zhang, Yingzhuo Huang, Pengrong Lin e Quanbin Yao. "Simulation analysis of a specification package for high density and high voltage power module". Journal of Physics: Conference Series 2383, n.º 1 (1 de dezembro de 2022): 012093. http://dx.doi.org/10.1088/1742-6596/2383/1/012093.

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A novel packaging designing for high density and high voltage power module, namely TPak was proposed. It uses flip-chip welding technology and through-hole technology to avoid the parasitic parameters introduced by wire bonding in traditional electrical interconnection, so that the proposed efficiency of the entire high-voltage module is close to 100%, parasitics are reduced by an order of magnitude, and module manufacturing is simplified and the module mechanical stress capability is improved. The finite element simulation anakysis of heat and force are carried out by means of simulation software, and the problems existing in the current Tpak packaging are analyzed from the perspective of materials, and improvement methods are proposed to optimize performance and improve its reliability.

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Berglund, Olof, Per Nyström e Per Larsson. "Persistent organic pollutants in river food webs: influence of trophic position and degree of heterotrophy". Canadian Journal of Fisheries and Aquatic Sciences 62, n.º 9 (1 de setembro de 2005): 2021–32. http://dx.doi.org/10.1139/f05-115.

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We investigated how the degree of autotrophy/heterotrophy and organism trophic position influenced the bioaccumulation of polychlorinated biphenyls (PCBs) in 10 benthic river food webs consisting of terrestrial detritus, periphyton, invertebrates, and age-0 brown trout (Salmo trutta) in southern Sweden. Concentrations of PCBs increased with trophic position, estimated from δ15N and δ13C, on a dry weight basis (ng·g1 dry weight) but not on a lipid weight basis (ng·g1 lipid). PCB biomagnification factors between the first and second trophic levels (invertebrates/ periphyton and invertebrates/detritus) ranged between 0.3 and 2.3 and between the second and third levels (trout/invertebrates) between 0.3 and 2.0 on a lipid weight basis. The mean proportion of carbon ultimately derived from terrestrial sources, α, was 0.82 ± 0.19 for invertebrates and 0.67 ± 0.28 for trout. Contrary to our hypothesis, PCB concentrations in trout were positively related to α (r2 = 0.580.77, p < 0.05). As α and the periphyton density (g C·m2) in the rivers was positively related (r2 = 0.88, p < 0.01), we propose that this relationship was due to an increased retention and exposure of PCBs to trout in rivers with low grazing pressure and high periphyton density.

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Huang, Guoping, Hao Zhuang, Honglie Shen, Yashuai Jiang, Guan Sun, Xueliang Bai e Jingnan Li. "Study of novel high-density solar panels based on small space interconnection technology". E3S Web of Conferences 260 (2021): 03007. http://dx.doi.org/10.1051/e3sconf/202126003007.

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Small space interconnection technology (SSIT) has been utilized in solar panels recently. The application of this technology can further increase the module efficiency. However, higher power decay after long-time operation may occur due to additional risk. Therefore, in this paper, damp heat (DH), thermal cycle (TC), UV irradiation and humidity freezing (HF) tests were utilized to study the weatherability performance of SSIT-based high-density solar panels fabricated with cells cut by two different techniques. The achieved data suggest that the novel high-density modules with small space between cells have good reliability in various weather conditions. The novel low-damage laser-induced cutting technique is beneficial for the improvement of module reliability.

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Morikawa, Yasuhiro. "Plasma Dry Process Technology for High-Density Interconnection on 2D Panel Substrate Packaging". Journal of Japan Institute of Electronics Packaging 20, n.º 4 (2017): 185–91. http://dx.doi.org/10.5104/jiep.20.185.

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Kondo, Kazuo, Mitsunori Yokoyama e Keisuke Fukui. "Computation Transport Phenomena in Chemical Engineering. Shape Evolution of High Density Interconnection Bumps." KAGAKU KOGAKU RONBUNSHU 23, n.º 6 (1997): 780–88. http://dx.doi.org/10.1252/kakoronbunshu.23.780.

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Strazzella, Arianna, Alice Ossoli e Laura Calabresi. "High-Density Lipoproteins and the Kidney". Cells 10, n.º 4 (31 de março de 2021): 764. http://dx.doi.org/10.3390/cells10040764.

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Dyslipidemia is a typical trait of patients with chronic kidney disease (CKD) and it is typically characterized by reduced high-density lipoprotein (HDL)-cholesterol(c) levels. The low HDL-c concentration is the only lipid alteration associated with the progression of renal disease in mild-to-moderate CKD patients. Plasma HDL levels are not only reduced but also characterized by alterations in composition and structure, which are responsible for the loss of atheroprotective functions, like the ability to promote cholesterol efflux from peripheral cells and antioxidant and anti-inflammatory proprieties. The interconnection between HDL and renal function is confirmed by the fact that genetic HDL defects can lead to kidney disease; in fact, mutations in apoA-I, apoE, apoL, and lecithin–cholesterol acyltransferase (LCAT) are associated with the development of renal damage. Genetic LCAT deficiency is the most emblematic case and represents a unique tool to evaluate the impact of alterations in the HDL system on the progression of renal disease. Lipid abnormalities detected in LCAT-deficient carriers mirror the ones observed in CKD patients, which indeed present an acquired LCAT deficiency. In this context, circulating LCAT levels predict CKD progression in individuals at early stages of renal dysfunction and in the general population. This review summarizes the main alterations of HDL in CKD, focusing on the latest update of acquired and genetic LCAT defects associated with the progression of renal disease.

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Park, Ji-Su, Won-Je Oh, Jang-Hun Joo, Jun-Sin Yi, Byung-You Hong e Jae-Hyeong Lee. "Design of High-Power and High-Density Photovoltaic Modules Based on a Shingled Cell String". Journal of Nanoscience and Nanotechnology 20, n.º 11 (1 de novembro de 2020): 6996–7001. http://dx.doi.org/10.1166/jnn.2020.18837.

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Building-integrated photovoltaic (BIPV) arrays, which are installed on the roofs of buildings as part of urban solar power generation, have created a demand for high-power and high-density photovoltaic (PV) modules to produce high-output power in a limited area. In this paper, a high-power PV module using a shingles technology is designed. When the vertical and horizontal dimensions of the module were 201.78 cm × 96.75 cm in the same area as that of the conventional PV module, the number of cell strips reached 390. When six 65-interconnection shingled strings were connected in series, the output power of 367.8 W was achieved. Compared with a conventional PV module of the same area, the output power was 8% greater.

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Partsinevelou, Aikaterini-Sofia. "Using the SWAT model in analyzing hard rock hydrogeological environments. Application in Naxos Island, Greece." Bulletin of the Geological Society of Greece 51 (4 de outubro de 2017): 18. http://dx.doi.org/10.12681/bgsg.11960.

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The main parameter that controls the groundwater flow regime in fractured aquifers is the fracture pattern. Its description is crucial for a hydrogeological study, as the hydraulic properties of hard rocks are mainly controlled by fracturing. The parameters of the fracture pattern that were analyzed in the study area were the frequency and spatial location of the fractures, the density of fractures and the degree of fracture intersection.Furthermore, a straight link between the fracture pattern and the hydrological conditions is important for a first analysis of the potential groundwater zones and their vulnerability in hard rock environments. To study this link, the SWAT hydrology model was applied in the study area. Using suitable territorial and meteorological data, the model simulates the parameters of the hydrological balance in each catchment of the hydrographical network.The analysis of the fracture pattern revealed that the fragmentation in all lithologies is characterized by high degree of uniformity. Very high density and interconnection density of the fractures are observed in areas where the alternations between different lithologies are very intense. Also the application of the SWAT model showed that the calculated hydrological parameters could be related to the fracture pattern, as high infiltration rates occur in areas where the density and the degree of interconnection of the fractures are also high.

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Zhang, Fang-Li, Xing-Jian Yang, Xiu-Ling Xue, Xue-Qin Tao, Gui-Ning Lu e Zhi Dang. "Estimation ofn-Octanol/Water Partition Coefficients (log KOW) of Polychlorinated Biphenyls by Using Quantum Chemical Descriptors and Partial Least Squares". Journal of Chemistry 2013 (2013): 1–8. http://dx.doi.org/10.1155/2013/740548.

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Then-octanol/water partition coefficient (log KOW) is a useful parameter for the assessment of the environmental fate and impact of xenobiotic trace contaminants. Quantitative structure-activity relationship (QSAR) model for log KOWof polychlorinated biphenyls (PCBs) was analyzed by using the density functional theory at B3LYP/6-31G(d) level and the partial least squares (PLS) method with an optimizing procedure. A PLS model with reasonably good coefficient (R2=0.992) and cross-validation test (Q2cum=0.988) values was obtained. All the predicted values are within the range of±0.3log unit from the observed values. The log KOWvalues of 7 PCBs in the test set predicted by the model are very close to those observed, indicating that this model has high fitting precision and good predictability. The PLS analysis showed that PCBs with larger electronic spatial extent and lower molecular total energy values tend to be more hydrophobic and lipophilic.

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