Literatura científica selecionada sobre o tema "High density interconnection PCBs"
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Artigos de revistas sobre o assunto "High density interconnection PCBs"
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Cauwe, Maarten, Bart Vandevelde, Chinmay Nawghane, Marnix Van De Slyeke, Erwin Bosman, Joachim Verhegge, Alexia Coulon e Stan Heltzel. "High-Density Interconnect Technology Assessment of Printed Circuit Boards for Space Applications". Journal of Microelectronics and Electronic Packaging 17, n.º 3 (1 de julho de 2020): 79–88. http://dx.doi.org/10.4071/imaps.1212898.
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Abstract High-density interconnect (HDI) printed circuit boards (PCBs) and associated assemblies are essential to allow space projects to benefit from the ever increasing complexity and functionality of modern integrated circuits such as field-programmable gate arrays, digital signal processors and application processors. Increasing demands for functionality translate into higher signal speeds combined with an increasing number of input/outputs (I/Os). To limit the overall package size, the contact pad pitch of the components is reduced. The combination of a high number of I/Os with a reduced pitch places additional demands onto the PCB, requiring the use of laser-drilled microvias, high-aspect ratio core vias, and small track width and spacing. Although the associated advanced manufacturing processes have been widely used in commercial, automotive, medical, and military applications, reconciling these advancements in capability with the reliability requirements for space remains a challenge. Two categories of the HDI technology are considered: two levels of staggered microvias (basic HDI) and (up to) three levels of stacked microvias (complex HDI). In this article, the qualification of the basic HDI technology in accordance with ECSS-Q-ST-70-60C is described. At 1.0-mm pitch, the technology passes all testing successfully. At .8-mm pitch, failures are encountered during interconnection stress testing and conductive anodic filament testing. These failures provide the basis for updating the design rules for HDI PCBs.
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Bernhard, T., L. Gregoriades, S. Branagan, L. Stamp, E. Steinhäuser, R. Schulz e F. Brüning. "Nanovoid Formation at Cu/Cu/Cu Interconnections of Blind Microvias: A Field Study". International Symposium on Microelectronics 2019, n.º 1 (1 de outubro de 2019): 000492–502. http://dx.doi.org/10.4071/2380-4505-2019.1.000492.
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Abstract A key factor for a high electrical reliability of multilayer High Density Interconnection Printed Circuit Boards (HDI PCBs) is the thermomechanical stability of stacked microvia interconnections. With decreasing via sizes and higher numbers of interconnected layers, the structural integrity of these interconnections becomes a critical factor and is a topic of high interest in current research. The formation of nanovoids and inhibited Cu recrystallization across the interfaces are the two main indications of a weak link from the target pad to the filled via. Based on TEM/EDX measurements on a statistically relevant number of stacked and blind microvias produced in the industrial field, different types of nanovoid phenomena are revealed at the Cu/Cu/Cu junction. The types of nanovoids were categorized relating to the time of appearance (before or after thermal treatment), the affected interfaces or layers and the impact on the Cu recrystallization. The main root causes for each void type are identified and the expected impact on the thermomechanical stability of the via junction is discussed.
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Petrosyants, Konstantin O., e Anton A. Popov. "Experimental Investigation of Temperature-Current Rise in Fine PCB Copper Traces on Polyimide, Aluminium and Ceramic (Al2O3) Substrates". Advanced Materials Research 739 (agosto de 2013): 155–60. http://dx.doi.org/10.4028/www.scientific.net/amr.739.155.
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Three types of copper traces for PCBs were investigated: 1) 2.5 μm thin film lines (Ti;Cu;Ni) on aluminium and ceramic (Al2O3) substrates; 2) 2.5 μm thin film lines (Ti;Cu;Ni;Au) on ceramic (Al2O3) substrates; 3) 15 μm traces (Cu;Ni) on polyimide substrate for high density interconnection PCBs. The width of all types of traces was varying in the range of 100-500 μm. The set of temperature-current diagrams for different PCB scenarios are presented and analyzed. The temperature caused by Joule heating was measured using IR camera Flir A40 with macrolens. For different cases the current was set in the range of 0.1-3 A; the measured temperature was in the range of 20-140 °C. The close agreement between the results measured and simulated with ELCUT software tool was achieved.
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Ji, Linxian, Chong Wang, Shouxu Wang, Wei He, Dingjun Xiao e Ze Tan. "Multiphysics coupling simulation of RDE for PCB manufacturing". Circuit World 41, n.º 1 (2 de fevereiro de 2015): 20–28. http://dx.doi.org/10.1108/cw-09-2014-0037.
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Purpose – The purpose of this paper is to optimize experimental parameters and gain further insights into the plating process in the fabrication of high-density interconnections of printed circuit boards (PCBs) by the rotating disc electrode (RDE) model. Via metallization by copper electrodeposition for interconnection of PCBs has become increasingly important. In this metallization technique, copper is directly filled into the vias using special additives. To investigate electrochemical reaction mechanisms of electrodeposition in aqueous solutions, using experiments on an RDE is common practice. Design/methodology/approach – An electrochemical model is presented to describe the kinetics of copper electrodeposition on an RDE, which builds a bridge between the theoretical and experimental study for non-uniform copper electrodeposition in PCB manufacturing. Comsol Multiphysics, a multiphysics simulation platform, is invited to modeling flow field and potential distribution based on a two-dimensional (2D) axisymmetric physical modeling. The flow pattern in the electrolyte is determined by the 2D Navier–Stokes equations. Primary, secondary and tertiary current distributions are performed by the finite element method of multiphysics coupling. Findings – The ion concentration gradient near the cathode and the thickness of the diffusion layer under different rotating velocities are achieved by the finite element method of multiphysics coupling. The calculated concentration and boundary layer thicknesses agree well with those from the theoretical Levich equation. The effect of fluid flow on the current distribution over the electrode surface is also investigated in this model. The results reveal the impact of flow parameters on the current density distribution and thickness of plating layer, which are most concerned in the production of PCBs. Originality/value – By RDE electrochemical model, we build a bridge between the theoretical and experimental study for control of uniformity of plating layer by concentration boundary layer in PCB manufacturing. By means of a multiphysics coupling platform, we can accurately analyze and forecast the characteristic of the entire electrochemical system. These results reveal theoretical connections of current density distribution and plating thickness, with controlled parameters in the plating process to further help us comprehensively understand the mechanism of copper electrodeposition.
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Avitabile, Gianfranco, Antonello Florio, Vito Leonardo Gallo, Alessandro Pali e Lorenzo Forni. "An Optimization Framework for the Design of High-Speed PCB VIAs". Electronics 11, n.º 3 (6 de fevereiro de 2022): 475. http://dx.doi.org/10.3390/electronics11030475.
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Signal integrity represents a key issue in all modern electronic systems, which are strongly dominated by the extreme component density usually employed on PCBs and the associated increase in the interconnection density. The use of multi-layer structures with microstrips connected by various types of Vertical Interconnect Accesses (VIAs) calls for design strategies that reduce the impedance mismatch and signal attenuation. The paper proposes a thorough analysis of the effects associated with the VIA geometry and presents a parametric evaluation of them. The obtained results represent the starting point for a possible design procedure that manages the geometric aspects of differential VIAs, aiming to optimize their electrical performance while reducing their occupation of PCB area. The optimization technique considers a differential VIA as a four-port circuit whose characteristics are evaluated with suitable Figures of Merit (FoMs), thus striving for an optimal design obtained with closed-loop iterations. The analysis is performed in both the time (TDR: Time-Domain Reflectometry) and frequency domains (S and Z parameters), thus allowing a dramatic reduction in the number of cases to be analyzed. The procedure is thoroughly described and validated using simulation results.
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Bernhard, T., S. Branagan, R. Schulz, F. Brüning, L. Stamp, K. Wurdinger e S. Kempa. "The Formation of Nano-voids in electroless Cu Layers". MRS Advances 4, n.º 41-42 (2019): 2231–40. http://dx.doi.org/10.1557/adv.2019.336.
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ABSTRACTThe electrical reliability of multilayer high density interconnection printed circuit boards (HDI-PCBs) is mainly affected by the thermo-mechanical stability of stacked micro via interconnections. Here, a critical failure mode is the stress related crack between the electrolytically filled via and the target pad, commonly known as target pad separation. The junction includes two Cu-Cu-interfaces, one between the target Cu pad and the thin electroless Cu layer and the second between electroless Cu and electrolytic Cu. In this paper we will show that state-of-the-art electroless Cu plating processes are able to provide solid, completely recrystallized and highly reliable stacked via junctions. Defect free interfaces were achieved by using ionic Pd-activators and electroless Cu baths with a cyanide based stabilizer system. Cyanide free electroless Cu baths tend more to the formation of nanometer sized defects, discovered via Transmission Electron Microscopy (TEM). In this case a precise adjustment of single stabilizer components is mandatory to achieve defect free layers. The defects are hollow and were identified as “nano voids”. A critical density of these nano voids weakens the interface, predefines the crack path and reduces the overall reliability of the junction. A precise localization of the nano voids within the junction was enabled by detecting the Ni-containing electroless Cu layer via TEM-Ni mapping. Slower volume exchange of the electroless Cu solution within the blind micro via (BMV) substantially increases the nano void density. The ability of nano voids to migrate and coalesce at elevated temperatures was investigated as well.
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He, Huirong, Jida Chen, Shengtao Zhang, Minhui Liao, Lingxing Li, Wei He, Yuanming Chen e Shijin Chen. "Fabrication and surface treatment of fine copper lines for HDI printed circuit board with modified full-additive method". Circuit World 43, n.º 3 (7 de agosto de 2017): 131–38. http://dx.doi.org/10.1108/cw-02-2017-0004.
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Purpose This paper aims to propose a modified full-additive method (MFAM) to fabricate fine copper lines for high density interconnection (HDI) printed circuit boards (PCBs). In addition, the surface of the fine copper lines is treated with a brown oxidation process to obtain good adhesion between the copper and the dielectric resin. Design/methodology/approach Fine copper lines fabricated by MFAM were observed to evaluate the undercut quality, in comparison to undercut quality of copper lines fabricated by the semi-additive method and the subtractive method. The effect of the thickness of the dry film on the quality of the copper plating was investigated to obtain the regular shape of fine lines. The fine copper lines treated with the brown oxidation process were also examined to generate a coarse surface microstructure to improve the adhesion between the copper and the dielectric resin. The cross section and surface of as-fabricated fine copper lines were characterized using an optical microscope, a scanning electron microscope and an atomic force microscope. Findings MFAM has the potential to fabricate high-performance fine copper lines for HDI PCBs. Undercut of as-fabricated fine copper lines could be prevented to meet the design requirement of impedance. In addition, fine copper lines exhibit enough adhesive force to laminate with dielectric resin after the brown oxidation process. Originality/value MFAM, with the advantages of high efficiency and being a facile process, is developed to fabricate high-quality fine copper lines for industrial HDI PCB manufacture.
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Shearer, Catherine, Ken Holcomb e Jim Haley. "Shrinking Package Footprint by Embedding Top-Side Real Estate Using Core-to-Core Joining". Additional Conferences (Device Packaging, HiTEC, HiTEN, and CICMT) 2015, DPC (1 de janeiro de 2015): 001982–2014. http://dx.doi.org/10.4071/2015dpc-tha22.
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The electronics industry trend continues to be to continually increase capability and performance within an existing or smaller footprint. Shoehorning all of the required components onto the exterior surface of the PCB has become an increasingly difficult puzzle. The use of stacked microvias instead of plated through holes and stacked ICs in various configurations has freed up some real estate. The use of ever smaller passive devices also saves space, but reintroduces old issues such as tombstoning. The ideal solution would be to provide ‘surface’ real estate within the architecture of the circuit board – like moving items from a desk to a bookshelf – by embedding components into the board. In this paper, an alternative strategy is presented for embedded components. Sub-PCB constructions are built and populated on both sides, and then are joined using an interposer with sintering conductive paste interconnects. Sintering paste z-axis interconnections have been successfully used in this type of core-to-core joining for many years. The combination of the sintering paste interconnect and an interposer element is the key to enabling this architecture. This manufacturing strategy presents a number of advantages. The board may be broken down into logical substructures such as high density, core or RF portions. Each of the sub-PCBs can be fabricated according to best manufacturing practices for that portion of the circuit board rather than trying to fabricate a single complicated board. Yield losses from sequential process steps and multiple laminations may be reduced. The embedded components may be assembled onto the sub-PCBs using conventional solder reflow technology. The component placement can facilitate point-of-source architecture for high electrical performance. The process flow and some laboratory demonstrations of this technique will be presented in this paper.
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Hübner, Henning, Christian Ohde e Dirk Ruess. "Upscaling panel size for Cu plating on FOPLP (Fan Out Panel Level Packaging) applications to reduce manufacturing cost". International Symposium on Microelectronics 2018, n.º 1 (1 de outubro de 2018): 000037–42. http://dx.doi.org/10.4071/2380-4505-2018.1.000037.
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Abstract Electrolytic metal deposition is a key process step in the manufacturing of vertical and horizontal interconnections used in today's PCBs and IC substrates on one hand and advanced packaging applications on the other hand. Historically both application areas were clearly defined and separated by different requirements in feature sizes and substrate formats. PCBs and IC substrates were based on organic large scale substrates with rather large features while advanced packaging technology is wafer based with the capability to incorporate fine features down to a few microns. The ever increasing demand of higher performance, lower cost and thinner end user devices like smartphones require intense developments and innovation in all areas of the electronic component design including the substrate and chip packaging. Latest manufacturing technologies in both areas like fan-out wafer level packaging and advanced substrates are constantly emerging and promise to be a critical piece to meet these requirements. As a consequence both areas are currently merging while creating a new application segment. This segment combines the request of small feature sizes with the manufacturability on large scale substrates. Obviously many of the traditional process technologies like plating and available equipment cannot be easily adopted and need certain developments, adaptions and improvements. In this respect, a key challenge in the area of electrolytic metal deposition is the combination of various challenging requirements: creation of feature sizes down to 2μm L/S with heterogeneous feature density on large substrates up to 600mm at excellent metal thickness uniformity and high plating speed. The paper presents latest studies and conclusions in critical performance areas of the plating process such as electrolyte fluid dynamics, impact of anode design, pulse reverse rectification and newly designed electrolytes. Finally latest test results of optimized process conditions will be discussed in detail with different feature sizes providing data of within die and within substrate uniformity. All tests are done on panel level, both organic and glass substrates. The latest findings and achievements of the discussed panel based plating process technology will support the industry to develop panel based packaging processes that meet both technical and commercial requirements.
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Katahira, Takayoshi, Ilkka Kartio, Hiroshi Segawa, Michimasa Takahashi e Katsumi Sagisaka. "Vertically high-density interconnection for mobile application". Microelectronics Reliability 46, n.º 5-6 (maio de 2006): 756–62. http://dx.doi.org/10.1016/j.microrel.2005.07.001.
Texto completo da fonteTeses / dissertações sobre o assunto "High density interconnection PCBs"
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Sahel, Faten. "Contribution à la modélisation du couplage entre les alimentations et les signaux sensibles dans les cartes électroniques à haute densité d'interconnexions". Electronic Thesis or Diss., Sorbonne université, 2022. http://www.theses.fr/2022SORUS053.
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Pour ses applications HPC (High Performance Computing), Atos conçoit des cartes électroniques ultra-denses, qui contiennent des processeurs fonctionnant à très fortes puissances, et des liens séries ultra-rapides. La densité de ces cartes induit un rapprochement inévitable entre des signaux sensibles, et des alimentations à découpage. Cette proximité entraine des phénomènes de couplage qui peuvent parfois être nuisibles au bon fonctionnement des systèmes électroniques constituants ces cartes. Un prototypage virtuel s’avère nécessaire afin de repérer par simulation les perturbations dues au couplage, et de vérifier l’efficacité des corrections nécessaires à apporter au système pour les réduire. Les outils de CAO actuels ne disposent pas d’application dédiée pour la modélisation de l’impact du fonctionnement d’une alimentation sur son environnement. Pour parer à cette lacune, on propose dans cette thèse une méthode de simulation robuste, permettant de modéliser fidèlement le couplage entre alimentations à découpage et des conducteurs avoisinants, sur des circuits imprimés à haute densité d’interconnexions. Cette méthode de simulation est d’abord développée sur un cas d’étude, avant d’être appliquée à un cas plus complexe. A travers ce prototypage virtuel, on parvient à simplifier l’identification du mode de couplage, et à tester les solutions pour le réduire, avant de les implémenterThe high-density interconnection boards that Atos develop for HPC (High Performance Computing) applications contain processors functioning at very high currents and low voltages, along with high-speed serial links. With HDI (High Density Interconnection) technology, fast switching power supplies create coupling noise on nearby sensitive signals, that can lead to errors in the transmitted data, and in the worst case, may result in a malfunctioning circuit. Therefore, virtual prototyping is required to verify the signals’ behaviour in transmission lines, detect the parasitic effects on sensitive signals due to crosstalk, and thus allowing necessary adjustments to be made to reduce the noise. Today’s EDA tools lack a dedicated application able to model the impact of power supplies on their neighbouring signals. In this thesis, we suggest a simulation method using existing EDA tools, that would allow the modelling of the coupling between power supplies and nearby conductors in HDI boards. The simulation method is first applied to a case study board, then to a more complex one. This virtual prototyping method simplifies the coupling mode detection and allows us to test solutions to reduce the coupling noise, prior to their implementation
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Liu, Wenduo. "Alternative structures for integrated electromagnetic passives". Diss., Virginia Tech, 2006. http://hdl.handle.net/10919/27419.
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The demand for high power density keeps driving the development of electromagnetic integration technologies in the field of power electronics. Based on planar homogeneous integrated structures, the mechanism of the electromagnetic integration of passives has been investigated with distributed-parameter models. High order modeling of integrated passives has been developed to investigate the electromagnetic performance. The design algorithm combining electromagnetic design and loss models has been developed to optimize and evaluate the spiral winding structure. High power density of 480 W/in3 has been obtained on the prototype.
Due to the structural limitation, the currently applied planar spiral winding structure does not sufficiently utilize the space, and the structure is mechanically vulnerable. The improvement on structures is necessary for further application of integrated passives. The goal of this research is to investigate and evaluate alternative structures for high-power-density integrated passives. The research covers electromagnetic modeling, constructional study, design algorithm, loss modeling, thermal management and implementation technology
The symmetric single layer structure and the stacked structure are proposed to overcome the disadvantages of the currently applied planar spiral winding structure. Because of the potential of high power density and low power loss, the stacked structure is selected for further research. The structural characteristics and the processing technologies are addressed.
By taking an integrated LLCT module as the study case, the general design algorithm is developed to find out a set of feasible designs. The obtained design maps are used to evaluate the constraints from spatial, materials and processing technologies for the stacked structure.
Based on the assumption of one-dimensional magnetic filed on the cross-section and linear current distribution along the longitudinal direction of the stacked structure, the electromagnetic field distribution is analyzed and the loss modeling is made. The experimental method is proposed to measure the loss and to verify the calculation.
The power loss in the module leads to thermal issues, which limit the processed power of power electronics modules and thus limit the power density. To further improve the power handling ability of the module, the thermal management is made based on loss estimation. The heat extraction technology is developed to improve the heat removal ability and further improve the power density of integrated passives.
The experimental results verify the power density improvement from the proposed stacked structure and the applied heat extraction technology. The power density of 1147 W/in3 (70 W/cm3) is achieved in the implemented LLCT module with the efficiency of 97.8% at output power of 1008W.Ph. D.
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Mota, Pinheiro Júlio. "Development of passive circuits in nanowire-membrane technology in millimeter wave frequencies : application to functionalized interposer". Thesis, Université Grenoble Alpes, 2020. http://www.theses.fr/2020GRALT024.
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Ce travail vise à développer des circuits passifs en ondes millimétriques dans l'interposeur appelé MnM - metallic nanowire-filled membrane. Cet interposeur s'inscrit dans le contexte où la miniaturisation des circuits passifs due à la haute fréquence de fonctionnement (environ supérieure à 10 GHz jusqu’à 300 GHz pour les ondes millimétriques) rend intéressante l'insertion de circuits passifs dans des technologies intégrées telles que le CMOS, mais qui en raison des limitations liées à la technologie ne présentent pas une qualité élevée, étant donc plus intéressant en termes de performance et de coût l'utilisation d'un substrat auxiliaire pour la conception de circuits passifs qui permet leur intégration avec des circuits actifs en technologie intégrée ; ce substrat est appelé interposeur. Pour le développement d'un bon interposeur, il est nécessaire qu'il présente des lignes de transmission et des vias de haute qualité. L'interposeur MnM est une membrane d'alumine à faible coût qui possède par sa fabrication des nanopores naturels pouvant être utilisés pour la croissance de nanofils de cuivre. Pour le développement de cet interposeur et la présentation des circuits passifs, le processus de fabrication est amélioré, l'accent étant mis sur la croissance des nanofils de manière localisée et sur le rendement de la fabrication. Le substrat est caractérisé électriquement pour l'extraction des pertes et sa constante diélectrique, dont on a constaté qu'elle était influencée par les nanopores. Avec l'amélioration du processus de fabrication, le voie de nanofils sont développés et leurs performances analysées dans le cadre d'une transition entre une face et une autre du substrat grâce à un modèle électrique lié à la disposition physique validée par les résultats des mesures. Pour le modèle électrique, une approche analytique et une autre matrice sont proposées, avec la vérification que cette voie se comporte comme une voie solide avec une conductance qui prend en compte le matériau des nanofils et leur densité surfacique. Il est vérifié que les voie de nanofils ont des performances de pointe, en plus de leurs dimensions telles que le rayon et l'espacement entre les voies sont faibles, dictées uniquement par la dimension minimale atteinte en photolithographie. Les inductions de type solénoïde à deux, trois, cinq et dix spires qui utilisent ces voies sont proposées et analysées, avec la proposition d'un modèle électrique, qui concerne sa disposition physique, à utiliser par les concepteurs. Ces inductances sont compactes en raison de la petite taille des voies de nanofils, et ont une fréquence de résonance élevée, 98 GHz pour l’inductances à deux spires. Enfin, un nouveau modèle électrique pour les lignes de transmission de type microruban avec un effet d'onde lente causé par les nanofils est proposé pour faciliter sa conception et sa simulation, car sa simulation électromagnétique présente un coût de calcul élevé. Ce même modèle est également utilisé pour les lignes de transmission en technologie PCB, qui présentent le même effet d'onde lente mais avec une fréquence de fonctionnement en micro-ondes. Ainsi, ce travail présente une avancée significative pour l'interposeur MnM, en présentant à la fin un interposeur d'ondes millimétriques pleinement fonctionnelThis work aims at the development of passive circuits in millimeter-wave frequency in the interposer called MnM – metallic nanowire-filled membrane. This interposer is inserted in the context where the miniaturization of passive circuits due to the high operating frequency (roughly above 10 GHz up to 300 GHz for millimeter-waves) makes it interesting to insert passive circuits in integrated technologies such as CMOS, but that due to the limitations linked to the technology do not present high quality, being therefore more interesting in terms of performance and cost the use of an auxiliary substrate for the design of passive circuits that allows their integration with active circuits in integrated technology; this substrate is called an interposer. For the development of a good interposer, it is necessary that it presents high quality transmission lines and vias. The MnM interposer is a low cost alumina membrane that naturally has nanopores caused by its fabrication process that can be used to grow copper nanowires. For the development of this interposer and passive circuits on it, the manufacturing process is improved, with the focus on the growth of nanowires in specific regions and on the fabrication yield. The substrate is electrically characterized for extracting its losses and its dielectric constant, which has been shown to be influenced by the nanopores. With the improvement of the manufacturing process, nanowire-vias are developed and their performance analyzed in the context of a transition between one face and another of the substrate through an electrical model related to the physical layout validated by the measurement results. For the electrical model, an analytical and a matrix approach are proposed, with the verification that the nanowire-via behaves as a solid via with a conductance that takes into account the material of the nanowires and their surface density. It is verified that the nanowire-via have a state-of-the-art performance, besides its small dimensions such radius and pitch between vias, dictated only by the minimum dimension achieved in photolithography. Two, three, five and ten spires solenoid-type inductions that make use of these vias are proposed and analyzed, with the proposal of an electrical model, which relates to its physical layout, to be used by designers. These inductances are compact, due to the small size of the nanowire-vias, and have a high self-resonance frequency, 98 GHz for two-spire inductance. Finally, a new linear electric model for microstrip transmission lines with slow-wave effect caused by the nanowires is proposed, to facilitate its design and simulation, since its electromagnetic simulation presents a high computational cost. This same model is also used for transmission lines in PCB technology, which present the same slow-wave effect but with operating in microwave frequency. Thus, this work presents a significant advance for MnM interposer, presenting at the end a fully functional millimeter wave interposer
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Lee, Yu-Wei, e 李育維. "Self-annealing Mechanism of Electroplated Cu in the Blind-hole Structure of High-density-interconnection Printed Circuit Boards (HDI-PCBs)". Thesis, 2016. http://ndltd.ncl.edu.tw/handle/46593551772826064723.
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碩士元智大學
化學工程與材料科學學系
104
Blind-hole (BH) metallization by electrolytic Cu fillings technology has become a critical process for fabricating high density interconnection (HDI) circuit boards in electronic industry because it it provides high thermal and electrical conductivity. Although numerous publications concerning the room-temperature recrystallization (i.e., self-annealing) of electroplated Cu, there is still limited information regarding the self-annealing behavior of the Cu electrodeposition in the BH structure. The morphology and crystallographic orientation/texture of the Cu fillings governs the electrical, thermal, and mechanical properties of the interconnections, affecting the overall reliability of an electronic device. In this study, the resistance, morphologies and microstructures in the BH Cu filling with self-annealing time (t) was analyzed by employing a source meter, field-emission scanning electron microscope (FE-SEM), and electron backscattered diffraction (EBSD).
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Sun, Hsiang-Wei, e 孫詳崴. "The Study of Plasma Treatment of Polyimide Film Used in High Density Interconnection Board". Thesis, 2002. http://ndltd.ncl.edu.tw/handle/49405545052898026895.
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碩士元智大學
化學工程學系
90
The effect of plasma treatment on the chemical compositions, morphologies, and energies of the polyimide (PI) surfaces is studied with attenuated total reflection infrared spectroscopy (ATR), contact angle measurement, and atomic force microscopy (AFM). PI studied includes Dupont H and E films. The surface energies of all three PI increase after plasma treatment and respond similarly under different plasmas. However, the ATR spectra confirm that the generated functional groups on the surfaces of PI’s are different. The surface morphologies after plasma are also different. The type of plasma also affects the extents of changes of surface functional groups and morphologies.
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Chen, Yu-Pin, e 陳育斌. "Applications and Development for CO2 Laser Drilling Machine of High-Density Interconnection Printed Circuit Boards". Thesis, 2007. http://ndltd.ncl.edu.tw/handle/25630227792779329061.
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博士國立彰化師範大學
機電工程學系
96
The current trend in the microelectronics industry is towards smaller, lighter and more powerful electronic products, and electronic circuit designers are designing high-density interconnected printed circuit boards (HDI PCBs). The board design, transformed from the conventional through hole to the sequence stacking then to blind buried via structure– called HDI technology, which can highly increase the routing density and components assembly density. Laser drilling machines, including CO2 laser drilling machine and UV laser drilling machine, have been widely adopted in forming the microvias of high-density interconnected printed circuit boards. Due to the work efficiency of CO2 laser drilling machine is higher than UV laser drilling machine, CO2 laser drilling machines are main equipment of choice for the microvias formation in the PCB industries. Accordingly, the CO2 laser drilling machine is developed and discussed in this study. In order to develop the CO2 laser drilling machine, several techniques should be developed, including the mechanical structure, the optical system, the PC-base controller, the CAD/CAM interpretation and the compensation methods, and they are discussed in this study. The high positioning accuracy of feeding system is one of the heavy components in precision machine systems, and its compensation method for the positioning accuracy is also an important technique in machine systems. The investigation develops a compensation method of positioning accuracy for two-dimensional feeding system, which using the two-dimensional Lagrange polynomial amend the positioning error of feeding system. First, positioning errors of XY tables are measured by a CCD image processing system by using a standard specimen. Then the two-dimensional compensation function can be determined by the two-dimensional positioning errors curve of the XY feeding system – the system is responsible for correcting the positioning error of the XY table. The positioning accuracy of the amended XY feeding system is measured by a HP 5519A Interferometer, and is verified can effectively increase the accuracy of XY table. According to the experimental results, the positioning accuracy of the X-axis of the XY feeding system has decreased from 7 microns to 2.8 microns and that of the Y-axis is from 17 microns to 2.6 microns. Furthermore, the compensation method does not affect the perpendicular accuracy and the repeatability accuracy of XY feeding systems. The CO2 laser drilling machine utilizes a galvanometric scanning system that can effectively increase the speed of laser drilling procedure, and most of the laser materials processing systems have used the scanning systems improving the efficiency of processing. However, laser galvanometric scanning systems are usually associated with a field distortion error. Accordingly, techniques must be developed to compensate for distortion error. Hence, the investigation discusses the field distortion error of a laser scanning system based on a CO2 laser drilling machine and a method for the correcting this distortion error. The field distortion error is a random error in the laser galvanometric scanning system. This irregular error is usually corrected using pre-compensation methods that apply an error function. The study gives a pre-compensation technique to correct the distortion error of scanning image, which using the two-dimensional Lagrange polynomials modified the control commands of the galvanometric scanning system. The results in this study indicate that the compensation method effectively amended the field distortion and increased the accuracy of the positioning of the holes that were drilled using a laser galvanometric scanning drilling machine. The positioning errors of drilling holes have reduced from ±0.3mm to ±0.05 mm after error compensation. Although Lagrange polynomial can effectively reduce the errors of the scanning system, the non-continuous result of scanning image would be occurred in the marking pictures. Hence, the dissertation develops a new method to decrease the field distortion of the laser marking image, which using the surface curve fitting method to obtain the function of the correction control commands of the galvos. The experimental results indicate that the method can effectively amend the field distortion of laser marking system. Finally, the result of microvias of HDI PCBs that uses the CO2 laser drilling machine is also presented in this study. The conformal mask drilling for microvias formation is presented, and these microvias are formed by a shaped laser beam to improve the quality of microvias. The technology of laser coding on the eggshell and the laser direct write patterning technique of ITO film are presented in this dissertation. Furthermore, the study has developed a laser marking system that uses the DSP controller. The technology of laser marking system is presented in this study, including the dot marking, the vector marking and the error diffusion techniques for the picture marking.
Livros sobre o assunto "High density interconnection PCBs"
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National Research Council (U.S.). Committee on Materials for High-Density Electronic Packaging. Materials for high-density electronic packaging and interconnection: Report of the Committee on Materials for High-Density Electronic Pakaging. Washington, D.C: National Academy Press, 1990.
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National Research Council (U.S.). Committee on Materials for High-Density Electronic Packaging. Materials for high-density electronic packaging and interconnection: Report of the Committee on Materials for High-Density Electronic Packaging, National Materials Advisory Board, Commission on Engineering and Technical Systems, National Research Council. Washington, D.C: National Academy Press, 1990.
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Materials for High-Density Electronic Packaging and Interconnection. Washington, D.C.: National Academies Press, 1990. http://dx.doi.org/10.17226/1624.
Texto completo da fonteCapítulos de livros sobre o assunto "High density interconnection PCBs"
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Guo, Fengrui, Xingming Li, Shanqing Hu e Yanyan Qin. "An Optimized Daisy-chain Topology for Multi-load Interconnection in High–speed and High–density Electronic Systems". In Lecture Notes in Electrical Engineering, 139–46. Singapore: Springer Singapore, 2017. http://dx.doi.org/10.1007/978-981-10-7521-6_17.
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De Martino, Raffaela, Rossella Franchino e Caterina Frettoloso. "A “Stepping Stone” Approach to Exploiting Urban Density". In The Urban Book Series, 639–47. Cham: Springer International Publishing, 2023. http://dx.doi.org/10.1007/978-3-031-29515-7_57.
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AbstractCurrently, there is an increasing need to use ecological-environmental strategies that can contribute to human well-being and biodiversity in urban contexts that are complex systems with an increasingly diverse demand for ecosystem services. This becomes important especially for areas with high urban density which are those that determine the greatest impacts. Recent studies have related the increase of the COVID-19 pandemic to urban density, and the results seem to converge on the hypothesis that the lack of availability of urban space and high population concentration are factors contributing to the spread of disease. However, density constitutes both a problem and an opportunity to creating open spaces on a human scale, favoring the development and articulation of spaces that can more easily creep in and create the necessary conditions both for functional and environmental improvement and for mending the built environment. A dense environment suggests to work according to new logics that, starting from the optimization of existing spaces able to provide ecosystem services, experiment especially the “micro” and “interconnected” formula. The issue of interconnection in cities is complex as the continuity of connections, necessary to ensure the reticularity of spaces, is often inhibited by urban density. The idea is to replace the “structural continuity” with a “functional continuity” according to the “stepping stones” approach, borrowed from the ecology of the landscape. In analogy to the ecological networks approach, therefore, it is proposed to use this logic to enhance existing open spaces and create new ones with the aim of implementing overall urban quality.
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Skulimowski, Andrzej M. J. "Visions of a Future Research Workplace Arising from Recent Foresight Exercises". In Progress in IS, 169–85. Cham: Springer International Publishing, 2021. http://dx.doi.org/10.1007/978-3-030-66262-2_11.
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AbstractThe results of recent foresight projects reveal the impact of future ICT tools on the practice of scientific research. This paper presents several aspects of the process of building scenarios and trends of selected advanced ICT technologies. We point out the implications of emerging global expert systems (GESs) and AI-based learning platforms (AILPs). GESs will be capable of using and processing global knowledge from all available sources, such as databases, repositories, video streams, interactions with other researchers and knowledge processing units. In many scientific disciplines, the high volume, density and increasing level of interconnection of data have already exhausted the capacities of any individual researcher. Three trends may dominate the development of scientific methodology. Collective research is one possible coping strategy: Group intellectual capacity makes it possible to tackle complex problems. Recent data flow forecasts indicate that even in the few areas, which still resist ICT domination, research based on data gathered in non-ICT supported collections will soon reach its performance limits due to the ever-growing amount of knowledge to be acquired, verified, exchanged and communicated between researchers. Growing automation of research is the second option: Automated expert systems will be capable of selecting and processing knowledge to the level of a professionally edited scientific paper, with only minor human involvement. The third trend is intensive development and deployment of brain–computer interfaces (BCIs) to quickly access and process data. Specifically, GESs and AILPs can be used together with BCIs. The above approaches may eventually merge, forming a few AI-related technological scenarios, as discussed to conclude the paper.
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"Landscape Influences on Stream Habitats and Biological Assemblages". In Landscape Influences on Stream Habitats and Biological Assemblages, editado por Michael R. Rosen, Timothy G. Rowe, Steven L. Goodbred, Douglas O. Shipley e Jorge A. Arufe. American Fisheries Society, 2006. http://dx.doi.org/10.47886/9781888569766.ch7.
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<em>Abstract.</em>—Rapid urbanization in the southwest United States has increased concern about water quality of streams and its impact on aquatic biota. One way to estimate potential toxicity impacts is to deploy passive samplers that accumulate many organic contaminants associated with anthropogenic landscapes. Semipermeable membrane devices (SPMDs) use a lipid to mimic bioaccumulation of hydrophobic organic contaminants (HOCs), including polycyclic aromatic hydrocarbons (PAHs), pesticides, and industrial compounds. We investigated effects of land use and streamflow on the presence of HOCs and potential toxicity in the Truckee River and Lake Tahoe watersheds of Nevada and California. We used SPMDs during August/ September 2002 and 2003 base flows and during March 2003 high flows. We employed two complementary toxicity tests to assess potential toxicity to aquatic organisms. The fluoroscan (pyrene index) is designed to assess PAH concentrations. The CYP1A test measures the toxicity of aryl hydrocarbon receptor type compounds, which include PAHs, polychlorinated biphenyls (PCBs), and dioxins. A relatively strong correlation (<em>r </em>= 0.79) between the pyrene index and CYP1A in our data indicated that PAHs were the dominant group of organic contaminants sequestered by our SPMDs. Due to its low-density urbanization, SPMD extracts from the Lake Tahoe watershed generally had less toxicity than those deployed in the Truckee River watershed. Samples from the Truckee River and its tributaries near Reno/Sparks had the highest toxicity, owing to dense residential development and light industry. Higher percentages of urban and agricultural land use correlated with increased toxicity of SPMD extracts, although urban land use had a much greater influence. Streamflow was a less important factor than land use, and only flows greater than 5 m<sup>3</sup>/s correlated with toxicity. Toxicity decreased with higher flows, probably due to dilution. Toxicity of SPMD extracts at all sites during both high and low flows significantly correlated with percent urban land use (<EM>R</EM><sup>2</sup> = 0.32). Generally, toxicity did not correlate with dissolved oxygen, pH, or temperature, but did with specific conductance (<EM>R</EM><sup>2</sup> = 0.27) when samples influenced by geothermal water were excluded.
Trabalhos de conferências sobre o assunto "High density interconnection PCBs"
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Borecki, Janusz. "High density interconnections in PCBs - an overview of plating techniques". In SPIE Proceedings, editado por Ryszard S. Romaniuk. SPIE, 2006. http://dx.doi.org/10.1117/12.675093.
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Sahel, Faten, Pascal Guilbault, Farouk Vallette e Sylvain Feruglio. "A Crosstalk Modelling Method between a Power Supply and a Nearby Signal in High-density Interconnection PCBs". In 2021 22nd International Symposium on Quality Electronic Design (ISQED). IEEE, 2021. http://dx.doi.org/10.1109/isqed51717.2021.9424304.
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Ghaffarian, Reza. "Damage and Failures of CGA/BGA Assemblies Under Thermal Cycling and Dynamic Loadings". In ASME 2013 International Mechanical Engineering Congress and Exposition. American Society of Mechanical Engineers, 2013. http://dx.doi.org/10.1115/imece2013-63062.
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Commercial-off-the-shelf column/ball grid array packaging (COTS CGA/BGA) technologies in high-reliability versions are now being considered for use in high-reliability electronic systems. For space applications, these packages are prone to early failure due to the severe thermal cycling in ground testing and during flight, mechanical shock and vibration of launch, as well as other less severe conditions, such as mechanical loading during descent, rough terrain mobility, handling, and ground tests. As the density of these packages increases and the size of solder interconnections decreases, susceptibility to thermal, mechanical loading and cycling fatigue grows even more. This paper reviews technology as well as thermo-mechanical reliability of field programmable gate array (FPGA) IC packaging developed to meet demands of high processing powers. The FPGAs that generally come in CGA/PBGA packages now have more than thousands of solder balls/columns under the package area. These packages need not only to be correctly joined onto printed circuit board (PCB) for interfacing; they also should show adequate system reliability for meeting thermo-mechanical requirements of the electronics hardware application. Such reliability test data are rare or none for harsher environmental applications, especially for CGAs having more than a thousand of columns. The paper also presents significant test data gathered under thermal cycling and drop testing for high I/O PBGA/CGA packages assembled onto PCBs. Damage and failures of these assemblies after environmental exposures are presented in detail. Understanding the key design parameters and failure mechanisms under thermal and mechanical conditions is critical to developing an approach that will minimize future failures and will enable low-risk insertion of these advanced electronic packages with high processing power and in-field re-programming capability.
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He, Baofeng, Dennis Patrick Webb, Jon Petzing e Richard Leach. "Improving plated copper adhesion for metallisation of glass PCBs". In High Density Packaging (ICEPT-HDP). IEEE, 2011. http://dx.doi.org/10.1109/icept.2011.6066836.
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Arruda, Luciano, Quayle Chen e Jairo Quintero. "Failure evaluation of flexible-rigid PCBs by thermo-mechanical simulation". In High Density Packaging (ICEPT-HDP). IEEE, 2009. http://dx.doi.org/10.1109/icept.2009.5270619.
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Zhou, Liangjie, Weihong Peng, Dong Liu, Rubin Zou, Xuefei Jiang, Weisheng Xia e Fengshun Wu. "Research on dimensional change characteristics of silver halide films for multi-layer PCBs". In High Density Packaging (ICEPT-HDP). IEEE, 2011. http://dx.doi.org/10.1109/icept.2011.6066931.
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Zhang, Shunong, Anshul Shrivastava, Michael Osterman, Michael Pecht e Rui Kang. "The influence of SO2 environments on immersion silver finished PCBs by mixed flow gas testing". In High Density Packaging (ICEPT-HDP). IEEE, 2009. http://dx.doi.org/10.1109/icept.2009.5270782.
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Arruda, Luciano, Willy Ferreira e Marco Andolfatto. "Experimental analysis of propagation of the delamination in Flex-PCBs subjected to thermal cycling loading". In High Density Packaging (ICEPT-HDP). IEEE, 2010. http://dx.doi.org/10.1109/icept.2010.5582797.
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Krusius, J. P. "System interconnection of high-density multichip modules". In Boston - DL tentative, editado por Stuart K. Tewksbury e John R. Carruthers. SPIE, 1991. http://dx.doi.org/10.1117/12.25582.
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Beyne, E., e R. Mertens. "Trends in packaging and high density interconnection". In Proceedings of International Conference on Microelectronics (ICM'99). IEEE, 2000. http://dx.doi.org/10.1109/icm.2000.884794.
Texto completo da fonteRelatórios de organizações sobre o assunto "High density interconnection PCBs"
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Wang, Michael R. High Density Optical Interconnection Based on Free Space Non-Diffracting Beams. Fort Belvoir, VA: Defense Technical Information Center, março de 1999. http://dx.doi.org/10.21236/ada361509.
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Lotufo, Guilherme, Mandy Michalsen, Danny Reible, Philip Gschwend, Upal Ghosh, Alan Kennedy, Kristen Kerns et al. Interlaboratory study of polyethylene and polydimethylsiloxane polymeric samplers for ex situ measurement of freely dissolved hydrophobic organic compounds in sediment porewater. Engineer Research and Development Center (U.S.), maio de 2024. http://dx.doi.org/10.21079/11681/48512.
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We evaluated the precision and accuracy of multilaboratory measurements for determining freely dissolved concentrations (Cfree) of polycyclic aromatic hydrocarbons (PAHs) and polychlorinated biphenyls (PCBs) in sediment porewater using polydimethylsiloxane and low-density polyethylene polymeric samplers. Four laboratories exposed performance reference compound (PRC) preloaded polymers to actively mixed and static ex situ sediment for approximately one month or more. For Cfree results, intralaboratory precision was high for single compounds; most PAHs and PCBs variability was low. Variability was higher for most hydrophobic PAHs, PCBs, and naphthalene, which were present at low concentrations and required larger PRC-based corrections. Intra- and interlaboratory variability between methods was low. Cfree polymer equilibrium was achieved in approximately one month during active exposures, suggesting using PRCs may be avoided for ex situ analysis using comparable active exposure; however, such testing may not reflect field conditions. Polymer-derived Cfree concentrations for most PCBs and PAHs averaged within a factor of 2 compared with concentrations in isolated porewater; difference factors of up to 6 were observed for naphthalene and the most hydrophobic PAHs and PCBs. Cfree results were similar for academic and private sector laboratories. The accuracy and precision demonstrated for determinating Cfree using polymer sampling are anticipated to increase regulatory acceptance and confidence.