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Bibliografias temáticas / Gate array circuits

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Literatura científica selecionada sobre o tema "Gate array circuits"

Autor: Grafiati

Publicado: 4 de junho de 2021

Última modificação: 29 de julho de 2024

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Artigos de revistas sobre o assunto "Gate array circuits"

1

Kunts, A. V., O. V. Dvornikov e V. A. Tchekhovski. "Design of BJT-JFET Operational Amplifiers on the Master Slice Array". Doklady BGUIR 21, n.º 6 (4 de janeiro de 2024): 29–36. http://dx.doi.org/10.35596/1729-7648-2023-21-6-29-36.

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The use of dual-gate field-effect transistors located on the base matrix crystal MH2XA031, controlled by a p–n junction needed to reduce the input current of operational amplifiers is studied. Typical circuits of operational amplifiers, containing: source repeaters connected to the inputs of the operational amplifier on complementary bipolar transistors; input differential stage on p-JFET with a “current mirror” load on n–p–n-transistors; input differential in the form of a “folded cascode” on a p-JFET are analyzed. To minimize the input current, it is re commended to use bootstrapped feedback to keep the drain-to-source voltage of the input JFETs low, independent of the input common-mode voltage, and to connect only the top gate of the dual-gate JFET to the op-amp input. The electrical circuits for MH2XA031 elements and the results of circuit simulation of the developed amplifiers, called OAmp10J, OAmp11.1, OAmp11.2, are presented. Accounting the established features of the input stages and operating modes of active elements in circuit design will allow to create an operational amplifier with the required combination of basic parameters.

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Abraitis, Vidas, e Žydrūnas Tamoševičius. "Transition Test Patterns Generation for BIST Implemented in ASIC and FPGA". Solid State Phenomena 144 (setembro de 2008): 214–19. http://dx.doi.org/10.4028/www.scientific.net/ssp.144.214.

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Transition delay testing of sequential circuits in a clocked environment is analyzed. There are presented two test pattern generator methods for built in self testing of the circuit implemented as Application Specific Integrated Circuit (ASIC) and Field Programmable Gate Array (FPGA) of Virtex family. Cellular automaton and Linear Feedback Shift Register (LFSR) structures are used for test sequence generation. The circuits are tested as the black boxes under Transition fault model. Experimental results of the test pattern generation methods are presented and analyzed. Results compared with exhaustive test of transition faults for ASICs and programmable integrated circuits with given configuration.

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Mohammadi, Hossein, e Keivan Navi. "Energy-Efficient Single-Layer QCA Logical Circuits Based on a Novel XOR Gate". Journal of Circuits, Systems and Computers 27, n.º 14 (23 de agosto de 2018): 1850216. http://dx.doi.org/10.1142/s021812661850216x.

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Quantum-dot Cellular Automata (QCA) as a nanoscale transistor-less device technology offers distinguishing advantages over the limitations of CMOS circuits. This nanoelectronic is based on the mapping of binary logic in the two excess electrons configuration within a four-dot cell. In this paper, we propose a new ultra-low energy and low-complexity two-input XOR gate which can be employed as a basic component in designing a wide range of QCA logical circuits. For performance evaluation of the presented design in a large array of QCA structures, even parity generator circuit with different lengths up to 32 bits as well as LFSR circuit are designed and analyzed as instances of logical circuits. The simulation results reveal that our proposed designs have significant improvements in contrast to counterparts from hardware implementation requirements and energy consumption aspects. QCADesigner tool is utilized to evaluate functional correctness of the proposed circuits and power dissipation is evaluated using QCAPro simulator as an accurate power estimator tool.

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Mowafy, Aya Nabeel. "Asynchronous Circuits Design Using a Field Programmable Gate Array". International Journal for Research in Applied Science and Engineering Technology 6, n.º 4 (30 de abril de 2018): 2423–32. http://dx.doi.org/10.22214/ijraset.2018.4412.

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Sato, Ryoichi, Yuta Kodera, Md Arshad Ali, Takuya Kusaka, Yasuyuki Nogami e Robert H. Morelos-Zaragoza. "Consideration for Affects of an XOR in a Random Number Generator Using Ring Oscillators". Entropy 23, n.º 9 (5 de setembro de 2021): 1168. http://dx.doi.org/10.3390/e23091168.

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A cloud service to offer entropy has been paid much attention to. As one of the entropy sources, a physical random number generator is used as a true random number generator, relying on its irreproducibility. This paper focuses on a physical random number generator using a field-programmable gate array as an entropy source by employing ring oscillator circuits as a representative true random number generator. This paper investigates the effects of an XOR gate in the oscillation circuit by observing the output signal period. It aims to reveal the relationship between inputs and the output through the XOR gate in the target generator. The authors conduct two experiments to consider the relevance. It is confirmed that combining two ring oscillators with an XOR gate increases the complexity of the output cycle. In addition, verification using state transitions showed that the probability of the state transitions was evenly distributed by increasing the number of ring oscillator circuits.

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Kuboki, S., I. Masuda, T. Hayashi e S. Torii. "A 4K CMOS gate array with automatically generated test circuits". IEEE Journal of Solid-State Circuits 20, n.º 5 (outubro de 1985): 1018–24. http://dx.doi.org/10.1109/jssc.1985.1052430.

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AKELLA, KAPILAN MAHESWARAN VENKATESH. "PGA-STC: programmable gate array for implementing self-timed circuits". International Journal of Electronics 84, n.º 3 (março de 1998): 255–67. http://dx.doi.org/10.1080/002072198134823.

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Murtaza, Ali Faisal, e Hadeed Ahmed Sher. "A Reconfiguration Circuit to Boost the Output Power of a Partially Shaded PV String". Energies 16, n.º 2 (4 de janeiro de 2023): 622. http://dx.doi.org/10.3390/en16020622.

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An optical isolator circuit is developed to detect and dynamically relocate the photovoltaic (PV) module under partial shading. The suggested system control structure operates in two modes. Mode 1 governs the system at global maxima (GM) by tracing the power-voltage (PV) curve. Mode 2 detects and separates all the bypassed modules from a PV string/array by means of a decentralized control and stores its power in the battery. Simulations are performed on different shading patterns to verify the efficacy of the suggested system. The results showcase that the averaged harnessed power using the proposed circuit is 25.26% more than the total cross-tied (TCT) and series-parallel (SP) array configurations. The proposed circuit does not require complex gate driver circuits and large switch counts. The circuit is scalable and can be implemented on an “N × N” array.

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Jaafar, Anuar, Norhayati Soin, Sharifah F. Wan Muhamad Hatta, Sani Irwan Salim e Zahriladha Zakaria. "Multipoint Detection Technique with the Best Clock Signal Closed-Loop Feedback to Prolong FPGA Performance". Applied Sciences 11, n.º 14 (12 de julho de 2021): 6417. http://dx.doi.org/10.3390/app11146417.

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The degradation effect of a field-programmable gate array becomes a significant issue due to the high density of logic circuits inside the field-programmable gate array. The degradation effect occurs because of the rapid technology scaling process of the field-programmable gate array while sustaining its performance. One parameter that causes the degradation effect is the delay occurrence caused by the hot carrier injection and negative bias temperature instability. As such, this research proposed a multipoint detection technique that detects the delay occurrence caused by the hot carrier injection and negative bias temperature instability degradation effects. The multipoint detection technique also assisted in signaling the aging effect on the field-programmable gate array caused by the delay occurrence. The multipoint detection technique was also integrated with a method to optimize the performance of the field-programmable gate array via an automatic clock correction scheme, which could provide the best clock signal for prolonging the field-programmable gate array performance that degraded due to the degradation effect. The delay degradation effect ranged from 0° to 360° phase shifts that happened in the field-programmable gate array as an input feeder into the multipoint detection technique. With the ability to provide closed-loop feedback, the proposed multipoint detection technique offered the best clock signal to prolong the field-programmable gate array performance. The results obtained using the multipoint detection technique could detect the remaining lifetime of the field-programmable gate array and propose the best possible signal to prolong the field-programmable gate array’s performance. The validation showed that the multipoint detection technique could prolong the performance of the degraded field-programmable gate array by 13.89%. With the improvement shown using the multipoint detection technique, it was shown that compensating for the degradation effect of the field-programmable gate array with the best clock signal prolonged the performances.

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Cherepacha, Don, e David Lewis. "DP-FPGA: An FPGA Architecture Optimized for Datapaths". VLSI Design 4, n.º 4 (1 de janeiro de 1996): 329–43. http://dx.doi.org/10.1155/1996/95942.

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This paper presents a new Field-Programmable Gate Array (FPGA) architecture which reduces the density gap between FPGAs and Mask-Programmed Gate Arrays (MPGAs) for datapath oriented circuits. This is primarily achieved by operating on data as a number of identically programmed four-bit slices. The interconnection network incorporates distinct sets of resources for routing control and data signals. These features reduce circuit area by sharing programming bits among four-bit slices, reducing the total number of storage cells required.This paper discusses the requirements of logic blocks and routing structures that can be used to implement typical circuits containing a number of regularly structured datapaths of various sizes, as well as a small number of irregularities. It proposes a specific set of logic block architectures and analyzes it empirically. Experimental results show that the block with the smallest estimated area contains the following features: a lookup table with four read ports, a dedicated carry chain using a bidirectional four-bit carry skip circuit, a four-bit register with enable and direct input capabilities, and four three-state buffers. Further estimates of implementation area predict that the area of a design's datapath can be reduced by a factor of approximately two compared to a conventional FPGA through the use of programming bit sharing.

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Teses / dissertações sobre o assunto "Gate array circuits"

1

Sharma, Akshay. "Place and route techniques for FPGA architecture advancement /". Thesis, Connect to this title online; UW restricted, 2005. http://hdl.handle.net/1773/6108.

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Baweja, Gunjeetsingh. "Gate level coverage of a behavioral test generator". Thesis, This resource online, 1993. http://scholar.lib.vt.edu/theses/available/etd-11102009-020104/.

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Tan, Zhou. "Design of a Reconfigurable Pulsed Quad-Cell for Cellular-Automata-Based Conformal Computing". Thesis, North Dakota State University, 2011. https://hdl.handle.net/10365/29176.

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This paper presents the design of a reconfigurable asynchronous unit, called the pulsed quad-cell (PQ-cell), for conformal computing. The conformal computing vision is to create computational materials that can conform to the physical and computational needs of an application. PQ-cells, like cellular automata, are assembled into arrays with nearest neighbor communication and are capable of general computation. They operate asynchronously to minimize power consumption and to allow sealing without the limitations imposed by a global clock. Cell operations are stimulated by pulses which use two wires to encode a data bit. Cells are individually reconfirgurable to perform logic, move and store information, and coordinate parallel activity. The PQ-cell design targets a 0.25 ?m CMOS technology. Simulation results show that a PQ-cell, when pulsed at 1.3 GHz, consumes 16.9 pJ per operation. Examples of self-timed multi-cell structures include a 98 MHz ring oscillator and a 385 MHz pipeline.

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Hu, Jhy-Fang 1961. "AUTOMATIC HARDWARE COMPILER FOR THE CMOS GATE ARRAY". Thesis, The University of Arizona, 1986. http://hdl.handle.net/10150/276948.

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Balog, Michael Rosen Warren A. "The automated compilation of comprehensive hardware design search spaces of algorithmic-based implementations for FPGA design exploration /". Philadelphia, Pa. : Drexel University, 2007. http://hdl.handle.net/1860/1770.

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Hall, Tyson Stuart. "Field-Programmable Analog Arrays: A Floating-Gate Approach". Diss., Available online, Georgia Institute of Technology, 2004:, 2004. http://etd.gatech.edu/theses/available/etd-07122004-124607/unrestricted/hall%5Ftyson%5Fs%5F200407%5Fphd.pdf.

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Thesis (Ph. D.)--Electrical and Computer Engineering, Georgia Institute of Technology, 2005. Directed by David Anderson.
Prvulovic, Milos, Committee Member ; Citrin, David, Committee Member ; Lanterman, Aaron, Committee Member ; Yalamanchili, Sudhakar, Committee Member ; Hasler, Paul, Committee Member ; Anderson, David, Committee Chair. Includes bibliographical references.

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7

Qi, Wen-jie. "Study on high-k dielectrics as alternative gate insulators for 0.1[mu] and beyond ULSI applications /". Digital version accessible at:, 2000. http://wwwlib.umi.com/cr/utexas/main.

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Mao, Yu-lung. "Novel high-K gate dielectric engineering and thermal stability of critical interface /". Digital version accessible at:, 1999. http://wwwlib.umi.com/cr/utexas/main.

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Lee, Jian-hung. "Strontium titanate thin films for ULSI memory and gate dielectric applications /". Digital version accessible at:, 2000. http://wwwlib.umi.com/cr/utexas/main.

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10

Kucic, Matthew R. "Analog programmable filters using floating-gate arrays". Thesis, Georgia Institute of Technology, 2000. http://hdl.handle.net/1853/13755.

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Livros sobre o assunto "Gate array circuits"

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1955-, Trimberger Stephen, ed. Field-programmable gate array technology. Boston: Kluwer Academic Publishers, 1994.

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2

W, Read John, ed. Gate arrays: Design and applications. London: Collins, 1985.

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3

Inc, Xilinx. The programmable gate array data book. San Jose, Calif: XILINX, Inc., 1988.

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4

ACM, International Symposium on Field-Programmable Gate Arrays (17th 2009 Monterey Calif ). FPGA'09: Proceedings of the Seventeenth ACM SIGDA International Symposium on Field-Programmable Gate Arrays, Monterey, California, USA, February 22-24, 2009. New York, N.Y: Association for Computing Machinery, 2009.

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5

ACM, International Symposium on Field-Programmable Gate Arrays (12th 2004 Monterey Calif ). FPGA 2004: ACM/SIGDA Twelfth ACM International Symposium on Field-Programmable Gate Arrays, Monterey Beach Hotel, Monterey, California, USA : February 22-24, 2004. New York, N.Y: Association for Computing Machinery, 2004.

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6

ACM, International Symposium on Field-Programmable Gate Arrays (7th 1999 Monterey Calif ). FPGA '99: ACM/SIGDA International Symposium on Field Programmable Gate Arrays. New York, NY: ACM Press, 1999.

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7

ACM, International Symposium on Field-Programmable Gate Arrays (3rd 1995 Monterey Calif ). FPGA '95: 1995 ACM Third International Sympsosium on Field-Programmable Gate Arrays : February 12-14, 1995, Monterey Marriott, Monterey, California, USA. New York, N.Y: ACM Press, 1995.

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8

ACM Special Interest Group on Design Automation, ed. FPGA '13: Proceedings of the 2013 ACM SIGDA International Symposium on Field Programmable Gate Arrays : February 11-13, 2013, Monterey, California, USA. New York, N.Y: Association for Computing Machinery, 2013.

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9

ACM International Symposium on Field-Programmable Gate Arrays (10th 2002 Monterey, Calif.). FPGA 2002: Tenth ACM International Symposium on Field-Programmable Gate Arrays, Monterey, California, USA : February 24-26, 2002. New York, N.Y: ACM Press, 2002.

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10

ACM International Symposium on Field-Programmable Gate Arrays (17th 2009 Monterey, Calif.). FPGA'09: Proceedings of the Seventeenth ACM SIGDA International Symposium on Field-Programmable Gate Arrays, Monterey, California, USA, February 22-24, 2009. New York, N.Y: Association for Computing Machinery, 2009.

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Capítulos de livros sobre o assunto "Gate array circuits"

1

Sanchez, Eduardo. "Field programmable gate array (FPGA) circuits". In Towards Evolvable Hardware, 1–18. Berlin, Heidelberg: Springer Berlin Heidelberg, 1996. http://dx.doi.org/10.1007/3-540-61093-6_1.

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Babu, Hafiz Md Hasan. "Place and Route Algorithm for Field Programmable Gate Array". In VLSI Circuits and Embedded Systems, 207–12. Boca Raton: CRC Press, 2022. http://dx.doi.org/10.1201/9781003269182-20.

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3

Pandey, Bishwajeet, e Keshav Kumar. "HDL coding of GCC Circuits". In Green Communication with Field-programmable Gate Array for Sustainable Development, 33–69. Boca Raton: CRC Press, 2023. http://dx.doi.org/10.1201/9781003302872-3.

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Babu, Hafiz Md Hasan. "BCD Adder Using a LUT-Based Field Programmable Gate Array". In VLSI Circuits and Embedded Systems, 287–98. Boca Raton: CRC Press, 2022. http://dx.doi.org/10.1201/9781003269182-23.

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Chen, Yu-Fang, Philipp Rümmer e Wei-Lun Tsai. "A Theory of Cartesian Arrays (with Applications in Quantum Circuit Verification)". In Automated Deduction – CADE 29, 170–89. Cham: Springer Nature Switzerland, 2023. http://dx.doi.org/10.1007/978-3-031-38499-8_10.

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AbstractWe present a theory of Cartesian arrays, which are multi-dimensional arrays with support for the projection of arrays to sub-arrays, as well as for updating sub-arrays. The resulting logic is an extension of Combinatorial Array Logic (CAL) and is motivated by the analysis of quantum circuits: using projection, we can succinctly encode the semantics of quantum gates as quantifier-free formulas and verify the end-to-end correctness of quantum circuits. Since the logic is expressive enough to represent quantum circuits succinctly, it necessarily has a high complexity; as we show, it suffices to encode the k-color problem of a graph under a succinct circuit representation, an NEXPTIME-complete problem. We present an NEXPTIME decision procedure for the logic and report on preliminary experiments with the analysis of quantum circuits using this decision procedure.

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Lenk, Claudia, Kalpan Ved, Steve Durstewitz, Tzvetan Ivanov, Martin Ziegler e Philipp Hövel. "Bio-inspired, Neuromorphic Acoustic Sensing". In Springer Series on Bio- and Neurosystems, 287–315. Cham: Springer International Publishing, 2023. http://dx.doi.org/10.1007/978-3-031-36705-2_12.

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AbstractWe present an overview of recent developments in the area of acoustic sensing that is inspired by biology and realized by micro-electromechanical systems (MEMS). To support understanding, an overview of the principles of human hearing is presented first. After the review of bio-inspired sensing systems, we continue with an outline of an adaptable acoustic MEMS-based sensor that offers adaptable sensing properties due to a simple, real-time feedback. The transducer itself is based on an active cantilever, which offers the advantage of an integrated deflection sensing based on piezoresistive elements and an integrated actuation using thermomechanical effects. We use a feedback loop, which is realized via a field-programmable gate array or analog circuits, to tune the dynamics of the sensor system. Thereby, the transfer characteristics can be switched between active, linear mode, for which the sensitivity and minimal detectable sound pressure level can be set by the feedback strength (similar to control of the quality factor), and an active nonlinear mode with compressive characteristics. The presented sensing system, which is discussed both from an experimental and theoretical point of view, offers real-time control for adaptation to different environments and application-specific sound detection with either linear or nonlinear characteristics.

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Murray, Alan F., e H. Martin Reekie. "The GATEWAY Gate Array Design Exercise". In Integrated Circuit Design, 119–45. New York, NY: Springer New York, 1987. http://dx.doi.org/10.1007/978-1-4899-6675-9_8.

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Murray, Alan F., e H. Martin Reekie. "The GATEWAY Gate Array Design Exercise". In Integrated Circuit Design, 119–45. London: Macmillan Education UK, 1987. http://dx.doi.org/10.1007/978-1-349-18758-4_8.

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Pau, L. F. "Inspection of Integrated Circuits and Gate Arrays". In Computer Vision for Electronics Manufacturing, 61–86. Boston, MA: Springer US, 1990. http://dx.doi.org/10.1007/978-1-4613-0507-1_5.

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Watanabe, Takahiro, e Minoru Watanabe. "Triple Module Redundancy of a Laser Array Driver Circuit for Optically Reconfigurable Gate Arrays". In Lecture Notes in Computer Science, 163–73. Berlin, Heidelberg: Springer Berlin Heidelberg, 2012. http://dx.doi.org/10.1007/978-3-642-28365-9_14.

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Trabalhos de conferências sobre o assunto "Gate array circuits"

1

Larkins, B., S. Canaga, G. Lee, B. Terrell e I. Deyhimy. "13000 gate ECL compatible GaAs gate array". In 1989 Proceedings of the IEEE Custom Integrated Circuits Conference. IEEE, 1989. http://dx.doi.org/10.1109/cicc.1989.56764.

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Gallia, J., A. Yee, I. Wang, K. Chau, H. Davis, S. Swamy, T. Sridhar et al. "A 100 K gate sub-micron BiCMOS gate array". In 1989 Proceedings of the IEEE Custom Integrated Circuits Conference. IEEE, 1989. http://dx.doi.org/10.1109/cicc.1989.56717.

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3

Takechi, Yamagiwa, Okabe, Arai, Maejima, Zurita, Hara, Takahashi e Ikuzaki. "A 630k Transistor Cmos Gate Array". In 1988 IEEE International Solid-State Circuits Conference. IEEE, 1988. http://dx.doi.org/10.1109/isscc.1988.663629.

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4

EI-Ajat, El Gamal, Guo, Chang, Hamdy, McCollum e Mohsen. "A Cmos Electrically Configurable Gate Array". In 1988 IEEE International Solid-State Circuits Conference. IEEE, 1988. http://dx.doi.org/10.1109/isscc.1988.663633.

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5

Craft, Nicholas, Michael Prise, R. E. LaMarche e M. M. Downs. "Optical digital pipeline processor using symmetric self-electro-optic-effect devices". In OSA Annual Meeting. Washington, D.C.: Optica Publishing Group, 1990. http://dx.doi.org/10.1364/oam.1990.tujj3.

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We constructed an optical digital processor in which large arrays of symmetric self-electro-optic-effect (S-SEED) devices are available for use as optical logic gates. Four arrays were used, and 32 devices on each array were connected to the next array via a free-space optical split and shift network. Patterned masks, which blocked some of the light beams, were used to configure the ma chine. The optical power supply consisted of a pair of 850 nm, 10 mW laser diodes for each gate array. A Dammann grating was used to split each pair of laser beams into an array of 32 beams. When these beams reflected off one of the S-SEED arrays, they became the input signals to the next array. We used polarizing beam splitters and placed patterned mirrors in focal planes to combine the two inputs and the power supply beams at the device and to retrieve the reflected output. The system was clocked by current modulating the lasers. Two circuits were demonstrated: a shift register that used 1-input gates and a selector/decoder that used 2 inputs. The former circuit ran at 1 MHz, the latter at 70 kHz.

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6

Krestinskaya, Olga, Akshay Kumar Maan e Alex Pappachen James. "Programmable Memristive Threshold Logic Gate Array". In 2018 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS). IEEE, 2018. http://dx.doi.org/10.1109/apccas.2018.8605646.

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Kotani, S., A. Inoue e S. Hasuo. "A 7.6 K-gate Josephson macrocell array". In Digest of Technical Papers., 1990 Symposium on VLSI Circuits. IEEE, 1990. http://dx.doi.org/10.1109/vlsic.1990.111099.

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Morita, H., e M. Watanabe. "MEMS optically differential reconfigurable gate array". In 2009 IEEE International Conference of Electron Devices and Solid-State Circuits (EDSSC 2009). IEEE, 2009. http://dx.doi.org/10.1109/edssc.2009.5394174.

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9

Nakajima, Mao, e Minoru Watanabe. "A 100-context optically reconfigurable gate array". In 2010 IEEE International Symposium on Circuits and Systems - ISCAS 2010. IEEE, 2010. http://dx.doi.org/10.1109/iscas.2010.5536965.

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Lentine, A. L., L. M. F. Chirovsky, M. W. Focht, J. M. Freund, G. D. Guth, R. E. Leibenguth, G. J. Przybylek, L. E. Smith, L. A. D’Asaro e D. A. B. Miller. "Integrated array of self electro-optic effect device logic gates". In Optical Computing. Washington, D.C.: Optica Publishing Group, 1991. http://dx.doi.org/10.1364/optcomp.1991.ma2.

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Arrays of symmetric self electro-optic effect devices (S-SEEDs) have been made with low operating energies and fast switching speeds [1,2]. The device has the characteristics of a set-reset latch, although it can be made to do logic functions such as a NOR gate by presetting the state of the device before the application of the data inputs [3]. Logic gates that can perform more complex functions without preset beams may be realized by using electrically connected detectors configured like transistors in NMOS or CMOS circuits together with an output S-SEED to provide the output beams [4]. In this paper, we describe the first integrated arrays of these logic gates, each of which can perform the four basic logic functions without the use of preset beams. Each logic gate in the array consists of six quantum well p-i-n diodes, four input diodes configured similar to transistors in a CMOS NOR gate, and two output diodes (i. e. a S-SEED) that provide a set of complementary output beams. Like the S-SEEDs, this device has time sequential gain, in which the low power input beams set the state of the device and a set of equal higher power clock beams subsequently read the state. This device retains many desirable qualities of the S-SEED such as signal regeneration and retiming, wavefront restoration, and operation over several decades in power levels due to its differential nature. Because the logic gate contains only quantum well diodes, the same batch fabrication procedures [1] used for S-SEED arrays were used to make the arrays of these devices.

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