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Bibliografias temáticas / Field Programmable Gate Arrays

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Literatura científica selecionada sobre o tema "Field Programmable Gate Arrays"

Autor: Grafiati

Publicado: 4 de junho de 2021

Última modificação: 29 de julho de 2024

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Artigos de revistas sobre o assunto "Field Programmable Gate Arrays"

1

Marchal, Pierre. "Field-programmable gate arrays". Communications of the ACM 42, n.º 4 (abril de 1999): 57–59. http://dx.doi.org/10.1145/299157.299594.

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Verma, H. "Field programmable gate arrays". IEEE Potentials 18, n.º 4 (1999): 34–36. http://dx.doi.org/10.1109/45.796099.

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3

Lombardi, F. "Field Programmable Gate-Arrays". IEEE Design & Test of Computers 15, n.º 1 (janeiro de 1998): 8–9. http://dx.doi.org/10.1109/mdt.1998.655176.

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4

Bhatia, Dinesh. "Field-Programmable Gate Arrays". VLSI Design 4, n.º 4 (1 de janeiro de 1996): i—ii. http://dx.doi.org/10.1155/1996/87608.

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5

Hurst, S. L. "Field programmable gate arrays". Microelectronics Journal 28, n.º 1 (janeiro de 1997): 102. http://dx.doi.org/10.1016/s0026-2692(97)87854-8.

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Hurst, S. L. "Field-programmable gate arrays". Microelectronics Journal 25, n.º 1 (fevereiro de 1994): 77–78. http://dx.doi.org/10.1016/0026-2692(94)90166-x.

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7

Jay, Christopher. "Field programmable gate arrays". Microprocessors and Microsystems 17, n.º 7 (setembro de 1993): 370. http://dx.doi.org/10.1016/0141-9331(93)90058-f.

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8

Greene, J., E. Hamdy e S. Beal. "Antifuse field programmable gate arrays". Proceedings of the IEEE 81, n.º 7 (julho de 1993): 1042–56. http://dx.doi.org/10.1109/5.231343.

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9

Leon, A. F. "Field programmable gate arrays in space". IEEE Instrumentation & Measurement Magazine 6, n.º 4 (dezembro de 2003): 42–48. http://dx.doi.org/10.1109/mim.2003.1251482.

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10

Rose, J., A. El Gamal e A. Sangiovanni-Vincentelli. "Architecture of field-programmable gate arrays". Proceedings of the IEEE 81, n.º 7 (julho de 1993): 1013–29. http://dx.doi.org/10.1109/5.231340.

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Teses / dissertações sobre o assunto "Field Programmable Gate Arrays"

1

Howard, Neil John. "Defect-tolerant Field-Programmable Gate Arrays". Thesis, University of York, 1994. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.359290.

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2

Hall, Tyson Stuart. "Field-Programmable Analog Arrays: A Floating-Gate Approach". Diss., Available online, Georgia Institute of Technology, 2004:, 2004. http://etd.gatech.edu/theses/available/etd-07122004-124607/unrestricted/hall%5Ftyson%5Fs%5F200407%5Fphd.pdf.

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Thesis (Ph. D.)--Electrical and Computer Engineering, Georgia Institute of Technology, 2005. Directed by David Anderson.
Prvulovic, Milos, Committee Member ; Citrin, David, Committee Member ; Lanterman, Aaron, Committee Member ; Yalamanchili, Sudhakar, Committee Member ; Hasler, Paul, Committee Member ; Anderson, David, Committee Chair. Includes bibliographical references.

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3

Leong, David Chin Kuang. "Incremental placement for field-programmable gate arrays". Thesis, University of British Columbia, 2006. http://hdl.handle.net/2429/31671.

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As the logic capacity of FPGAs continues to increase with deep submicron technology, performing a full recompilation for small iterative changes in a large design is an extremely time-consuming and costly process. To address this issue, this thesis presents a new incremental placement algorithm for FPGAs named "iPlace" that significantly reduces the time required for recompilation. The iPlace algorithm is based on shifting, compaction, and annealing. Key ideas from the algorithm include a placement super-grid that is larger than the physical size of the FPGA. The super-grid allows insertion of additional CLBs into areas with no free locations by CPU-efficient shifting. This is followed by a compaction scheme to re-legalize CLBs that are shifted to illegal locations outside of the physical size of the FPGA. The algorithm ends with a low-temperature anneal to improve quality. This algorithm is capable of handling multiple design changes across large regions of a FPGA. This is especially useful for hierarchical designs where sub-circuits are re-used multiple times. If one such sub-circuit is modified, iPlace can quickly produce a high quality incremental placement solution. For a single region of design change, we found that iPlace is 34 to 260 times faster than the academic tool Versatile Place and Route (VPR) in default mode. Compared to VPR's reduced-quality "-fast" placement option, iPlace is 3 to 28 times faster with equivalent quality. For multiple regions of design changes, iPlace is still 50-70 times faster compared to VPR in default mode when up to 2/3 of the CLBs are modified; Compared to the "-fast" placement option, iPlace is still 5-8 times faster. We believe that iPlace is the first academically available incremental placement algorithm capable of handling significant changes to a netlist for very large circuits.
Applied Science, Faculty of
Electrical and Computer Engineering, Department of
Graduate

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4

Messa, Norman C. "Design implementation into field programmable gate arrays". Thesis, Monterey, California. Naval Postgraduate School, 1991. http://hdl.handle.net/10945/26451.

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5

Niu, Jianyong. "Digital control using field programmable gate arrays". Thesis, University of Sheffield, 2006. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.434507.

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6

Lu, Aiguo. "Logic synthesis for field programmable gate arrays". Thesis, University of Bristol, 1995. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.295061.

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7

Newalkar, Aditya. "Alternative techniques for Built-In Self-Test of Field Programmable Gate Arrays". Auburn, Ala., 2005. http://repo.lib.auburn.edu/2005%20Summer/master's/NEWALKAR_ADITYA_6.pdf.

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8

Карнаушенко, В. П., e А. В. Бородин. "Field Programmable Counter Arrays Integration with Field Programmable Gates Arrays". Thesis, NURE, MC&FPGA, 2019. https://mcfpga.nure.ua/conf/2019-mcfpga/10-35598-mcfpga-2019-004.

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Field Programmable Counter Arrays (FPCAs) have been recently introduced to close the gap between Field Programmable Gates Arrays (FPGA) and Application Specified Integrated Circuits (ASICs) for arithmetic dominated applications. FPCAs are reconfigurable lattices that can be embedded into FPGAs to efficiently compute the result of multi-operand additions.

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9

Vachranukunkiet, Petya Nagvajara Prawat Johnson Jeremy. "Power flow computation using field programmable gate arrays /". Philadelphia, Pa. : Drexel University, 2007. http://hdl.handle.net/1860/1789.

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10

Camus, Dominic Roger. "Improved logic optimisation for field programmable gate arrays". Thesis, University of Oxford, 1999. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.301840.

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Mais fontes

Livros sobre o assunto "Field Programmable Gate Arrays"

1

Brown, Stephen D., Robert J. Francis, Jonathan Rose e Zvonko G. Vranesic. Field-Programmable Gate Arrays. Boston, MA: Springer US, 1992. http://dx.doi.org/10.1007/978-1-4615-3572-0.

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2

D, Brown Stephen, ed. Field-programmable gate arrays. Boston: Kluwer Academic Publishers, 1992.

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3

Brown, Stephen D. Field-Programmable Gate Arrays. Boston, MA: Springer US, 1992.

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4

1955-, Trimberger Stephen, ed. Field-programmable gate array technology. Boston: Kluwer Academic Publishers, 1994.

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5

Murgai, Rajeev. Logic synthesis for field-programmable gate arrays. Boston: Kluwer Academic Publishers, 1995.

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6

Ukeiley, Richard Larry. Field programmable gate arrays (FPGAs): The 3000 series. Englewood Cliffs, N.J: PTR Prentice Hall, 1993.

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7

Murgai, Rajeev, Robert K. Brayton e Alberto Sangiovanni-Vincentelli. Logic Synthesis for Field-Programmable Gate Arrays. Boston, MA: Springer US, 1995. http://dx.doi.org/10.1007/978-1-4615-2345-1.

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8

Vuillamy, Jean-Michel. Performance enhancement in field-programmable Gate Arrays. Ottawa: National Library of Canada, 1991.

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9

Messa, Norman C. Design implementation into field programmable gate arrays. Monterey, Calif: Naval Postgraduate School, 1991.

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10

Murgai, Rajeev. Logic Synthesis for Field-Programmable Gate Arrays. Boston, MA: Springer US, 1995.

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Capítulos de livros sobre o assunto "Field Programmable Gate Arrays"

1

Gu, Changyi. "Field-Programmable Gate Arrays". In Building Embedded Systems, 191–231. Berkeley, CA: Apress, 2016. http://dx.doi.org/10.1007/978-1-4842-1919-5_9.

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2

Barkalov, Alexander, Larysa Titarenko e Małgorzata Mazurkiewicz. "Field Programmable Gate Arrays". In Foundations of Embedded Systems, 81–106. Cham: Springer International Publishing, 2019. http://dx.doi.org/10.1007/978-3-030-11961-4_4.

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3

de Dinechin, Florent, e Martin Kumm. "Field Programmable Gate Arrays". In Application-Specific Arithmetic, 87–100. Cham: Springer International Publishing, 2023. http://dx.doi.org/10.1007/978-3-031-42808-1_4.

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4

Brown, Stephen D., Robert J. Francis, Jonathan Rose e Zvonko G. Vranesic. "Introduction to FPGAs". In Field-Programmable Gate Arrays, 1–11. Boston, MA: Springer US, 1992. http://dx.doi.org/10.1007/978-1-4615-3572-0_1.

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5

Brown, Stephen D., Robert J. Francis, Jonathan Rose e Zvonko G. Vranesic. "Commercially Available FPGAs". In Field-Programmable Gate Arrays, 13–43. Boston, MA: Springer US, 1992. http://dx.doi.org/10.1007/978-1-4615-3572-0_2.

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6

Brown, Stephen D., Robert J. Francis, Jonathan Rose e Zvonko G. Vranesic. "Technology Mapping for FPGAs". In Field-Programmable Gate Arrays, 45–86. Boston, MA: Springer US, 1992. http://dx.doi.org/10.1007/978-1-4615-3572-0_3.

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7

Brown, Stephen D., Robert J. Francis, Jonathan Rose e Zvonko G. Vranesic. "Logic Block Architecture". In Field-Programmable Gate Arrays, 87–115. Boston, MA: Springer US, 1992. http://dx.doi.org/10.1007/978-1-4615-3572-0_4.

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8

Brown, Stephen D., Robert J. Francis, Jonathan Rose e Zvonko G. Vranesic. "Routing for FPGAs". In Field-Programmable Gate Arrays, 117–45. Boston, MA: Springer US, 1992. http://dx.doi.org/10.1007/978-1-4615-3572-0_5.

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9

Brown, Stephen D., Robert J. Francis, Jonathan Rose e Zvonko G. Vranesic. "Flexibility of FPGA Routing Architectures". In Field-Programmable Gate Arrays, 147–67. Boston, MA: Springer US, 1992. http://dx.doi.org/10.1007/978-1-4615-3572-0_6.

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10

Brown, Stephen D., Robert J. Francis, Jonathan Rose e Zvonko G. Vranesic. "A Theoretical Model for FPGA Routing". In Field-Programmable Gate Arrays, 169–90. Boston, MA: Springer US, 1992. http://dx.doi.org/10.1007/978-1-4615-3572-0_7.

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Trabalhos de conferências sobre o assunto "Field Programmable Gate Arrays"

1

Jyothi, Vinayaka, Ashik Poojari, Richard Stern e Ramesh Karri. "Fingerprinting Field Programmable Gate Arrays". In 2017 IEEE 35th International Conference on Computer Design (ICCD). IEEE, 2017. http://dx.doi.org/10.1109/iccd.2017.58.

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2

DeHon, A. "Entropy, Counting, and Programmable Interconnect". In Fourth International ACM Symposium on Field-Programmable Gate Arrays. IEEE, 1996. http://dx.doi.org/10.1109/fpga.1996.242346.

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3

Pérez López, Daniel, Aitor López Hernández, Andrés Macho Ortiz, Prometheus DasMahapatra e José Capmany Francoy. "Towards field-programmable photonic gate arrays". In Smart Photonic and Optoelectronic Integrated Circuits XXII, editado por Sailing He e Laurent Vivien. SPIE, 2020. http://dx.doi.org/10.1117/12.2551289.

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4

Chow, P., P. G. Gulak e P. Chow. "A Field-Programmable Mixed-Analog-Digital Array". In Third International ACM Symposium on Field-Programmable Gate Arrays. IEEE, 1995. http://dx.doi.org/10.1109/fpga.1995.242048.

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5

Lombardi, F., D. Ashen, Xiaotao Chen e Wei Kang Huang. "Diagnosing Programmable Interconnect Systems for FPGAs". In Fourth International ACM Symposium on Field-Programmable Gate Arrays. IEEE, 1996. http://dx.doi.org/10.1109/fpga.1996.242436.

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6

Tong Liu, Wei Kang Huang e F. Lombardi. "Testing of Uncustomized Segmented Channel Field Programmable Gate Arrays". In Third International ACM Symposium on Field-Programmable Gate Arrays. IEEE, 1995. http://dx.doi.org/10.1109/fpga.1995.242145.

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7

Vi Cuong Chan e D. M. Lewis. "Area-Speed Tradeoffs for Hierarchical Field-Programmable Gate Arrays". In Fourth International ACM Symposium on Field-Programmable Gate Arrays. IEEE, 1996. http://dx.doi.org/10.1109/fpga.1996.242343.

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8

Lamoureux, Julien, e Steven Wilton. "Activity Estimation for Field-Programmable Gate Arrays". In 2006 International Conference on Field Programmable Logic and Applications. IEEE, 2006. http://dx.doi.org/10.1109/fpl.2006.311199.

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9

Bratt, A., e I. Macbeth. "Design and Implementation of a Field Programmable Analogue Array". In Fourth International ACM Symposium on Field-Programmable Gate Arrays. IEEE, 1996. http://dx.doi.org/10.1109/fpga.1996.242434.

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10

Chan, Pak K., e Martine D. F. Schlag. "Parallel placement for field-programmable gate arrays". In the 2003 ACM/SIGDA eleventh international symposium. New York, New York, USA: ACM Press, 2003. http://dx.doi.org/10.1145/611817.611825.

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Relatórios de organizações sobre o assunto "Field Programmable Gate Arrays"

1

Mumbru, Jose, George Panotopoulos e Demetri Psaltis. Optically Programmable Field Programmable Gate Arrays (FPGA) Systems. Fort Belvoir, VA: Defense Technical Information Center, janeiro de 2004. http://dx.doi.org/10.21236/ada421336.

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2

Stepaniak, Michael J., Maarten Uijt de Haag e Frank Van Graas. Field Programmable Gate Array-Based Attitude Stabilization. Fort Belvoir, VA: Defense Technical Information Center, julho de 2008. http://dx.doi.org/10.21236/ada485525.

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3

Manohar, Rajit. Experimental 3D Asynchronous Field Programmable Gate Array (FPGA). Fort Belvoir, VA: Defense Technical Information Center, março de 2015. http://dx.doi.org/10.21236/ada614130.

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4

Wawrzynek, J., e K. Asanovic. Field-Programmable Gate Array (FPGA) Emulation for Computer Architecture. Fort Belvoir, VA: Defense Technical Information Center, agosto de 2009. http://dx.doi.org/10.21236/ada519578.

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5

Tyler, Stephen C. The Design of a Frequency Domain Interference Excision Processor Using Field Programmable Gate Arrays. Fort Belvoir, VA: Defense Technical Information Center, janeiro de 2005. http://dx.doi.org/10.21236/ada432369.

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6

Wirthlin, Michael, Brent Nelson, Brad Hutchings, Peter Athanas e Shawn Bohner. Future Field Programmable Gate Array (FPGA) Design Methodologies and Tool Flows. Fort Belvoir, VA: Defense Technical Information Center, julho de 2008. http://dx.doi.org/10.21236/ada492273.

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7

Manohar, Rajit. A Secure and Reliable High-Performance Field Programmable Gate Array for Information Processing. Fort Belvoir, VA: Defense Technical Information Center, março de 2012. http://dx.doi.org/10.21236/ada559184.

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8

Learn, Mark Walter. Evaluation of soft-core processors on a Xilinx Virtex-5 field programmable gate array. Office of Scientific and Technical Information (OSTI), abril de 2011. http://dx.doi.org/10.2172/1013229.

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9

Lin, Chun-Shin. High Speed Publication Subscription Brokering Through Highly Parallel Processing on Field Programmable Gate Array (FPGA). Fort Belvoir, VA: Defense Technical Information Center, janeiro de 2010. http://dx.doi.org/10.21236/ada514601.

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10

Bobrek, Miljko, Don Bouldin, David Eugene Holcomb, Stephen M. Killough, Stephen Fulton Smith e Christina D. Ward. Survey of Field Programmable Gate Array Design Guides and Experience Relevant to Nuclear Power Plant Applications. Office of Scientific and Technical Information (OSTI), setembro de 2007. http://dx.doi.org/10.2172/991174.

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