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1
Strand, Martin. "Verifiable Shuffled Decryption". Thesis, Norges teknisk-naturvitenskapelige universitet, Institutt for matematiske fag, 2013. http://urn.kb.se/resolve?urn=urn:nbn:no:ntnu:diva-21427.
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We describe the Verifiable Shuffled Decryption problem, and present five solutions based on adapting several existing verifiable shuffles. All but one may have potential for implementation, the choice of which would depend on the required level of security and computational restrictions given by the available hardware.
2
Burman, Annie. "Gendering decryption - decrypting gender : The gender discourse of labour at Bletchley Park 1939-1945". Thesis, Uppsala universitet, Historiska institutionen, 2013. http://urn.kb.se/resolve?urn=urn:nbn:se:uu:diva-201046.
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3
Takagi, Tsuyoshi. "New public-key cryptosystems with fast decryption". Phd thesis, [S.l. : s.n.], 2001. http://deposit.ddb.de/cgi-bin/dokserv?idn=962729302.
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4
Käck, Emil. "TLS Decryption in passive monitoring system with server private key". Thesis, Umeå universitet, Institutionen för datavetenskap, 2021. http://urn.kb.se/resolve?urn=urn:nbn:se:umu:diva-184490.
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Many network operators need to be able to ensure that customers get the level of service they pay for. To avoid bandwidth and server performance bottlenecks, and easily troubleshoot network problems, the network providers need to be able to see what payload data is sent. Modern networks encrypt data when sending it between nodes that makes passive monitoring more complex. A prevalent encryption mechanism on an IP-based network is TLS that needs to be decrypted. This article’s purpose is to check if it is possible to decrypt TLS traffic in a passive monitoring system with the server’s private key. This is done by implementing a decryptor in a passive monitoring system in the programming language Java. The implemented solution intercepts the traffic, takes out relevant data from the traffic, and derives the session key from that data. How this is done is dependent on what cipher suite is used for the session. Because of delimitations and lack of time the solution is only able to decrypt the cipher suite TLS_RSA_WITH_AES_128_CBC_SHA256. The result showed that it is possible to decrypt TLS traffic and should be possible for more than the specified cipher suite. But there exists a major problem that's called forward secrecy. This is used in the key exchange algorithm called Diffie–Hellman and makes it impossible to decrypt with only server private key. The conclusion is that it is possible but because of forward secrecy, it is not recommended. TLS 1.3 only uses cipher suites with the key exchange algorithm Diffie–Hellman and the forward secrecy functionality is important for security.
5
Merz, Doug, e Bruce Maples. "Encrypt/Decrypt COMSEC Unit for Space-based Command and Telemetry Applications". International Foundation for Telemetering, 2003. http://hdl.handle.net/10150/605565.
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International Telemetering Conference Proceedings / October 20-23, 2003 / Riviera Hotel and Convention Center, Las Vegas, NevadaThis paper describes the system-level architecture and design concept of a communications security (COMSEC) equipment intended for space-based low data rate (< 1 Mbps) command and telemetry applications. The COMSEC Unit is a stand-alone piece of equipment which provides decryption of uplink command and control information and encryption of downlink telemetry data. The system-level architecture is described followed by an overview of the digital design concepts and a discussion of applications. Finally, although specifically targeted for narrowband command and telemetry applications, this design approach is flexible enough to accommodate other algorithms of choice as well as operate in higher data rate applications.
6
Loban, H. "A VHDL Implemetation of the Advanced Encryption Standard". Thesis, NURE, MC&FPGA, 2019. https://mcfpga.nure.ua/conf/2019-mcfpga/10-35598-mcfpga-2019-014.
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7
Greinsmark, Carl. "Ransomware". Thesis, Högskolan Kristianstad, Fakulteten för naturvetenskap, 2020. http://urn.kb.se/resolve?urn=urn:nbn:se:hkr:diva-20695.
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This thesis researches different ransomwares, how we can stop them and how their threat vectors work. It is important to notice that when solving one ransomware doesn’t solve the next incoming one. In this thesis we investigate six different ransomwares that spread between 2016-2019. We investigate the encryption methods, the different threat vectors, infection spreading and how to prevent from them by doing a theoretical and practical study. The results show that after infection of a ransomware, it encrypts the data instantaneously on the system. Fortunately, to keep information safe there are few prevention methods such as anti-virus software and a few prototypes created that is not currently released one is called PayBreak for Windows 7 and tests to find a solution through flash memory.
8
Samuel, David. "RFID security in door locks". Thesis, Linköping University, Department of Computer and Information Science, 2008. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-12186.
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Radio frequency identification, RFID is a technology that is used in many fields including locks. The unlimited access to the reader and the transponder has resulted in severe security weaknesses and made it possible to apply different attacks. To classify door locks as secure they must at least fulfil two main criteria: the first is the use of a challenge-response authentication protocol and the second is to deploy sophisticated and secure algorithms.
MiFare classic and KeeLoq are two widely applied technologies that are still in use in many security critical applications and are considered to be secure but which have been broken by cryptanalysis and with modest efforts and cost.
How secure a certain solution is depends on how expensive it is to buy the equipment that can break the system and reveal the secret key and how secure a lock should be depends on the value of what it is protecting.
The dropping price of powerful computers and the availability of security related information on the web will lead to an increase of the number of attacks on different systems.
By the time this thesis is published those locks evaluated are not secure enough, to overcome the security shortage some improvements have to be made such as: the use of sophisticated algorithms, the use of longer key of at least 128-bit, the use of non-deterministic random number generators and the use of pure hardware solutions both in the receiver and the transmitter to reduce leakage.
9
Manteena, Rajender. "A VHDL Implemetation of the Advanced Encryption Standard-Rijndael Algorithm". Scholar Commons, 2004. https://scholarcommons.usf.edu/etd/1149.
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The National Institute of Standards and Technology (NIST) has initiated a process to develop a Federal information Processing Standard (FIPS) for the Advanced Encryption Standard (AES), specifying an Advanced Encryption Algorithm to replace the Data Encryption standard (DES) the Expired in 1998. NIST has solicited candidate algorithms for inclusion in AES, resulting in fifteen official candidate algorithms of which Rijndael was chosen as the Advanced Encryption Standard.
The Advanced Encryption Standard can be programmed in software or built with pure hardware. However Field Programmable Gate Arrays (FPGAs) offer a quicker, more customizable solution. This research investigates the AES algorithm with regard to FPGA and the Very High Speed Integrated Circuit Hardware Description language (VHDL). Altera Max+plus II software is used for simulation and optimization of the synthesizable VHDL code. All the transformations of both Encryptions and Decryption are simulated using an iterative design approach in order to minimize the hardware consumption. Altera ACEX1K Family devices are utilized for hardware evaluation.
10
Kundur, Abhinay. "Digital and Analog Signal Encryption and Decryption in Mid RF Range Using Hybrid Acousto-Optic Chaos". University of Dayton / OhioLINK, 2012. http://rave.ohiolink.edu/etdc/view?acc_num=dayton1336100009.
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11
Chaparala, Suman Krishna. "Secure Encryption and Decryption by Aperture Variations of a Photodetector in an Acousto-Optic Bragg Cell". University of Dayton / OhioLINK, 2016. http://rave.ohiolink.edu/etdc/view?acc_num=dayton1468527741.
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12
Kandi, Jayavardhan R. "Embedded Cryptography: An Analysis and Evaluation of Performance and Code Optimization Techniques for Encryption and Decryption in Embedded Systems". [Tampa, Fla.] : University of South Florida, 2003. http://purl.fcla.edu/fcla/etd/SFE0000151.
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13
Zhao, Weiliang, University of Western Sydney, of Science Technology and Environment College e School of Computing and Information Technology. "Security techniques for electronic commerce applications". THESIS_CSTE_CIT_Zhao_W.xml, 2003. http://handle.uws.edu.au:8081/1959.7/127.
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Electronic commerce and the internet provide greater opportunities for companies and individual person to be involved in commercial activities; the involved parties may not know or trust each other or may even be mutually suspicious of each other. The issue of fairness becomes more critical and must be well addressed. The aim of this thesis is to investigate security solutions with fairness for on-line transactions. A fair trading protocol with credit payment is proposed. The proof of equivalence of discrete logarithm to discrete loglogarithm is employed as the main tool to construct the protocol. The scheme provides a unique link between payment and gambling outcome so that the winner can be ensured to get the payment. Since an optimal fair exchange method is used in gambling message exchange, the proposed system guarantees that no one can successfully cheat during a gambling process. Our system requires an off-line Trusted Third Party (TTP). If cheating occurs, the TTP can resolve the problem and make the gambling process fair. An efficient and secure poker scheme is proposed. It is based on multiple encryption and decryption of individual cards. The protocol satisfies all major security requirements of a real mental poker. It gets rid of the Card Salesman and guarantees minimal effect due to collusion. The protocol is secure and more efficient compared with other known protocols. The strategies of players can be kept confidential with the introduction of a Dealer. The protocol is suitable to be implemented in an on-line gambling card game. The implementation of the fair on-line gambling protocol has been demonstrated and all utility classes for the implementation have been defined.Master of Science (Hons)
14
Lisoněk, David. "Šifrování SMS pro mobilní komunikaci". Master's thesis, Vysoké učení technické v Brně. Fakulta informačních technologií, 2008. http://www.nusl.cz/ntk/nusl-235448.
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This thesis deals with encryption of short text message (SMS) in mobile communication. Introduction is dedicated to overview of the parts of GSM radiotelephone nets and SMS messages transfer . Next chapter is reserved for description of cryptographic methods especially symetric and asymetric encryptografic aproaches. A design of a SMS messages encryption and decryption techniques is in next. For SMS encryption and sign, there is used the asymetric cypher RSA. Encryption use OAEP padding schema. The public key is saved in certificate. The Symbian OS has been choosen as a suitable platform for programming of mobile devices.
15
Špidla, Milan. "Možnosti narušení bezpečnosti bezdrátové přístupové sítě". Master's thesis, Vysoké učení technické v Brně. Fakulta elektrotechniky a komunikačních technologií, 2009. http://www.nusl.cz/ntk/nusl-218086.
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Master´s thesis „Security risks of wireless access networks“ deals with wireless access networks, which are the most widespread in this time. The main target is realization of attacks wireless access networks protected by various using methods. This thesis shows main securities gaps, which originate from project this networks. These securities gaps are used for realization attacts in practical part. In the next part I took attention of network´s monitoring possibilities.
16
Almehmadi, Fares Saleh S. "Secure Chaotic Transmission of Digital and Analog Signals Under Profiled Beam Propagation in Acousto-Optic Bragg Cells with Feedback". University of Dayton / OhioLINK, 2015. http://rave.ohiolink.edu/etdc/view?acc_num=dayton1426781250.
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17
Ringmann, Björn, e Peter Hildeblom. "Minnet sviker Aldrig : Att utnyttja volatil data i Krypterade system". Thesis, Högskolan i Halmstad, Sektionen för Informationsvetenskap, Data– och Elektroteknik (IDE), 2014. http://urn.kb.se/resolve?urn=urn:nbn:se:hh:diva-26424.
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When the use of encryption amongst the regular computer user grows morewidespread than ever it makes the life of the IT-forensics experts difficult.Hampering the judicial investigations that otherwise could have lead to convictions. In this report we will treat the subject of crypto analysis with a focus on decrypting files and devices encrypted with the software TrueCrypt. A solution will be presented that can facilitate the future work involving encryption. The application DFEAT that has been developed during the writings of this report is faster than the corresponding software EFDD, and attacks both partitions and bitwise copies of entire harddrives where PKF fails.DFEAT is a lightweight application that is almost 50 times smaller compared to EFDD and 200 times smaller than PKF's portable version.
18
Liljekvist, Erika, e Oscar Hedlund. "Uncovering Signal : Simplifying Forensic Investigations of the Signal Application". Thesis, Högskolan i Halmstad, Akademin för informationsteknologi, 2021. http://urn.kb.se/resolve?urn=urn:nbn:se:hh:diva-44835.
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The increasing availability of easy-to-use end-to-end encrypted messaging applications has made it possible for more people to conduct their conversations privately. This is something that criminals have taken advantage of and it has proven to make digital forensic investigations more difficult as methods of decrypting the data are needed. In this thesis, data from iOS and Windows devices is extracted and analysed, with focus on the application Signal. Even though other operating systems are compatible with the Signal application, such as Android, it is outside the scope of this thesis. The results of this thesis provide access to data stored in the encrypted application Signalwithout the need for expensive analysis tools. This is done by developing and publishing the first open-source script for decryption and parsing of the Signal database. The script is available for anyone at https://github.com/decryptSignal/decryptSignal.
19
Lien, E.-Jen, e 連一真. "Modular Large Number Encryption/Decryption Processor Design". Thesis, 1999. http://ndltd.ncl.edu.tw/handle/61653002071694188155.
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碩士國立臺灣大學
電機工程學研究所
87
Combined with the widely used electrical communication, cryptosystem becomes more and more important. If we want to keep each communication in high secret, we must apply cryptosystem. There exist two main types of cryptosystems. One is the public-key cryptosystem; the other is the secret-key cryptosystem. The most famous public-key cryptosystem is RSA cryptosystem. In a RSA cipher system, the bit length of the modulus is very big. Montgomery suggested a new algorithm, which can be implemented into hardware efficiently. So many people modified the original Montgomery's algorithm to achieve better hardware usage and less operation time. Chen and Yang are the most famous ones. In this Thesis, a modular encryption/decryption processor is introduced. This is a modified version of the systolic array Montgomery processor. Each basic unit is with 128 bits, but we can combine these units to build a large-bit RSA cryptosystem.
20
Chien, Chih-Feng, e 簡志峰. "A High Throughput Programmable Encryption/Decryption Processor". Thesis, 2007. http://ndltd.ncl.edu.tw/handle/71226350051530015461.
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碩士國立清華大學
產業研發碩士積體電路設計專班
95
The AES (Advanced Encryption Standard) algorithm is a new standard algorithm of symmetric-key cryptography system. In order to replace DES algorithm, the Rijndael’s algorithm was selected as the Advanced Encryption Standard (AES) by the National Institute of Standards and Technology (NIST). Cryptographic applications are often applied to application specific integrated circuit (ASIC) design as it is trusted in sufficient security level. However, fixed hardware implementations become more and more insecure because it is impossible to update or upgrade in response to new security threats. For high security level, a reconfigurable S-box utilized RAM based design is constructed in our AES design. And the reconfiguration of S-box can be generated by using our previous proposed pseudo random number generator (PRNG). The PRNG utilized to generate random numbers can construct the look-up table of S-box dynamically. The embedded memory of FPGA is exploited for the reconfigurable S-box in our proposed architecture. Using FPGA with embedded memory is the most cost-effective for RAM based design because for the balance of memory and logic resource. Mix/InvMix Column dominates both in the logic resource and the critical delay in AES hardware implementation with direct mapping S-boxes. The integrated Mix/InvMix Column circuit based on the proposed decomposition method optimizes the area and the delay. Theoretically, in architecture level, the proposed short-path circuit reduced the area up to 42% with the same 5 XOR gates delay in critical path. The FPGA of Altera Stratix family EP1S25F780C5 is used to implement our AES design. A 70 MHz clock is achieved, and the throughput is 0.898 Gbps for 128-bit keys.
21
Hsu, Ho-Kai, e 許賀凱. "An Encryption/Decryption Scheme for Smart Locks". Thesis, 2017. http://ndltd.ncl.edu.tw/handle/sbw28v.
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碩士國立臺灣科技大學
電機工程系
105
With the vigorous development of Internet of Things, more and more smart home’s products are popular. Smart lock is a basic product of smart-home, and it could make products be easier to show the convenience via technology. Although the smart lock is an elementary product, it is the most important home’s security. Therefore, how developers build a smart lock is a huge challenge. This paper proposes a mechanism with encryption and decryption for smart lock system which contains the One Password authentication protocol called Secure Remote Password, the fingerprint identification and the AES encryption. This system enables users to verify the identity with the mobile device through the fingerprint and server. After the authentication finishes, it will generate a set of temporary key which encrypts and decrypts the data in the transmission process which ensures the transmission’s security, and completes the unlock action. In addition, this system designed a mobile application logout-timed, a counter verification function and a hardware automatically locked which cannot be hacked. Besides, this system also designed a set of permission management approach. If people need to enter and exit the house, the lock of the administrator can add the temporary permission for opening certain period of time to enter and exit the house. If the permission is invalid, the lock’s administrator can remove the permission to ensure safety. If you want to look the history of the lock, you can search with a list of history. Finally, this paper based on the safety and stability considerations compares functions between this system with other systems, and builds a system different from door lock products on the market.
22
Lin, Mei-Ling, e 林美伶. "Elliptic Curve Encryption/Decryption IP for SoC Design". Thesis, 2006. http://ndltd.ncl.edu.tw/handle/rmrf83.
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碩士國立東華大學
資訊工程學系
94
Since network technique develops quickly, it has become important to provide the privacy and safety with transmitting messages. Compared to the presented cryptosystems, Elliptic Curve Cryptosystems (ECC) based on discrete logarithms offers the same security with a far smaller key size. However, the operation of the ECC is more complex than those of other cryptosystems. Thus, it can not achieve a high performance when using software to design and implement the ECC. In this paper, we use the hardware to design and implement an ECC chip based on . And we also propose a novel inverse algorithm to accelerate the performance of the chip. Furthermore, the interface of the chip is based on AMBA bus system. Our ECC chip with 155-bit key size can operate at 250MHz clock rate. Its throughput rate is 6.898086Mbps, and the Encryption time is 0.04ms.
23
Huang, Yu-Rong, e 黃昱融. "Text file encryption and decryption of laser printer". Thesis, 2015. http://ndltd.ncl.edu.tw/handle/gh7gbt.
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碩士國立中正大學
機械工程學系暨研究所
104
Printer identification based on a printed document can provide forensic information to protect copyright and verify authenticity. Some features generated by modulating EP process such like raggedness of the edge in the text, can be designed and utilized to help develop the extrinsic signature. In this thesis, we will investigate embedding extrinsic signature in text documents using laser intensity as a signal modulation source and develop extrinsic signatures using Kasami seuquence. The experimental results show that for a typical 40 point text document with 21 lines, 63 bits of information can be embedded per page.
24
Chang, Hsiang-Nien, e 張翔年. "Design of Efficient RC6 Encryption and Decryption Systems". Thesis, 2010. http://ndltd.ncl.edu.tw/handle/51646697241689813050.
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碩士國立東華大學
電子工程研究所
98
The RC6 algorithm is an effective encryption method proposed in recent years. It is a type of symmetric-key encryption, which not only provides enough data security but also supports simple 128-bit block cipher encryption. The key feature of the RC6 algorithm is that it uses large amount of data dependencies in its computation. This feature facilitates relatively less computation during the rotate operation stage in the core of the algorithm, while it still meets the data security requirements. Furthermore, the RC6 algorithm flexibly supports 128-bit, 192-bit and 256-bit key length. In this thesis, we present the efficient design of the RC6 cipher for encryption and decryption sharing the same hardware. Based on the analysis of the characteristics of the RC6 algorithm, we parallelize the operations of the independent data and use the same components. Furthermore, the design can be used for either encryption or decryption with limited hardware complexity. During runtime, it can generate the ciphertext from the plaintext or vice versa by controlling the data flow dynamically. We have implemented the VLSI design of the RC6 algorithm. The combinational circuits area can be saved for approximately 21% compared with the design using separate encryption and decryption hardware modules. The portion without combinational circuitry can be saved for approximately 50%. The whole circuitry can be saved for approximately 24% including both parts in the above.
25
Chang, Chien-Cheng, e 張建誠. "The Design of a RSA Encryption/Decryption Circuit". Thesis, 2000. http://ndltd.ncl.edu.tw/handle/61393486894775458082.
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碩士國立臺灣科技大學
電子工程系
88
The RSA encryption algorithm is widely used in communication and data security system. It takes much time to perform because of the RSA algorithm using more than 512-bit word lengths to guarantee security. Developing a high speed RSA encryption circuit which takes less gate count and can carry out its layout easily, will be a challenge. In this thesis, a 1024-bit RSA encryption circuit that is constructed by two 1024-bit adders is proposed. Based on the consideration of speed and regularity, a 1024-bit hierarchical carry skip adder consisting of 8 bits ripple adders is proposed. The adder only takes 9.4ns to perform a 1024-bit addition with 0.35μm SPQM cell library. The resulting RSA circuit can output a 10240-bit encrypted message every 22ms at the operating frequency of 72 MHz. Its die size is 3.7x3.7mm^2 and consumes 633mw. Moreover, the design of the proposed RSA circuit is modularized in a bit-sliced manner so that it can be expanded easily to a longer word length.
26
LIN, JING-CHI, e 林敬奇. "XOR Gate Design for Encryption and Decryption Circuit". Thesis, 2014. http://ndltd.ncl.edu.tw/handle/79570156697789872292.
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碩士東海大學
電機工程學系
102
With the rapid growth of portable device software, the communication security becomes more and more important. However, using traditional encryption/decryption scheme without special components results in huge power consumption and computation time. In this thesis, we propose the low power XOR/XNOR logic gates for Sbox/InvSBox circuits, which are greatly used in encryption/decryption schemes. Several typical and modern XOR/XNOR logic gates are implemented by BSIM-CMG technology and simulated by HSPICE. The simulation results show that the low power Sbox can be implemented by sixteen XOR2_3n3p gates, while the low power InvSBox can be implemented by six XOR3_8Tdinv gates with two XNOR3_8TSinv gates.
27
GAO, ZHI-MING, e 高志名. "Design FPGA Prototype for Video Encryption and Decryption". Thesis, 2013. http://ndltd.ncl.edu.tw/handle/42443168945074536984.
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碩士中華科技大學
電子工程研究所碩士班
101
With the development of video camera technology, the portable video camera such as digital cameras, car camera recorders, smart phones are widely used. Nowadays, with video camera lens continuous progress, electronic products have multi-media video functions such that we can share images more conveniently. ”Every Solution Breeds the New Problems.” With that powerful device, the information security and personal privacy are becoming the huge problems that we should handle. Therefore, the real time image protection is very important. In this thesis, a video image development platform based on real time image protection is studied. The real time image uses encryption and decryption algorithm and mode structure to perform the image data security protection. The traditional security protection is by software. its complication of security level demand and encryption and decryption algorithm adds much load to the processor and it will reduce the efficiency of the processor. In addition, the software encryption or decryption has the security risk, it is easier to be attacked. Therefore, this study uses FPGA hardware chip to achieve the encryption and decryption algorithm and also combine the webcam as the hardware protection. Other than the upgrade of hardware security, it also integrates the video system as a platform. The hardware chip can perform AES cipher and 4 types of operation mode (ECB、CBC、CFB、OFB) and also hybrid mode. It can achieve the video data security protection. Furthermore, this study presents a defect of the ECB mode structure to bring up hybrid operation mode of ECB+CBC, also to improve weakness of the ECB mode structure. Besides, with hardware mode structure for the whole security protection, and provided for studying the design of video image development platform. Keywords: FPGA Prototype, Advanced Encryption Standard (AES), Video Security
28
Lin, Lian-Yuan, e 林連源. "A Study of Fuzzy-based Encryption and Decryption". Thesis, 2007. http://ndltd.ncl.edu.tw/handle/00577121938949825042.
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碩士國立臺灣師範大學
應用電子科技研究所
95
Many methods of cryptography are available nowadays. They are used in several situations such as financial processing system, electronic commerce and electronic data interchange. Each has its own specific purpose and implementation algorithm. But no one is without any disadvantage even the best policy is carried on. The thesis proposed a method based on Fuzzy Theory to improve the information security by increasing the complexity of decryption for fuzzy-based encryption source data. The simulation results of security quality are better than former cryptographies as in this paper. Thus, the fuzzy-based encryption algorithm can be used in cryptosystem if needed.
29
Chuang, Ming-Chuan, e 莊銘權. "Suitable for JPEG 2000 Image Encryption/Decryption Scheme". Thesis, 2007. http://ndltd.ncl.edu.tw/handle/85047454584863342890.
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碩士國防大學中正理工學院
電子工程研究所
96
Image encryption is a very important part for image security. Image compression technologies change with each passing day. They not only improve compression efficiency, but also provide a rich set of features for a variety of applications. Therefore, an efficient image encryption method should be developed according to the characteristics of the compression technique itself. JPEG 2000 is an emerging standard for still image compression. JPEG 2000 provides various functionalities to solve the problems for different image applications and possibly become a most popular image format. Therefore, JPEG 2000 image encryption has become a hot topic for image security. One of the important properties of JPEG 2000 codestream is that the two consecutive bytes in the packet body should be in the interval [0x0000, 0xFF8F] so that a standard JPEG 2000 decoder can exactly decode the JPEG 2000 compressed codestream. This is so called the compatibility of JPEG 2000 and should be followed by an effective JPEG 2000 encryption method. This thesis proposes a cryptography-based JPEG 2000 image encryption technique which uses the stream cipher to encrypt the JPEG 2000 codestream. To be compatible with the syntax of JPEG 2000, the proposed technique replaces the syntax non-compliant bytes with syntax compliant bytes and records the positions of these bytes as the deciphering information. The deciphering information is then embedded in the header of the JPEG 2000 codestream making use of the characteristics of the syntax of the JPEG 2000 to facilitate the decryption in the decoding side. Experimental results show that the proposed JPEG 2000 image encryption scheme not only can be compliant with the syntax of JPEG 2000, but also can encrypt the entire packets of the JPEG 2000 codestream. That is, the proposed technique has good compatibility and security. Moreover, because the extra deciphering information generated in the encryption process is very small, the proposed technique is also compression equivalent. According to the good properties mentioned above, the proposed JPEG 2000 image encryption technique can provide effective protection of JPEG 2000 images in various applications.
30
Lin, Guang-Huei, e 林光輝. "Design and Implementation of an Encryption/Decryption Coprocessor". Thesis, 1998. http://ndltd.ncl.edu.tw/handle/09525687797215334610.
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碩士國立臺灣大學
電機工程學系
86
As internet becomes popular today, more and more services will operate on internet, e.g., internet market, electronic bank, and electronic government. These services require high data security in network communication, such that encryption of data transfering between server and client is necessary. Higher data security indicates more complex cryptography computation. Two cryptosystems are using today for internet services, one is the symmetric-key cryprtosystem, and another is the public-key cryptosystem. The symmetric-key cryptosystem is used for information transfer, and the public-key cryptosystem is used for identification. For example, DES(Data Encryption Standard) algorithm is known as a symmetric-key cryptosystem, and RSA (Rivest-Shamir-Adelman) algorithm is a public-key cryptosystem. Though these two algorithms generate good data security, the amount of computations is very large, such that a general central processing unit (CPU) cannot timely complete the computations, and a hardware coprocessor is required to assist CPU. In this Thesis, an encryption/decryption coprocessor is designed to assist a core microprocessor to compute the cryptographic operations.
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Chang, Fu-Hsiang, e 張富翔. "Design and Implementation of a Twofish Encryption/Decryption Chip". Thesis, 2002. http://ndltd.ncl.edu.tw/handle/02068072808655441304.
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碩士國立東華大學
資訊工程學系
90
In 1997, NIST (National Institute of Standards and Technology) announced the Advanced Encryption Standard (AES) program to replace DES. NIST’s call design criteria are block cipher, a longer key length, larger block size, faster speed, and greater flexibility. Twofish was one of those schemes that meet NIST’s design criteria for AES. In a cipher, complicated round functions are harder to analyze and are not always better than simple ones. Hence, one of the guiding principles of Twofish is that the round function should be simple enough. With enough rounds, simple round functions can achieve the security requirement. Twofish is a 128-bit symmetric block cipher with key lengths of 128 bits, 192 bits, and 256 bits. The cipher is composed of 16 rounds built similarly to the Feistel network structure. A VLSI design and implementation of the Twofish block cipher is presented. This cipher is a 16-round Feistel-like network. The modification of the Feistel structure includes XOR operation and rotation by one bit. In this thesis, we present a pipelined structure for the VLSI implementation of the Twofish block cipher. Pipelined structure makes the chip operate faster. In our design, the chip performs data encryption, data decryption, and key generation in a single hardware unit. We have implemented this cipher with 0.35μm CMOS technology and the chip area is around 2.34mm by 2.34mm.
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Wisdom e 陳忠智. "A Study on Chip Design of Symmetric Encryption/Decryption". Thesis, 2006. http://ndltd.ncl.edu.tw/handle/91780663138130828909.
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碩士中華技術學院
電子工程研究所碩士班
94
This thesis is to study the IP (Intellectual Property) implementation of three types of symmetric encryption / decryption algorithms on DES, Triple DES and AES. This thesis show, how to simplify the algorithm of the round redundant circuit, reduce the logic element in the FPGA, and improve the performance efficiently. After the optimization, the performance rate is up to 1,368Mbps and 1,892 Mbps respectively for DES & AES function. These IP design is based on the popular low cost FPGA, it integrated the DES, Triple DES and AES in one single chip. The prototype passed the compliance test with NIST & FIPS document for its accuracy; meanwhile, it proved that this is a cost-saving solution in short developing time. In addition to the above complex algorithm design, this thesis also reveals the implementation of the 10-bit Key length as well as 8-bit of simplified DES algorithm. Along with this design, it also presents a significantly simplified Sub-Key generator, which will make the function design simpler and meet the full custom design flow criteria. The development of this ASIC (Application Specific Integrated Circuit) is sponsored by CIC (Chip Implementation Center) and fabricated by TSMC 0.35μm process. After finishing IC test, the result shows completely unmistakable, and achieves the encryption algorithm which to realize the goal of the ASIC.
33
Jwo, Hung-Ming, e 卓宏洺. "Research of RSA Encryption/Decryption Based on Embedded System". Thesis, 2006. http://ndltd.ncl.edu.tw/handle/tcf94z.
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碩士國立臺灣科技大學
電子工程系
94
Human life gets more and more dependent on internet as it grows rapidly. By means of internet, we can not only transfer text, audio, and video data, but also buy goods and pay for them. But in a public domain like internet, private personal information can be captured easily and therefore encryption is necessary to prevent captured data readable. Based on a developing platform with Samsung S3C2410 as its CPU, this thesis develops a internet transfer application that encrypts files with RSA before sending out via internet, and decrypts them after receiving at receiver end. RSA is currently the most popular public key cryptographic system. It's quite appropriate to use when transferring private information under public domain and it can also be used for digital signature and identification certification. S3C2410, a touch-panel-supported CPU produced by Samsung, is considered suitable for mobile devices such as PDA. Linux, the operating system we use on the developing platform, is capable of great portability, efficient network transfer, support for a great deal of peripherals, and short time to market, and most important of all is that it's open source.
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Prangjarote, Panyaporn, e Panyaporn Prangjarote. "Multimedia Content Protection via Joint Fingerprinting and Decryption Framework". Thesis, 2014. http://ndltd.ncl.edu.tw/handle/90094479620115056335.
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博士亞洲大學
資訊工程學系
102
With the advancement of the Internet and development of multimedia technology, multimedia data have been an ease to access and distribute from one place to another. Obviously, the multimedia data can be protected before and after transmission by multimedia encryption, but data security after decryption against illegal users are critical and urgent. Only combination of encryption and fingerprinting, generally known as joint fingerprinting and decryption (JFD), can provide both confidentially and proper usages suitable for multimedia content protection. Inspired by the conventional JFD framework, where the encryption process is performed at the sender side before transmission, and the fingerprint embedding and decryption processes are performed at the receiver side simultaneously, this dissertation presents the JFD scheme adopting three new different approaches, namely, the joint fingerprinting and decryption for vector quantization in resistance to noise, a reversible joint fingerprinting and decryption for vector quantization images, and a sub-pixel encryption and sub–block decryption-based fingerprinting scheme. The first scheme is made up from two encryption techniques, which encrypt a host image on the sender side. The first technique uses static key-trees and while the second adopts dynamic key-trees, a simplified version of the first technique. In decryption phase, when the subscriber receives the encrypted images, these images are jointly decrypted and fingerprinted and are slightly different from the original images. The experimental results show that the encrypted image is unintelligible, and the recovered image has desirable image quality resistant to noise interference. Another JFD scheme, that is the extension of previous idea, includes reversibility mechanism developing from side match vector quantization(SMVQ). With reversibility property of SMVQ, the proposed scheme can extract the fingerprint without referring to the original image; that is, the fingerprinted copy can be completely recovered to the un-fingerprinted version. The experimental results show that the proposed scheme can achieve high perceptual security (with PSNR below 12 on average), high fingerprinted visual quality (with PSNR above 28 on average), and desirable fingerprint payload (about 0.6 bit/per block). A low complexity joint fingerprint and decryption (JFD) scheme based on exclusive-or operations has been proposed. The scheme encrypts only sub-pixels of the entire image using a tiny lookup table generated by a stream cipher. In the decryption process, some pixels can be completely recovered and the fingerprinting process depends on four different directions of sub-image blocks. The method successfully leaves the user’s fingerprint during decryption and produces slightly different media copies. The experimental results show that the proposed scheme is highly effective in terms of perceptual security and fingerprinted visual quality.
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Hu, Chia-Ming, e 胡家銘. "The Study of Data Decryption Process of Electronic Documents". Thesis, 2013. http://ndltd.ncl.edu.tw/handle/57613619561601142563.
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碩士醒吾科技大學
資訊科技系所
101
The existing Web-based document system in file transfer process, to achieve the contents cannot be copied and altered from an official document in file transfer system are major difficulties of the management problem. Using public key encryption to ensure the electronic documents system is securitized. Through certification to confirm users to achieve non-repudiation, the file transfer creation of a safe environment is the basic needs of the enterprise. This research uses the office automation systems in a closed network, and achieves the simplicity and ease of transfer document to encrypt the unencrypted file. The transferred file was digitally signed and has processed a document for encryption and decryption capabilities. Once the documents have encrypted the unencrypted document procedures, this file can have the effect of non-repudiation and integrity through text encryption technology. This study just uses a part of the document in the file encoding, to verify that the various encryption technologies can achieve these characteristics. This study also tests AES encryption speed comparisons and differences. Other research structures and functional classification of document management systems can modify the scope and flexibility to achieve optimization as ours goal.
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陳嘉耀. "An Efficient Decryption Method for RSA Cryptosystem And Implementation". Thesis, 2005. http://ndltd.ncl.edu.tw/handle/71835300207564971666.
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Pujari, Abhisek, e Chandan Padhi. "Encryption & Decryption of Data in GF (13n) Field". Thesis, 2009. http://ethesis.nitrkl.ac.in/457/1/thesis_9006-09.pdf.
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Cryptography is the science of using mathematics to encrypt and decrypt data. Cryptography enables you to store sensitive information or transmit it across insecure networks (like the Internet) so that it cannot be read by anyone except the intended recipient.
Cryptographic strength is measured in the time and resources it would require to recover the plaintext. The result of strong cryptography is cipher text that is very difficult to decipher without possession of the appropriate decoding tool.
A cryptographic algorithm, or cipher, is a mathematical function used in the encryption and decryption process. A cryptographic algorithm works in combination with a key — a word, number, or phrase — to encrypt the plaintext. The same plaintext encrypts to different cipher text with different keys. The security of encrypted data is entirely dependent on two things: the strength of the cryptographic algorithm and the secrecy of the key.
With growing dependencies on secure information transfer and data security in this information age the requirement for a strong method of securing data is always in demand.
In this project , we have tried to device a new means of securing data by encryption and decryption in GF(13). The reason for using GF(13) is that much research has been done on GF(2) but the GF(13) field is still mostly untouched. Hence there is much scope for designing versatile techniques which will be both secure and faster. This will again reduce the probability of anonymous decryption by undesirable agents. Such technique can be the future of data security with wide application in every field starting with military application, internet security, wireless data transfer and many more.
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Bih-Ching, Yeh. "512-bit RSA Public Key Data Encryption/Decryption Chip Design". 1997. http://www.cetd.com.tw/ec/thesisdetail.aspx?etdun=U0009-0112200611290358.
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Tung, Li-Chung, e 董力中. "Design and Implementation of an Asynchronous AES Encryption/Decryption Chip". Thesis, 2002. http://ndltd.ncl.edu.tw/handle/90903697099582779167.
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碩士國立東華大學
資訊工程學系
90
When people transmit information over data network, hackers may attack it. Hence, the security of information is a critical issue. National Bureau of Standards (NBS) announce the Data Encryption Standard (DES) as the encryption scheme in 1977. As technology advances, the computer operates faster and faster. The DES is no longer a safe scheme security. Due to this, Rijndael is selected as the Advanced Encryption Standard (AES) in 2000 by NIST. Rijndael is a symmetric block cipher, and it allows scalable block length and the key length is 128, 192 and 256 bits. It has the properties of simplicity, high speed and proper security. To realize an AES cipher, low power and high performance are essential design issues. This thesis presents design for the AES cipher. We combine encryption and decryption in a single chip. The design of our AES cipher uses the asynchronous architecture and micropipeline technology. There is no clock in our circuit. We use the signals request and acknowledge to control the data path instead. Since the design does not need the clock, there is no problem for generation clock tree or clock skew in a VLSI chip. Power also can be reduced since there is almost no power consumption generated by clock switch. The pipeline design allows the chip to process more data at the same time, and hence the throughput of the cipher is increased. We have implemented the design in a VLSI chip. The chip size is 5.36 mm x 5.36 mm, and the gate count is 51 K with 36 256x8 ROM and four 16x32 RAM. The throughput is 1.16 Gbit/s and the power dissipation is 474 mW. Our results show that the design is feasible and achieves good performance.
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Takagi, Tsuyoshi [Verfasser]. "New public-key cryptosystems with fast decryption / von Tsuyoshi Takagi". 2001. http://d-nb.info/962729302/34.
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Chen, Yan-Chiau, e 陳彥樵. "Firmware Encryption and Decryption Using 2.43 GHz Digital Wireless Transceiver". Thesis, 2010. http://ndltd.ncl.edu.tw/handle/vd9p2e.
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碩士國立臺北科技大學
電腦與通訊研究所
98
This thesis partitions mainly into two parts, one is the encryption/decryption of the data packet to be communicated and the other is the wireless transmission interface. The format of the wireless data packet generated by the 2.4 GHz UBEC UZ2400 transceiver module is IEEE 802.15.4-compliant. The data packet comprises the following various fields: preamble, start of frame, frame length, frame control, sequence number, addressing information, payload data, and frame check sequence (FCS). For the data encryption/decryption, the Advanced Encryption Standard (AES) algorithm is investigated and applied to enhance the security of the wireless communications undertaken. The AES algorithm is entirely based on finite field arithmetic and very structured accordingly. AES has been studied, analyzed, and discussed in detail. Moreover, the Microchip PIC16LF877A microcontroller and its 35 PIC16 assembly language instructions are utilized to implement AES to achieve enhanced security for the digital wireless transmission/reception over the open space. As to the wireless interface, the configuration registers of the RF transceiver modules are properly set through the 4-wire serial peripheral interfaces (SPI) by microcontrollers to ensure proper functioning of the entire digital RF transceiving system. Lastly, the communication reliability and range are tested in various open sites.
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Zeng, Xi-Zhe, e 曾希哲. "The Design and Analysis of a RSA Encryption/Decryption Chip". Thesis, 2000. http://ndltd.ncl.edu.tw/handle/36112321014998661900.
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碩士國立海洋大學
電機工程學系
88
The role of cryptography is more important to prevent the computer- and communication-based crime in recent years. Many applications of cryptographic methods have been proposed recently from electronic mail, trading, and banking to network security. In this thesis, the implementation of a 512 bits public key cryptosystem of RSA encryption/decryption chip is presented based on the Montgomery algorithm to simplify the complexity of exponential modular operation in RSA algorithm. The architecture of chip includes two components: modular and multiplier that are implemented based on the 257 bits pipelining systolic array to achieve a low die area. We applied the VHDL (VHSIC Hardware Description Language) to accomplish its design entry. This chip completed by using FPGA (Field Programmable Gate Array). It’s clock rate can reach 43.5 MHz and the baud rate is 28.2 Kbits/sec.
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Chung, Yuan-Hao, e 鍾元浩. "The Design and Implementation of a SERPENT Encryption/Decryption Chip". Thesis, 2005. http://ndltd.ncl.edu.tw/handle/88507663227267182029.
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碩士國立臺灣海洋大學
資訊工程學系
93
Security and privacy is an important issue in the future. Cryptography is one of the key features of security. Using hardware implementation can provide faster and more secure solution than software implementation. Recently, the Internet is so popular in the world and the required bandwidth is as large as possible. The encryption of the digital data becomes more important. The SERPENT cryptosystem is considered as the securest in the AES candidates. This paper presents the design and implementation of a SERPENT prvite key cryptosystem based on pipeline architecture and on-the-fly subkey generator. We use pipeline scheme to improve throughput. The on-the-fly subkey generator in SERPENT cryptosystem is applied to reduce the chip size. The cryptosystem was implemented with the TSMC 0.35 μm process and its die size is 3.62×3.62 μm2. Average baud rate can reach 784 Mbps under a 98 MHz clock.
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Chen, Taoan, e 陳道安. "The Implement of a 1536 bits RSA Encryption/Decryption Chip". Thesis, 2001. http://ndltd.ncl.edu.tw/handle/51664063897658558255.
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碩士國立海洋大學
電機工程學系
89
It is obviously that security issues will play an important role in the majority of future computer and communication systems. Cryptographic algorithms and their software/hardware implementations are the major tools to achieve the system security. In this thesis, a 1536 bits RSA encryption/decryption chip based on the Montgomery algorithm is presented. The main structure of this chip includes an encryption/decryption module and a 64K*32 SRAM. The 32 bits encryption/ decryption module is implemented using Altera EFP10K200SRC240-1. Based on the same structure, a 1536 bits encryption/decryption module can be constructed easily using Altera EP20k400EBC 652-1 and has the expected 8.86 Kbps baud rate at the 40.83 clock rate.
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ZHENG, YANG-JUN, e 鄭仰均. "Study on Cloud Server Aided Computation for Encryption and Decryption". Thesis, 2018. http://ndltd.ncl.edu.tw/handle/3rjxd5.
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碩士南臺科技大學
資訊工程系
106
With the development of cloud computing in recent years, the large number of cryptographic algorithms that were only carried out on mobile devices in the past has now become available with the assistance of cloud servers. Clients (encryptors or decryptors) can take advantage of the powerful calculating ability of the cloud server to perform the complex computation. Once the clients receive the computing results, they could encrypt or decrypt the texts by combining the results. However, from the perspective of information security, this type of cryptographic algorithms needs to make sure the integrity of the parameters during the transmission among the senders, receivers, and cloud servers. Otherwise incorrect ciphertext or plaintext would occur. This paper performs analysis on the protocol proposed by Shiraishi et al. and Lee et al, and points out the lack of security existing in the protocol. When under malicious attack, the cloud server could tamper with the temporary ciphertext, thus errors appear when the sender or the receiver is encrypting or decrypting text. This paper proposes a new protocol to correct this security flaw. Compared with the protocol raised by Shiraishi et al, the new protocol in this article is more efficient and safer. Compared with the protocol raised by Lee et al, this article ensures the security of the protocol with smaller amount of computation. “Design and Realization of A Probability Asymmetric Public-Key Encryption Scheme”, ECE in short, proposed by Guo et al. is an improvement based on the Cramer-Shoup cryptographic algorithm. ECE not only inherits the security of the Cramer-Shoup cryptographic algorithm, but it also enhances the efficiency of the algorithm. This study modifies ECE and combines the cloud server aided computation system to ensure the confidentiality during the transmission between the sender, cloud server, and receiver. The purpose is to prevent malicious attacks coming from cloud servers or intend attacks from fourth parties, thus the clients could use cloud server aided computation system to perform computation with confidence.
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Huang, Ching-Min, e 黃靖閔. "Design and Implementation of 1024-bit Systolic RSA Encryption/Decryption Chip". Thesis, 2000. http://ndltd.ncl.edu.tw/handle/24237273771142804259.
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碩士國立臺灣大學
電機工程學研究所
88
With the increasing popularity of electronic communications, data security is becoming a more and more important issue. There are two main types of cryptosystems. One is private-key cryptosystem, and the other is public-key cryptosystem. The most famous and popular public-key cryptosystem is RSA scheme. RSA scheme is composed of large bit-length modular multiplication and modular exponentiation in principle. Because of the high complexity of modular exponentiation, it is very difficult to factor it and obtain the private-key from the public-key. Montgomery suggested an efficient method for faster modular multiplication, and the algorithm is suitable for hardware implementation. Many paper proposed modified Montgomery''s algorithms to achieve better hardware usage and less operation time. Our RSA encryption/decryption chip basically follows the modified Montgomery''s algorithm proposed by Yang in 1998. This chip is composed of five units: serial-parallel multiplier, modulus systolic array, RAM controller, RAM module, and exponentiation controller. All 1024-bit data computations are divided into 32-bit data processing. The chip is implemented using 0.35um 1P4M CMOS technology.
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Tsai, Chu-Yuan, e 蔡志垣. "A Data Encryption and Decryption Device Implemented by An Embedded Platform". Thesis, 2007. http://ndltd.ncl.edu.tw/handle/75321813272128436722.
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碩士國立中興大學
電機工程學系所
95
Since the flourishing development of Internet, there are more and more applications on Internet. But when network uses more and more extensive, the privacy of personal materials getting more and more important. Thus, many kinds of security mechanism are used in various kinds of applications in cryptography. Unfortunately, although those mechanisms improvement the safe of material security, the overhead of system increases. This thesis using OCF to change hardware en/decrypt functionality provide by IXP425 into a device file, which will include into kernel support. OCF aims to bring full asynchronous HW/SW crypto acceleration to the Linux kernel and applications running under Linux. Using OCF can reduce overhead of system effectively and provide better performance.
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Huang, Wen-Lung, e 黃文龍. "PARTIAL FORMAT COMPLIANT MPEG VIDEO ENCRYPTION / DECRYPTION BASED ON CHAOS THEORY". Thesis, 2006. http://ndltd.ncl.edu.tw/handle/97121808368864369675.
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碩士大同大學
電機工程學系(所)
94
The security of multimedia data is more and more important for multimedia commerce. The encryption algorithms developed to secure text data may not be suitable to multimedia applications because of large data sizes and real time constraint. Different from military secrets or financial information, multimedia videos the information rate of multimedia videos is very high, but information value is very low. In the literatures, some existing light weight multimedia encryption techniques had been developed to avoid the exposure of multimedia content. To break such encryption code is much more expensive than to buy the programs. In recent years, the Chaos has been applied to the cryptography. This thesis is intended to take advantage of the features of the chaotic sequences to encrypt the video. We propose a chaos-based partial format compliant MPEG video encryption algorithm. Finally, the effectiveness of the proposed algorithm is demonstrated by software implementation.
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Lai, Ue-Ln, e 賴譽仁. "Hardware Architecture Design and Implementation of Elliptic Curve Encryption/Decryption Algorithms". Thesis, 2002. http://ndltd.ncl.edu.tw/handle/60556511931839409769.
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碩士國立臺灣科技大學
電子工程系
90
In this thesis, the VLSI architecture design and implementation of two 162-bit elliptic curve encryption/decryption chips are presented. One of them is based-on the IEEE 1363-2000 standard, and the other is based-on the arithmetic operations over extension field. All of the chips perform arithmetic operations over field on projective coordinates with optimal normal-basis representation. To provide the flexibility of interfacing with common microprocessors, the data bus width can be set to 8, 16, or 32 bits. The performance of extension-field-based chip is superior to that of standard-based chip at the same operating frequency in terms of bit rate, die size, and power consumption. The standard-based chip operates at 45 MHz and has bit rate of 44.1 kbps when realized on the Xilinx FPGA Virtex V400BG560. It operates at 125 MHz and has bit rate 122.7 kbps when realized on TSMC 0.35 um cell-based process. The resulting chip occupies 2.713*2.713mm^2 die area and consumes 133.98mW. The extension-field-based chip operates at 48 MHz and has bit rate of 94.2 kbps when realized on the Xilinx FPGA Virtex V400BG560. It operates at 125 MHz and has bit rate 245.4 kbps when realized on TSMC 0.35um cell-based process. The resulting chip occupies 2.541*2.541mm^2 die area and consumes 124.74 mW.
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Lai, SUAN-YUAN, e 賴士元. "The Design and Verification of a RSA Encryption/Decryption Intellectual Porperty". Thesis, 2004. http://ndltd.ncl.edu.tw/handle/41241755407620563913.
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碩士國立臺灣科技大學
電子工程系
93
The success of high-performance computers and high-speed networking brings us a high-speed information-exchanging network. People begin to setup electric commercial platform and transfer important information on the Internet. Since the Internet is a public channel, the networking security becomes an important issue now. In order to prevent the information from being stolen or modified by unauthorized ones, we need some high security device to protect our information on networking systems. In this paper, we focus on the architecture design of a 1024-bit RSA encryption/decryption algorithm. The resulting IP has been verified by both FPGA and standard cell library. It can operate at 72 MHz, the area is 3.1 x 3.1 mm2, and bit rate is 35 kbps when it is realized by COMPASS 0.35 μm standard cells. The resulting chip can operate at 33 MHz, the area is 16,321 LCELLs, and bit rate is 17 kbps when it is realized by Altera FPGA device (EP20K600EBC652-1).