Teses / dissertações sobre o tema "Circuits intégrés – Mesures de sécurité"
Crie uma referência precisa em APA, MLA, Chicago, Harvard, e outros estilos
Veja os 50 melhores trabalhos (teses / dissertações) para estudos sobre o assunto "Circuits intégrés – Mesures de sécurité".
Ao lado de cada fonte na lista de referências, há um botão "Adicionar à bibliografia". Clique e geraremos automaticamente a citação bibliográfica do trabalho escolhido no estilo de citação de que você precisa: APA, MLA, Harvard, Chicago, Vancouver, etc.
Você também pode baixar o texto completo da publicação científica em formato .pdf e ler o resumo do trabalho online se estiver presente nos metadados.
Veja as teses / dissertações das mais diversas áreas científicas e compile uma bibliografia correta.
Cioranesco, Jean-Michel. "Nouvelles Contre-Mesures pour la Protection de Circuits Intégrés". Thesis, Paris 1, 2014. http://www.theses.fr/2014PA010022/document.
Texto completo da fonteEmbedded security applications are diverse and at the center of all personal embedded applications. They introduced an obvious need for data confidentiality and security in general. Invasive attacks on hardware have always been part of the industrial scene. The aim of this thesis is to propose new solutions in order to protect embedded circuits against some physical attacks described above. ln a first part of the manuscript, we detail the techniques used to achieve side-channel, invasive attacks and reverse engineering. I could implement several of these attacks during my thesis research, they will be detailed extensively. ln the second part we propose different hardware countermeasures against side-channel attacks. The third part is dedicated to protection strategies against invasive attacks using active shielding and we conclude this work by proposing an innovative cryptographic shield which is faulty and dpa resistant
Germain, Fabien. "Sécurité cryptographique par la conception spécifique de circuits intégrés". Phd thesis, Ecole Polytechnique X, 2006. http://pastel.archives-ouvertes.fr/pastel-00001858.
Texto completo da fonteDumont, Mathieu. "Modélisation de l’injection de faute électromagnétique sur circuits intégrés sécurisés et contre-mesures". Thesis, Montpellier, 2020. http://www.theses.fr/2020MONTS031.
Texto completo da fonteThis thesis is devoted to the study of electromagnetic fault injection attack on se-cure integrated circuits. Electrical modeling permits to simulate the coupling between an EM probe injection and the circuit supply and ground grids in order to understand the effect of the EM pulse. This modeling is then applied on a logic circuit simulation with a D flip-flop and its components. The simulation results were used to determine the various faults that could be induced by this attack and to explain their formation. Measurements on a test circuit revealed the appearance of timing and sampling faults and validated ex-perimentally the proposed model. Finally, some countermeasures based on the model are proposed in order to increase the robustness of a circuit against electromagnetic fault in-jection
Hély, David. "Conception en vue du test de circuits sécurisés". Montpellier 2, 2005. http://www.theses.fr/2005MON20123.
Texto completo da fonteDehbaoui, Amine. "Analyse Sécuritaire des Émanations Électromagnétiques des Circuits Intégrés". Thesis, Montpellier 2, 2011. http://www.theses.fr/2011MON20020.
Texto completo da fonteThe integration of cryptographic primitives in different electronic devices is widely used today incommunications, financial services, government services or PayTV.Foremost among these devices include the smart card. According to a report published in August 2010, IMS Research forecasts that the smart card market will reach 5.8 billion units sold in this year. The vast majority is used in telecommunications (SIM) and banking.The smart card incorporates an integrated circuit which can be a dedicated processor for cryptographic calculations. Therefore, these integrated circuits contain secrets such as secret or private keys used by the symmetric or asymmetric cryptographic algorithms. These keys must remain absolutely confidential to ensure the safety chain.Therefore the robustness of smart cards against attacks is crucial. These attacks can be classifiedinto three main categories: invasive, semi-invasive and non-invasive.Non-invasive attacks can be considered the most dangerous, since this kind of attack can be achieved without any contact with the circuit.Indeed, while using electronic circuits that compose them are subjected to variations in current and voltage. These variations generate an electromagnetic radiation propagating in the vicinity of the circuit.These radiations are correlated with secret information (eg a secret key used for authentication). Several attacks based on these leakages were published by the scientific community.This thesis aims to: (a) understand the different sources of electromagnetic emanations of integrated circuits, and propose a localized near field attack to test the robustness of a cryptographic circuit and (b) propose counter-measures to these attacks
Joaquim, da Rolt Jean. "Testabilité versus Sécurité : Nouvelles attaques par chaîne de scan & contremesures". Thesis, Montpellier 2, 2012. http://www.theses.fr/2012MON20168.
Texto completo da fonteIn this thesis, we firstly analyze the vulnerabilities induced by test infrastructures onto embedded secrecy in digital integrated circuits dedicated to cryptography. Then we propose new scan-based attacks and effective countermeasures. Scan chains insertion is the most used technique to ensure the testability of digital cores, providing high-fault coverage. However, for ICs dealing with secret information, scan chains can be used as back doors for accessing secret data, thus becominga threat to device's security. We start by describing a series of new attacks that exploit information leakage out of advanced Design-for-Testability structures such as response compaction, X-Masking and partial scan. Conversely to some previous works that proposed that these structures are immune to scan-based attacks, we show that our new attacks can reveal secret information that is embedded inside the chip boundaries. Regarding the countermeasures, we propose three new solutions. The first one moves the comparison between test responses and expected responses from the AutomaticTest Equipment to the chip. This solution has a negligible area overhead, no effect on fault coverage. The second countermeasure aims to protect the circuit against unauthorized access, for instance to the test mode, and also ensure the authentication of the circuit. For thatpurpose, mutual-authentication using Schnorr protocol on Elliptic Curves is implemented. As the last countermeasure, we propose that Differential Analysis Attacks algorithm-level countermeasures, suchas point-blinding and scalar-blinding can be reused to protect the circuit against scan-based attacks
Vaquié, Bruno. "Contributions à la sécurité des circuits intégrés face aux attaques par canaux auxiliaires". Thesis, Montpellier 2, 2012. http://www.theses.fr/2012MON20133/document.
Texto completo da fonteSide channel attacks such as power analysis attacks are a threat to the security of integrated circuits.They exploit the physical leakage of circuits during the cryptographic computations to retrieve the secret informations they contain. Many countermeasures, including hardware, have been proposed by the community in order to protect cryptosystems against such attacks. Despite their effectiveness, their major drawback is their significant additional cost in area, speed and consumption. This thesis aims at proposing low cost countermeasures able to reduce the leaks and offering a good compromise between security and costs. First we identify the main sources of leakage of a cryptographic system that integrates an iterative hardware architecture of a symetric algorithm. Then we propose several low cost countermeasures, which aim at reducing this leakage. Finally, we evaluate the robustness of our solutions against side channel attacks
Razafindraibe, Hanitriniaina Mamitiana Alin. "Analyse et amélioration de la logique double rail pour la conception de circuits sécurisés". Montpellier 2, 2006. http://www.theses.fr/2006MON20117.
Texto completo da fonteClavier, Christophe. "De la sécurité physique des crypto-systèmes embarqués". Versailles-St Quentin en Yvelines, 2007. http://www.theses.fr/2007VERS0028.
Texto completo da fonteIn a world full of threats, the development of widespread digital applications has led to the need for a practical device containing cryptographic functions that provide the everyday needs for secure transactions, confidentiality of communications, identification of the subject or authentication for access to a particular service. Among the cryptographic embedded devices ensuring these functionalities, smart cards are certainly the most widely used. Their portability (a wallet may easily contain a dozen) and their ability to protect its data and programs against intruders, make it as the ideal ``bunker'' for key storage and the execution of cryptographic functions during mobile usage requiring a high level of security. Whilst the design of mathematically robust (or even proven secure in some models) cryptographic schemes is an obvious requirement, it is apparently insufficient in the light of the first physical attacks that were published in 1996. Taking advantage of weaknesses related to the basic implementation of security routines, these threats include side-channel analysis which obtains information about the internal state of the process, and the exploitation of induced faults allowing certain cryptanalysis to be performed which otherwise would not have been possible. This thesis presents a series of research works covering the physical security of embedded cryptosystems. Two parts of this document are dedicated to the description of some attacks and to a study of the efficiency of conceivable countermeasures. A third part deals with that particular and still mainly unexplored area which considers the applicability of physical attacks when the cryptographic function is, partly or totally, unknown by the adversary
Acunha, guimarães Leonel. "Techniques de Test Pour la Détection de Chevaux de Troie Matériels en Circuits Intégrés de Systèmes Sécurisés". Thesis, Université Grenoble Alpes (ComUE), 2017. http://www.theses.fr/2017GREAT080/document.
Texto completo da fonteThe world globalization has led the semiconductor industry to outsource design and fabrication phases, making integrated circuits (ICs) potentially more vulnerable to malicious modifications at design or fabrication time: the hardware Trojans (HTs). New efficient testing techniques are thus required to disclose potential slight and stealth HTs, and to ensure trusted devices. This thesis studies possible threats and proposes two new post-silicon testing techniques able to detect HTs implanted after the generation of the IC netlist. The first proposed technique exploits bulk built-in current sensors (BBICS) -- which are originally designed to identify transient faults in ICs -- by using them as testing mechanisms that provide statistically-comparable digital signatures of the devices under test. With only 16 IC samples, the testing technique can detect dopant-level Trojans of zero-area overhead. The second proposition is a non-intrusive technique for detection of gate-level HTs in asynchronous circuits. With this technique, neither additional hardware nor alterations on the original test set-up are required to detect Trojans smaller than 1% of the original circuit. The studies and techniques devised in this thesis contribute to reduce the IC vulnerability to HT, reusing testing mechanisms and keeping security features of original devices
Leonhard, Julian. "Analog hardware security and trust". Electronic Thesis or Diss., Sorbonne université, 2021. http://www.theses.fr/2021SORUS246.
Texto completo da fonteThe ongoing globalization and specialization of the integrated circuit (IC) supply chain has led semiconductor companies to share their valuable intellectual property (IP) assets with numerous parties for means of manufacturing, testing, etc. As a consequence, sensitive IPs and ICs are being exposed to untrusted parties, resulting in serious piracy threats such as counterfeiting or reverse engineering. In this thesis we develop methods to secure analog and mixed signal IPs/ICs from piracy threats within the supply chain. We propose an anti-piracy methodology for locking mixed-signal ICs via logic locking of their digital part. Furthermore, we propose an anti-reverse engineering methodology camouflaging the effective geometry of layout components. Finally, we propose an attack to break all analog circuit locking techniques that act upon the biasing of the circuit. The presented techniques have the potential to protect analog and mixed-signal circuits against a large subset of all the possible risk scenarios while inflicting low overheads in terms of area, power and performance
Pamula, Danuta. "Opérateurs arithmétiques sur GF (2m) : étude de compromis performances-consommation-sécurité". Rennes 1, 2012. http://www.theses.fr/2012REN1E011.
Texto completo da fonteThe efficiency of devices performing arithmetic operations in finite field is crucial for the efficiency of ECC systems. Regarding the dependency of the system on those devices we conclude that the robustness of the system also depends on the robustness of the operators. The aim of conducted researches described in the dissertation was to propose efficient and robust against power analysis side-channel attacks hardware arithmetic operators on GF(2m) dedicated to elliptic curve cryptography (ECC) applications. We propose speed and area efficient hardware solutions for arithmetic operators on GF(2m). Designed units are flexible and operate, due to assumed applications, on large numbers (160-600 bits). Next we propose algorithmic and architectural modifications improving robustness against side-channel power analysis attacks of designed solutions. The final goal described was to find a tradeoff between security of arithmetic operators and their efficiency. We were able to perform such modifications increasing robustness of designed hardware arithmetic operators, which do not impact negatively overall performance of the operator. The attempt to protect the lowest level operations of ECC systems, the finite field operations, is a first known attempt of that type. Till now researches described in literature on the subject did not concern the finite field level operations protections. They considered only protections of curve or ECC protocol level operations. Proposed protections contribute and we may say complete already developed means of protections for ECC systems. By combining protections of all levels of operation of the ECC system it is assumed that it is possible to make the system very robust against side-channel power analysis attacks
Ba, Papa-Sidy. "Détection et prévention de Cheval de Troie Matériel (CTM) par des méthodes Orientées Test Logique". Thesis, Montpellier, 2016. http://www.theses.fr/2016MONTT271/document.
Texto completo da fonteIn order to reduce the production costs of integrated circuits (ICs), outsourcing the fabrication process has become a major trend in the Integrated Circuits (ICs) industry. As an inevitable unwanted side effect, this outsourcing business model increases threats to hardware products. This process raises the issue of un-trusted foundries in which, circuit descriptions can be manipulated with the aim to possibly insert malicious circuitry or alterations, referred to as Hardware Trojan Horses (HTHs). This motivates semiconductor industries and researchers to study and investigate solutions for detecting during testing and prevent during fabrication, HTH insertion.However, considering the stealthy nature of HTs, it is quite impossible to detect them with conventional testing or even with random patterns. This motivates us to make some contributions in this thesis by proposing solutions to detect and prevent HTH after fabrication (during testing).The proposed methods help to detect HTH as well during testing as during normal mode(run-time), and they are logic testing based.Furthermore, we propose prevention methods, which are also logic testing based, in order tomake harder or quasi impossible the insertion of HTH both in netlist and layout levels
Díaz, Rizo Alán Rodrigo. "Security and Trust for Wireless Integrated Circuits". Electronic Thesis or Diss., Sorbonne université, 2023. http://www.theses.fr/2023SORUS005.
Texto completo da fonteThe origin of the hardware security threats is the massively globalized and outsourcing-based Integrated Circuit (IC) supply chain that we see today. The prohibitively cost of owning a first-rate semiconductor foundry forces IC design houses to go fabless and outsource their IC fabrication, assembly, and testing. Outsourcing these tasks intensifies the risk of IC piracy attacks and Hardware Trojan (HT) insertion, and both threats translate into know-how and financial losses for the IC owner. Moreover, complex Systems-on-Chip (SoCs) are built by integrating third-party Intellectual Property (IP) cores from multiple IP providers. However, SoC integrators and IP providers have an imbalanced trust relationship. While IP providers are vulnerable to IP overuse, IP cloning, and IC overproduction, SoC integrators fear integrating HT-infected IPs into their systems. We propose a locking-based design-for-security methodology. In addition, we develop an RF transceiver-specific locking methodology that consists in two spatially separated mechanisms. inserting a locking mechanism into the circuit that unlocks with a single secret key in the form of a digital word. To assess the security of wireless ICs, we propose an HT attack that leaks sensitive information from the transmitter within a legitimate transmission
Elshamy, Mohamed. "Design for security in mixed analog-digital integrated circuits". Electronic Thesis or Diss., Sorbonne université, 2021. http://www.theses.fr/2021SORUS093.
Texto completo da fonteRecently, the enormous cost of owning and maintaining a modern semiconductor manufacturing plant has coerced many companies to go fabless. By outsourcing the manufacturing IC/IP to third-party and often off-shore companies, the process has been extended to potentially untrustworthy companies. This has resulted in several security threats to the semiconductor industry such as counterfeiting, reverse engineering, and HTs insertion. In this thesis, we propose an anti-piracy countermeasure to protect AMS ICs/IPs, a novel HT attack for AMS ICs/IPs, and a novel PUF. More specifically, we propose an anti-piracy technique based on locking for programmable analog circuits. The proposed technique leverages the programmability fabric to implement a natural lock-less locking. We discuss its implementation and its resilience capabilities against foreseen attacks. The proposed HT attack for analog circuits leverages the test infrastructure. The HT is hidden effectively in a digital core and transfers its payload to the analog circuit via the test bus and the interface of the analog circuit to the test bus. Its key characteristic is that it is invisible in the analog domain. The proposed HT is demonstrated on two case studies. This thesis sheds light on the importance of developing new security and trust countermeasures tailored for analog circuits. The proposed PUF, called "neuron-PUF", uses a single spiking neuron as the source of entropy. Its key characteristic is that it uses a single PUF cell and temporal redundancy to generate an arbitrarily long key, which results in significant low area and power overheads compared to mainstream PUFs, such as delay-based and memory-based PUFs
Montoya, Maxime. "Sécurité adaptative et énergétiquement efficace dans l’Internet des Objets". Thesis, Lyon, 2019. http://www.theses.fr/2019LYSEM032.
Texto completo da fonteThe goal of this work is to propose new methods that provide both a high security and a high energy efficiency for integrated circuits for the IoT.On the one side, we study the security of a mechanism dedicated to energy management. Wake-up radios trigger the wake-up of integrated circuits upon receipt of specific wake-up tokens, but they are vulnerable to denial-of-sleep attacks, during which an attacker replays such a token indefinitely to wake-up a circuit and deplete its battery. We propose a new method to generate unpredictable wake-up tokens at each wake-up, which efficiently prevents these attacks at the cost of a negligible energy overhead.On the other side, we improve on the energy efficiency of hardware countermeasures against fault and side-channel attacks, with two different approaches. First, we present a new combined countermeasure, which increases by four times the power consumption compared to an unprotected implementation, introduces no performance overhead, and requires less than 8 bits of randomness. Therefore, it has a lower energy overhead than existing combined protections. It consists in an algorithm-level power balancing that inherently detects faults. Then, we propose an adaptive implementation of hardware countermeasures, which consists in applying or removing these countermeasures on demand, during the execution of the protected algorithm, in order to tune the security level and the energy consumption. A security evaluation of all the proposed countermeasures indicates that they provide an efficient protection against existing hardware attacks
Lecomte, Maxime. "Système embarque de mesure de la tension pour la détection de contrefaçons et de chevaux de Troie matériels". Thesis, Lyon, 2016. http://www.theses.fr/2016LYSEM018/document.
Texto completo da fonteDue to the trend to outsourcing semiconductor manufacturing, the integrity of integrated circuits (ICs) became a hot topic. The two mains threats are hardware Trojan (HT) and counterfeits. The main limit of the integrity verification techniques proposed so far is that the bias, induced by the process variations, restricts their efficiency and practicality. In this thesis we aim to detect HTs and counterfeits in a fully embedded way. To that end we first characterize the impact of malicious insertions on a network of sensors. The measurements are done using a network of Ring oscillators. The malicious adding of logic gates (Hardware Trojan) or the modification of the implementation of a different design (counterfeits) will modify the voltage distribution within the IC.Based on these results we present an on-chip detection method for verifying the integrity of ICs. We propose a novel approach which in practice eliminates this limit of process variation bias by making the assumption that IC infection is done at a lot level. We introduce a new variation model for the performance of CMOS structures. This model is used to create signatures of lots which are independent of the process variations. A new distinguisher has been proposed to evaluate whether an IC is infected. This distinguisher allows automatically setting a decision making threshold that is adapted to the measurement quality and the process variation. The goal of this distinguisher is to reach a 100\% success rate within the set of covered HTs family. All the results have been experientially validated and characterized on a set of FPGA prototyping boards
Nejat, Arash. "Tirer parti du masquage logique pour faciliter les méthodes de détection des chevaux de Troie hardware". Thesis, Université Grenoble Alpes (ComUE), 2019. http://www.theses.fr/2019GREAT004.
Texto completo da fonteThe ever-increasing complexity of integrated circuits (ICs) design and manufacturing has necessitated the employment of third parties such as design-houses, intellectual property (IP) providers and fabrication foundries to accelerate and economize the development process. The separation of these parties results in some security threats. Untrustworthy fabrication foundries are suspected of three security threats: hardware Trojans, IP piracy, and IC overproduction. Hardware Trojans are malicious circuitry alterations in IC layouts intended for sabotage objectives.Some IC design modifications, known as Design-for-Trust (DfTr) have been proposed to facilitate Trojan detection methods or prevent Trojan insertion. In addition, key-based modifications, known as design masking or obfuscation, have been proposed to protect IPs/ICs from IP piracy and IC overproduction. They obscure circuits’ functionality by modifying circuits such that they do not correctly work without being fed with a correct key.In this thesis, we propose three DfTr methods based on leveraging the masking approach to hinder Trojan insertion. The first proposed DfTr method aims to maximize obscurity and simultaneously minimize the rare signal counts in circuits under masking. Rare signals barely have transitions during circuit operations and so the use of them causes hardware Trojans will not be easily activated and detected during circuit tests. The second proposed DfTr facilitates path delay analysis-based Trojan detection methods. Since the delay of shorter paths varies less than longer ones’, the objective is to generate fake short paths for nets which only belong to long paths by repurposing the masking elements. Our experiments show that this DfTr method increases the Trojan detectability in modified circuits and also provides the advantages of masking methods. The aim of the third DfTr method is to facilitate power-analysis-based Trojan detection. In a masked circuit by the proposed method, one has more control over the switching activity of the different circuit parts. For instance, one can target one part of the circuit, increase its switching activity, and simultaneously decrease the other parts’ switching activity; consequently, if the target part includes an hardware Trojan, its switching activity and so power consumption rises, although the total power consumption of the circuit goes down due to low switching activity rates in most parts of the circuit. When the circuit consumes less power, the power measurement noise abates. The noise can disturb to observe Trojans’ effects on the power consumption of Trojan-infected circuits.In addition, in this thesis, we introduce a CAD tool that can run various masking algorithms on gate-level netlists. The tool can also perform logic simulation and estimate circuit area, power consumption, and performance at the gate level
Marconot, Johan. "Fonction Physique Non-clonable pour la Sécurité du Cycle de Vie d'un Objet Cyber-physique". Thesis, Université Grenoble Alpes, 2020. http://www.theses.fr/2020GRALT011.
Texto completo da fonteThe thesis focus on the conception of solutions to secure, all along its lifecycle, the assets and the functions which are embedded into a connected object. The lifecycle induces multiple interactions which expose the assets. Still, each actor may need private access in order to perform technical operations which have to be done. The solution has to securely manage the access requests but also takes account of the fact that most of the connected object are resources constraints system.We provide two main contributions: the analysis of security requirements for the device lifecycle and a new model of extraction circuit for strong digital PUF. The identified configuration for the extraction circuit offer trade-off between the circuit area, the frequency and the security metrics. It allows to conceive an efficient DPUF which could be integrated at fabrication chip, ensuring authentication property and performance requirements for lifecycle
Di, Battista Jérôme. "Étude des techniques d'analyse de défaillance et de leur utilisation dans le cadre de l’évaluation de la sécurité des composants de traitement de l’information". Thesis, Montpellier 2, 2011. http://www.theses.fr/2011MON20011/document.
Texto completo da fonteThe purpose of failure analysis is to locate the source of a defect in order to characterize it, using different techniques (laser stimulation, light emission, electromagnetic emission...). Moreover, the aim of vulnerability analysis, and particularly side-channel analysis, is to observe and collect various leakages information of an integrated circuit (power consumption, electromagnetic emission ...) in order to extract sensitive data. Although these two activities appear to be distincted, they have in common the observation and extraction of information about a circuit behavior. The purpose of this thesis is to explain how and why these activities should be combined. Firstly it is shown that the leakage due to the light emitted during normal operation of a CMOS circuit can be used to set up an attack based on the DPA/DEMA technique. Then a second method based on laser stimulation is presented, improving the “traditional” attacks by injecting a photocurrent, which results in a punctual increase of the power consumption of a circuit. These techniques are demonstrated on an FPGA device
Beringuier-Boher, Noémie. "Evaluation et amélioration de la sécurité des circuits intégrés analogiques". Thesis, Université Grenoble Alpes (ComUE), 2015. http://www.theses.fr/2015GREAT007.
Texto completo da fonteWith the development of the Internet of things, the number of connected devices is in constant increase. These objects use a large amount of data including personal credentials. Therefore, security has become a major constraint for System on Chips (SoCs) designers. Moreover, in a context more and more aggressive in terms of performances and time to market, it is important to find low cost security solutions. Although the hardware security is often treated from a digital point of view, almost every SoCs is also using analog and mixed IP. Thus, this work presents different steps to improve the security of analog IPs, from vulnerability analysis to countermeasures design validation, and behavioral modeling in the context of mixed signals and low cost applications. To protect any system, the first requirement is to know its vulnerabilities. To do so, a vulnerability analysis methodology dedicated to analog circuit has been developed. Using the results of this analysis, countermeasures can be designed during the development of the circuit and not at the end. The circuit security is thus improved without dramatically increasing its cost in terms of design time. The analysis of a clock system generator, an analog IP widely used in current SoCs and composed with various sub-circuits, has shown fault attacks using Laser Photoelectric Stimulation (LPS) or supply voltage glitches as important threats. After having identified the 2 previous attacks types as major threats, their effects on analog circuits are analyzed. Existing countermeasures are then compared and evaluated for the protection of analog IPs. To complete these solutions, two analog detectors have been designed to detect laser and supply voltage glitch attacks considering SoCs level constraints. Electrical test of these detectors processed on CMOS 28nm FD-SOI technology proved their efficiency. Theoretical vulnerability analysis has shown some difficulties. Indeed, analog circuits are sensitive to numerous parametrical faults. Also, the high interconnection of various sub-circuits makes the faults propagation analysis quite difficult. To help this analysis, electrical simulations at transistor level are necessary. These simulations are quite long and, so the behavioral modeling of analog circuits to help the analysis of supply voltage glitch attack effects has been studied. To do so, the developed models must be developed according different constraints presented in this report and applied to the behavioral modeling of a real analog circuit. This illustration proved that behavioral models can be used to help to identify which attack shapes are the most likely to induce faults in the circuit
Baranowski, Sylvie. "Utilisation d'un microcontrôleur dans une application de sécurité : test et évaluation du taux de couverture de pannes et de la sécurité". Lille 1, 1988. http://www.theses.fr/1988LIL10095.
Texto completo da fonteOrdas, Thomas. "Analyse des émissions électromagnétiques des circuits intégrés". Thesis, Montpellier 2, 2010. http://www.theses.fr/2010MON20001.
Texto completo da fonteIn the area of secure integrated circuits, such as smart cards, circuit designers are always looking to innovate to find new countermeasures against attacks by the various side channels that exist today. Indeed, side channels attacks such as the analysis of electromagnetic emissions permit to extract secret information contained in circuits. Based on this observation, in this thesis, we focused on the study of electromagnetic analysis to observe the analysis possibilities. This manuscript is organized as follows. Initially, we presented a measurement system for electromagnetic emissions in time domain, and the results obtained on different circuits. From these results, a summary of opportunities, relating to the security threat, posed by electromagnetic analysis, is proposed as well as solutions proposals to reduce electromagnetic radiations of integrated circuits. In a second step, we are interested in the simulation of electromagnetic emissions. A state of the art of simulation tools which exist today, has allowed us to demonstrate that none of them allowed to have a fine enough resolution in terms of electromagnetic emissions. To fill this gap, a simulation tool has been developed and to validate this flow, a comparison between measurement results and simulation results was performed
Harrari, Mounia. "Hybridation CMOS/STT-MRAM des circuits intégrés pour la sécurité matérielle de l'Internet des Objets". Electronic Thesis or Diss., Aix-Marseille, 2019. http://www.theses.fr/2019AIXM0621.
Texto completo da fonteIn the last decade, the Internet of Things deployment highlighted new needs and constraints in terms of consumption and area for integrated circuits. However, the recent craze for connected objects and due to the extremely pressing time-to-market demand, the manufacturers commercialize their products, sometimes at the expense of their security. The main focus of the work undertook during this thesis consists in the hybridization of the CMOS technology with the emerging non-volatile memory technology STT-MRAM. This study aims to determine the assets and drawbacks of this hybridization. These innovating architectures must allow the development of low power applications and support the growth of secured connected objects. Thus, the design of a hybrid CMOS/STT-MRAM lightweight cryptographic algorithm based on the PRESENT cipher is realised.This is how the first study carried out consisted in investigating the robustness of STT-MRAM junctions facing physical attacks, before their integration in the cryptographic algorithm. To do this, laser fault injections were performed in order to evaluate the integrity of the sensitive data stored in the cells.Following the observations carried out on these experiments on perpendicular STT-MRAM memories, a new physical attack detector based on this memory technology is proposed, designated by DDHP. This sensor allows simultaneous detection of photoelectrical and thermal attacks that can target integrated circuits
Gautray, Jacques Marie. "Etude des résonateurs hybrides en bandes X et applications à la mesure des permittivités". Bordeaux 1, 1985. http://www.theses.fr/1985BOR10515.
Texto completo da fonteDe, Castro Stephan. "Modélisation et simulation d'attaque laser sur des circuits sécuritaires". Thesis, Montpellier, 2016. http://www.theses.fr/2016MONTT317/document.
Texto completo da fonteNowadays, more and more microelectronic circuits are used for critical purposes, such as payment or identification. Then those circuit sparked interest form attackers. Among the different ways to retrieve the cipher key, laser illumination is a very efficient one. Thereby, the protection of the circuit against these attacks becomes an important point for designers. However, to determine the resistance of a circuit against laser injection, laser illumination has to be performed. If the circuit do not match the security requirement, it has to be changed, which represent a large cost in terms of design time and fabrication cost. In order to predict the effect of a laser injection, electrical model and simulator have been developed.First, a description of the physical phenomenon (photoelectric effect), which leads to the fault injection in the circuit, is given. Then a description of the first electrical model developed using current sources to model the illumination effect.Then, a practical attack is performed on a crypto processor implanting the AES algorithm. This experimentation allows us to compare the two ways of laser injections, injection from the front side or the back side of the circuit. It comes out that the best way of injection depends on the circuit aimed and the laser bench at disposal of the attacker. Indeed, on the studied circuit, better exploitable fault can be injected, from the front side injection with a large laser spot than from the back side with the same laser spot size. This result can be explained by the effect of the metal lines above the circuit, which reduce the area of illuminated silicon.We discuss then about the validity of the electrical model for more recent technology nodes. Thus a new electrical model is developed for more recent CMOS bulk and Fully Depleted Silicon On Insulator (FDSOI) technologies. From its transistor structure, the CMOS FDSOI technology seems to be more resistant to laser injection than the CMOS bulk technology. This observation is confirmed by experimentation.Finally, we perform laser injection on a memory element (here a flip-flop chain). These experimentations show that even if the CMOS FDSOI technology seems to be more resistant, fault can be injected. With a one micro meter laser spot, the attacker can inject the wanted fault type in the flip-flop (bit set or bit reset) on 28nm CMOS bulk and FDSOI technologies. Even if, the fault injection is still possible, from the attacker point of view, fault injection is more difficult in a circuit using the CMOS 28nm FDSOI technology than the CMOS 28nm bulk one. Indeed, the gap between the fault injection threshold and the breaking threshold is narrower for the FDSOI than the bulk. Moreover, a breaking phenomenon has been observed in the FDSOI technology when multiple laser shot are performed in the same place.To conclude, the previous work allows updating and developed a new electrical model for the recent CMOS bulk and FDSOI technology under illumination, to compare those technologies against laser illumination. It comes out, that even if fault injection is possible for both technologies, the practical attack is more difficult to achieve on a CMOS FDSOI circuit
Salhi, Mohamed Amine. "Imagerie thermique et thermoélastique de circuits intégrés : application à l'analyse de défaillances". Bordeaux 1, 2006. http://www.theses.fr/2006BOR13295.
Texto completo da fonteGomina, Kamil. "Méthodologie et développement de solutions pour la sécurisation des circuits numériques face aux attaques en tensions". Thesis, Saint-Etienne, EMSE, 2014. http://www.theses.fr/2014EMSE0751.
Texto completo da fonteGeneral use products as mobile phones or smartcards manipulate confidential data. As such, the circuits composing them are more and more prone to physical attacks, which involve a threat for their security. As a result, SoC designers have to develop efficient countermeasures without increasing overall cost and complexity of the final application. The analysis of existing attacks on digital circuits leads to consider power attacks, in advanced technology nodes.First of all, the power signature of a circuit was determined at design time. To do so, an electrical model was suggested based on the current consumption and the overall power grid capacitance. The methodology to extract these parameters, as well as the evaluation of the model are presented. This model allows designers to anticipate information leakage at design time and to quantify the protection of countermeasures, as the use of integrated decoupling capacitors. Then, the study was dedicated to power glitch attacks. The different fault injection mechanisms were analyzed in details. From then on, a set of detection circuits were suggested and evaluated at design time and on silicon by electrical tests. Both the theoretical analysis and the given methodology were confirmed by the test campaigns.This work demonstrated that the design of low-cost solutions against passive and active power attacks can be achieved, and used in a large scale product development
Faurax, Olivier. "Méthodologie d'évaluation par simulation de la sécurité des circuits face aux attaques par faute". Aix-Marseille 2, 2008. http://theses.univ-amu.fr.lama.univ-amu.fr/2008AIX22106.pdf.
Texto completo da fonteMicroelectronic security devices are more and more present in our lives (smartcards, SIM cards) and they contains sensitive informations that must be protected (account number, cryptographic key, personal data). Recently, attacks on cryptographic algorithms appeared, based on the use of faults. Adding a fault during a device computation enables one to obtain a faulty result. Using a certain amount of correct results and the corresponding faulty ones, it is possible to extract secret data and, in some cases, complete cryptographic keys. However, physical perturbations used in practice (laser, radiations, power glitch) rarely match with faults needed to successfully perform theoretical attacks. In this work, we propose a methodology to test circuits under fault attacks, using simulation. The use of simulation enables to test the circuit before its physical realization, but needs a lot of time. That is why our methodology helps the user to choose the most important faults in order to significantly reduce the simulation time. The tool and the corresponding methodology have been tested on a cryptographic circuit (AES) using a delay fault model. We showed that use of delays to make faults can generate faults suitable for performing known attacks
Levant, Jean-Luc. "Mise en place d'une démarche d'intégration des contraintes CEM dans le flot de conception des circuits intégrés". Rennes, INSA, 2007. http://www.theses.fr/2007ISAR0018.
Texto completo da fonteExurville, Ingrid. "Détection non destructive de modification malveillante de circuits intégrés". Thesis, Saint-Etienne, EMSE, 2015. http://www.theses.fr/2015EMSE0800/document.
Texto completo da fonteThe globalization of integrated circuits fabrication involves several questions about the integrity of the fabricated circuits. Malicious modifications called Hardware Trojans (HT) can be introduced during the circuit production process. Due to the complexity of an integrated circuit, it is really difficult to find this kind of alterations.This work focuses on a non-destructive method of HT detection. We use the paths delays of the studied design as a channel to detect HT. A model to describe paths delays is defined. It takes into account two important parameters which are the experimental conditions and the process variations.Faults attacks by clock glitches based on timing constraints violations have been performed to measure data paths delays. Reliable circuits are used for reference. After validating the relevance of this channel to get information on the internal behavior of the targeted design, experimental detections of HT inserted on two different abstraction levels (RTL and after place and route) were achieved. Process variations are taken into consideration in the studies to detect if the tested circuits are infected
Bousselam, Kaouthar. "Résistance des circuits cryptographiques aux attaques en faute". Phd thesis, Université Montpellier II - Sciences et Techniques du Languedoc, 2012. http://tel.archives-ouvertes.fr/tel-00771357.
Texto completo da fonteHaddad, Patrick. "Caractérisation et modélisation de générateurs de nombres aléatoires dans les circuits intégrés logiques". Thesis, Saint-Etienne, 2015. http://www.theses.fr/2015STET4008/document.
Texto completo da fonteRandom number generators (RNG) are primitives that produce independent and uniformly distributed digital values, RNG are used in secure environments where the use of random numbers is required (generation of cryptographic keys, nonces in cryptographic protocols, padding values, countermeasures against side-channel attacks) and where the quality of the randomness is essential. All electronic components with a security function, such as smart cards, include one or more random generators (based on physical principles). Consequently, the RNG is an essential primitive for security applications. A flaw in security of the random number generation process directly impacts the security of the cryptographic system. This thesis focuses on the study of physical RNG (PTRNG), the modeling of its randomness and an electronic characterizations of the circuit. This study is in the context of the AIS-31 standard which is published by the BSI* and followed by many European countries. This standard is one of the few that require a characterizations of the PTRNG and a stochastic model. In this context, it is crucial to validate the evaluation methodology proposed by these standards and l focused on them during my thesis.*Bundesamt fiir Sicherheit in der Informationstechnik, federal agency German responsible for the security of information technology
Marchand, Cédric. "Conception de matériel salutaire pour lutter contre la contrefaçon et le vol de circuits intégrés". Thesis, Lyon, 2016. http://www.theses.fr/2016LYSES058/document.
Texto completo da fonteCounterfeiting and theft affects all industrial activities in our society. Electronic products are the second category of products most concerned by these issues. Among the most affected electronic products, we find mobile phones, tablets, computers as well as more basic elements such as analog and digital circuits or integrated circuits. These are the heart of almost all electronic products and we can say that a mobile phone is counterfeited if it has at least one counterfeit integrated circuit inside. The market of counterfeit integrated circuit is estimated between 7 and 10% of the global semi-conductors market, which represents a loss of at least 24 billion euros for the lawful industry in 2015. These losses could reach 36 billion euros in 2016. Therefore, there is an absolute necessity to find practical and efficient methods to fight against counterfeiting and theft of integrated circuits. The SALWARE project, granted by the French "Agence Nationale de la Recherche" and by the "Fondation de Recherche pour l’Aéronautique et l’Espace", aims to fight against the problem of counterfeiting and theft of integrated circuitsFor that, we propose to design salutary hardwares (salwares). More specifically,we propose to cleverly combine different protection mechanisms to build a completeactivation system. Activate an integrated circuit after its manufacturing helpsto restore the control of integrated circuits to the true owner of the intellectualproperty.In this thesis, we propose the study of three different protection mechanismsfighting against counterfeiting and theft of integrated circuits. First, the insertionand the detection of watermark in the finite state machine of digital and synchronoussystems will be studied. This mechanism helps to detect counterfeit or theftparts. Then, a physical unclonable function based on transcient effect ring oscillatoris implemented and characterized on FPGA. This protection mechanism is used toidentify integrated circuit with a unique identifier created thanks to the extractionof entropy from manufacturing process variations. Finally, we discuss the hardwareimplementations of lightweight block ciphers, which establish a secure communicationduring the activation of an integrated circuit
Badier, Hannah. "Transient obfuscation for HLS security : application to cloud security, birthmarking and hardware Trojan defense". Thesis, Brest, École nationale supérieure de techniques avancées Bretagne, 2021. https://tel.archives-ouvertes.fr/tel-03789700.
Texto completo da fonteThe growing globalization of the semiconductor supply chain, as well as the increasing complexity and diversity of hardware design flows, have lead to a surge in security threats: risks of intellectual property theft and reselling, reverse-engineering and malicious code insertion in the form of hardware Trojans during manufacturing and at design time have been a growing research focus in the past years. However, threats during highlevel synthesis (HLS), where an algorithmic description is transformed into a lower level hardware implementation, have only recently been considered, and few solutions have been given so far. In this thesis, we focus on how to secure designs during behavioral synthesis using either a cloud-based or an internal but untrusted HLS tool. We introduce a novel design time protection method called transient obfuscation, where the high-level source code is obfuscated using key-based techniques, and deobfuscated after HLS at register-transfer level. This two-step method ensures correct design functionality and low design overhead. We propose three ways to integrate transient obfuscation in different security mechanisms. First, we show how it can be used to prevent intellectual property theft and illegal reuse in a cloud-based HLS scenario. Then, we extend this work to watermarking, by exploiting the side-effects of transient obfuscation on HLS tools to identify stolen designs. Finally, we show how this method can also be used against hardware Trojans, both by preventing insertion and by facilitating detection
Cozzi, Maxime. "Infrared Imaging for Integrated Circuit Trust and Hardware Security". Thesis, Montpellier, 2019. http://www.theses.fr/2019MONTS046.
Texto completo da fonteThe generalization of integrated circuits and more generally electronics to everyday life systems (military, finance, health, etc) rises the question about their security. Today, the integrity of such circuits relies on a large panel of known attacks for which countermeasures have been developed. Hence, the search of new vulnerabilities represents one of the largest contribution to hardware security. The always rising complexity of dies leads to larger silicon surfaces.Circuit imaging is therefore a popular step among the hardware security community in order to identify regions of interest within the die. In this objective, the work presented here proposes new methodologies for infrared circuit imaging. In particular, it is demonstrated that statistical measurement analysis can be performed for automated localization of active areas in an integrated circuit.Also, a new methodology allowing efficient statistical infrared image comparison is proposed. Finally, all results are acquired using a cost efficient infrared measurement platform that allows the investigation of weak electrical source, detecting power consumption as low as 200 µW
Guitard, Nicolas. "Caractérisation de défauts latents dans les circuits intégrés soumis à des décharges électrostatiques". Phd thesis, Université Paul Sabatier - Toulouse III, 2006. http://tel.archives-ouvertes.fr/tel-00139542.
Texto completo da fonteCamponogara, Viera Raphael. "Simulating and modeling the effects of laser fault injection on integrated circuits". Thesis, Montpellier, 2018. http://www.theses.fr/2018MONTS072/document.
Texto completo da fonteLaser fault injections induce transient faults into ICs by locally generating transient currents that temporarily flip the outputs of the illuminated gates. Laser fault injection can be anticipated or studied by using simulation tools at different abstraction levels: physical, electrical or logical. At the electrical level, the classical laser-fault injection model is based on the addition of current sources to the various sensitive nodes of MOS transistors. However, this model does not take into account the large transient current components also induced between the VDD and GND of ICs designed with advanced CMOS technologies. These short-circuit currents provoke a significant IR drop that contribute to the fault injection process. This thesis describes our research on the assessment of this contribution. It shows by simulation and experiments that during laser fault injection campaigns, laser-induced IR drop is always present when considering circuits designed in deep submicron technologies. It introduces an enhanced electrical fault model taking the laser-induced IR-drop into account. It also proposes a methodology that uses standard CAD tools to allow the use of the enhanced electrical model to simulate laser-induced faults at the electrical level in large-scale circuits. On the basis of further simulations and experimental results, we found that, depending on the laser pulse characteristics, the number of injected faults may be underestimated by a factor as large as 3 if the laser-induced IR-drop is ignored. This could lead to incorrect estimations of the fault injection threshold, which is especially relevant to the design of countermeasure techniques for secure integrated systems. Furthermore, experimental and simulation results show that even though laser fault injection is a very local and accurate fault injection technique, the induced IR drops have a global effect spreading through the supply network. This gives experimental evidence that the effect of laser illumination is not as local as usually considered
Bérubé, Benoit-Louis. "Développement d'une technologie NMOS pour la conception de fonctions électroniques avancées". Mémoire, Université de Sherbrooke, 2010. http://savoirs.usherbrooke.ca/handle/11143/1567.
Texto completo da fonteDefrance, Nicolas. "Caractérisation et modélisation de dispositifs de la filière nitrure pour la conception de circuits intégrés de puissance hyperfréquences". Lille 1, 2007. https://pepite-depot.univ-lille.fr/LIBRE/Th_Num/2007/50376-2007-Defrance.pdf.
Texto completo da fonteMaghrebi, Houssem. "Les contre-mesures par masquage contre les attaques HO-DPA : évaluation et amélioration de la sécurité en utilisant des encodages spécifiques". Electronic Thesis or Diss., Paris, ENST, 2012. http://www.theses.fr/2012ENST0083.
Texto completo da fonteSide channel attacks take advantage of the fact that the power consumption of a cryptographic device depends on the internally used secret key. A very common countermeasure against side channel attacks is masking. It consists in splitting the sensitive variable of cryptographic algorithms into random shares (the masked data and the random mask) so that the knowledge on a subpart of the shares does not give information on the sensitive data itself. However, other attacks, such as higher-order side channel attacks, can defeat masking schemes. These attacks consist in combining the shares in order to cancel (at least partially) the effects of the mask. The overall goal of this thesis is to give a deep analysis of higher-order attacks and to improve the robustness of masking schemes.The first part of this thesis focuses on higher-order attacks. We propose three novel distinguishers. Theoretical and experimental results show the advantages of these attacks when applied to a masking countermeasure. The second part of this thesis is devoted to a formal security evaluation of hardware masking schemes. We propose a new side channel metric to jointly cover the attacks efficiency and the leakage estimation.In the last part, we propose three novel masking schemes remaining more efficient than the state-of-the-art masking. They remove (or at least reduce) the dependency between the leakage and the sensitive variable when the leakage function is known e.g. the Hamming weight or the Hamming distance leakage model). The new solutions have been evaluated within a security framework proving their excellent resistance against higher-order attacks
El, Abbazi Adil. "Etude et réalisation d'une nouvelle cellule TEM à support rotatif pour des mesures CEM des circuits : Application du modèle ICEM". Phd thesis, Rennes, INSA, 2006. http://www.theses.fr/2006ISAR0001.
Texto completo da fonteThe quick growth of electronic applications towards higher frequencies requires the development of new models as well as appropriate measurement methods regarding EMC in integrated circuits (I. C). TEM cell measurement is one of the key methods making it possible to evaluate the emission of these circuits. In this thesis, the results of the study, the design and the optimization of a TEM cell, as well as the development of the ICEM model, will be presented. The measurement effectiveness of the cell, which reduces RF interference thanks to a protection bell, is highlighted; it enables to improve localization accuracy for the emission sources of the component. This study has taken advantage of the development of the ICEM model of the microcontroller, taking into account many technological aspects. Finally, we noted that the results of the TEM cell design and of the ICEM model are highly significant to predict any emission of the IC before tapeout
Guilley, Sylvain. "Contre-mesures géométriques aux attaques exploitant les canaux cachés". Phd thesis, Télécom ParisTech, 2007. http://pastel.archives-ouvertes.fr/pastel-00002562.
Texto completo da fonteLaabidi, Selma. "Méthodologie de conception de composants intégrés protégés contre les attaques par corrélation". Phd thesis, Ecole Nationale Supérieure des Mines de Saint-Etienne, 2010. http://tel.archives-ouvertes.fr/tel-00488013.
Texto completo da fonteLacruche, Marc. "Caractérisation sécuritaire de circuits basse-consommation face aux attaques par laser". Electronic Thesis or Diss., Aix-Marseille, 2016. http://www.theses.fr/2016AIXM4331.
Texto completo da fonteThe increasing complexity of integrated circuits and the explosion of the number of mobile devices today makes power consumption minimisation a priority in circuit design. However, it is necessary to make sure that it does not compromise the security of sensitive circuits. In this regard, physical attacks are a particular concern, as mobile devices are ideal targets for these attacks.This work aims at evaluating the impact of body-biasing on circuit vulnerability to laser attacks. These methods allow to dynamically adjust the performance/consumption ratio of a circuit by modifying the bias voltage of the body. It is divided in four chapters. It begins by introducing cryptography, physical attacks and low power design methods. Then the test bench used during this thesis is described, as well as the developpement work done in order to allow its automation. Then an initial study of the impact of short duration laser pulses on SRAM memories is presented. The third chapter reports the results of a laser fault injection campaign on memories subjected to Forward Body-Biasing. The results show a sensitivy increase of the circuits when supply voltage is lowered and FBB is activated. Based on these results, the last chapter introduces a method using the body-biasing and voltage scaling capabilities of a microcontroller to harden a hardware AES embedded on the latter.In conclusion, this works shows that low-power design methods can induce additional security risks if they are not carefully taken into account. However the additional capabilities of the circuits intended for power consumption reduction can be used in a different way to enhance device resillience to attacks
Maghrebi, Houssem. "Les contre-mesures par masquage contre les attaques HO-DPA : évaluation et amélioration de la sécurité en utilisant des encodages spécifiques". Phd thesis, Télécom ParisTech, 2012. http://pastel.archives-ouvertes.fr/pastel-00913472.
Texto completo da fontePoucheret, François. "Injections électromagnétiques : développement d’outils et méthodes pour la réalisation d’attaques matérielles". Thesis, Montpellier 2, 2012. http://www.theses.fr/2012MON20255/document.
Texto completo da fonteAttacks based on fault injection consist in disturbing a cryptographic computation in order to extract critical information on the manipulated data. Fault attacks constitute a serious threat against applications, due to the expected effects: bypassing control and protection, granting access to some restricted operations… Nevertheless, almost of classical ways (T°,V,F) and optical attacks are limited on the newest integrated circuits, which embed several countermeasures as active shield, glitch detectors, sensors… In this context, potentials of Electromagnetic active attacks must undoubtedly be taken into account, because of their benefits (penetrating characteristics, contactless energy transmission, low cost power production…). In this work, EM active attacks based on continuous mode are presented, with a particular attention to the development and optimization of injection probes, with a complete characterization of EM fields provided by each probe at the IC surface. Finally, some experiments are realized on internal clock generator or on true random numbers generators, then evaluated to prove the efficiency of these techniques. Keywords. Hardware Attacks, Faults Attacks, EM induced faults, CMOS Integrated Circuits
De, Nardi Christophe. "Techniques d'analyse de défaillance de circuits intégrés appliquées au descrambling et à la lecture de données sur des composants mémoires non volatiles". Toulouse, INSA, 2009. http://eprint.insa-toulouse.fr/archive/00000307/.
Texto completo da fonteProtection of data stored on integrated circuit memories is a major preoccupation of our society. Today, these circuits are everywhere, from electronics for the general public (SIM charts, USB flash memories), to satellites, bank cards and numerical passports. This thesis strives to answer the following question: “Is it possible to physically read the information stored in a non volatile memory (NVM)?”. Contrary to software attacks, physical approaches (hardware) destroy components. To reach the information contained in the core of a memory, this progressive destruction must be controlled. We have developed a four stage method adapted to each NVM family: 1) technological analysis, 2) address descrambling, 3) sample preparation to make data accessible and 4) data reading. The difficulty and complexity of this work can be better understood if we start with the desired result. For example, the data (0 or 1) of flash memory cell corresponds to the presence/absence of a charge of several hundred electrons stored on the floating gate of a transistor. Detecting the correct value requires a technique with strong topographic and potential resolution, which is as non invasive as possible to avoid erasing the electrons which are by nature, highly mobile. For current memory technologies (node ≥90nm), we show that passive voltage contrast (PVC) or electric modes of Atomic Force Microscopy (AFM) are adapted to these constraints. With this approach, stage n°3 of sample preparation is the key step to expose storage location of programmed charges without losing them. The method described in this thesis is based on a functional and physical characterization of memories coupled with an understanding of component preparation and analysis techniques. The experience gained over the past three years shows the importance of choosing the right reading technique and adjusting parameters according to the type of memory to be analyzed. For future technologies (node ≤65nm) or silicon on insulator (SOI), our method should remain applicable
Zbrzeski, Adeline. "Circuits intégrés d’enregistrement et d’analyse en temps réel des potentiels de champ neuronaux : application au traitement de la maladie de Parkinson, par contrôle adaptatif de stimulations cérébrales profondes". Thesis, Bordeaux 1, 2011. http://www.theses.fr/2011BOR14328/document.
Texto completo da fonteParkinson’s disease is the second most common neurodegenerative diseases throughout theworld. In this context, the research project associated with this thesis is to improve the symptomatictreatment of Parkinson’s disease through the development process of deep brain stimulationadaptive. The work of this thesis is based on the design of an ASIC for recording andprocessing of neural signals, in response to a variety of issues : ongoing treatment and real-timefocus on specific bands of very low-frequency and highly configurable. The goal is to use theprocessed information to the control and generation of a stimulation signal. This ASIC wasdeveloped, characterized and used electronically in a context in vivo. A closed-loop system wasmade from the ASIC, showing functional. These in vivo validations open up many possibilitiesfor investigation of the concept of closed-loop brain stimulation
Lacruche, Marc. "Caractérisation sécuritaire de circuits basse-consommation face aux attaques par laser". Thesis, Aix-Marseille, 2016. http://www.theses.fr/2016AIXM4331/document.
Texto completo da fonteThe increasing complexity of integrated circuits and the explosion of the number of mobile devices today makes power consumption minimisation a priority in circuit design. However, it is necessary to make sure that it does not compromise the security of sensitive circuits. In this regard, physical attacks are a particular concern, as mobile devices are ideal targets for these attacks.This work aims at evaluating the impact of body-biasing on circuit vulnerability to laser attacks. These methods allow to dynamically adjust the performance/consumption ratio of a circuit by modifying the bias voltage of the body. It is divided in four chapters. It begins by introducing cryptography, physical attacks and low power design methods. Then the test bench used during this thesis is described, as well as the developpement work done in order to allow its automation. Then an initial study of the impact of short duration laser pulses on SRAM memories is presented. The third chapter reports the results of a laser fault injection campaign on memories subjected to Forward Body-Biasing. The results show a sensitivy increase of the circuits when supply voltage is lowered and FBB is activated. Based on these results, the last chapter introduces a method using the body-biasing and voltage scaling capabilities of a microcontroller to harden a hardware AES embedded on the latter.In conclusion, this works shows that low-power design methods can induce additional security risks if they are not carefully taken into account. However the additional capabilities of the circuits intended for power consumption reduction can be used in a different way to enhance device resillience to attacks