Artigos de revistas sobre o tema "Cache codée"
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Ding, Wei, Yuanrui Zhang, Mahmut Kandemir e Seung Woo Son. "Compiler-Directed File Layout Optimization for Hierarchical Storage Systems". Scientific Programming 21, n.º 3-4 (2013): 65–78. http://dx.doi.org/10.1155/2013/167581.
Texto completo da fonteCalciu, Irina, M. Talha Imran, Ivan Puddu, Sanidhya Kashyap, Hasan Al Maruf, Onur Mutlu e Aasheesh Kolli. "Using Local Cache Coherence for Disaggregated Memory Systems". ACM SIGOPS Operating Systems Review 57, n.º 1 (26 de junho de 2023): 21–28. http://dx.doi.org/10.1145/3606557.3606561.
Texto completo da fonteCharrier, Dominic E., Benjamin Hazelwood, Ekaterina Tutlyaeva, Michael Bader, Michael Dumbser, Andrey Kudryavtsev, Alexander Moskovsky e Tobias Weinzierl. "Studies on the energy and deep memory behaviour of a cache-oblivious, task-based hyperbolic PDE solver". International Journal of High Performance Computing Applications 33, n.º 5 (15 de abril de 2019): 973–86. http://dx.doi.org/10.1177/1094342019842645.
Texto completo da fonteMittal, Shaily, e Nitin. "Memory Map: A Multiprocessor Cache Simulator". Journal of Electrical and Computer Engineering 2012 (2012): 1–12. http://dx.doi.org/10.1155/2012/365091.
Texto completo da fonteMoon, S. M. "Increasing cache bandwidth using multiport caches for exploiting ILP in non-numerical code". IEE Proceedings - Computers and Digital Techniques 144, n.º 5 (1997): 295. http://dx.doi.org/10.1049/ip-cdt:19971283.
Texto completo da fonteMa, Ruhui, Haibing Guan, Erzhou Zhu, Yongqiang Gao e Alei Liang. "Code cache management based on working set in dynamic binary translator". Computer Science and Information Systems 8, n.º 3 (2011): 653–71. http://dx.doi.org/10.2298/csis100327022m.
Texto completo da fonteDas, Abhishek, e Nur A. Touba. "A Single Error Correcting Code with One-Step Group Partitioned Decoding Based on Shared Majority-Vote". Electronics 9, n.º 5 (26 de abril de 2020): 709. http://dx.doi.org/10.3390/electronics9050709.
Texto completo da fonteSimecek, Ivan, e Pavel Tvrdík. "A new code transformation technique for nested loops". Computer Science and Information Systems 11, n.º 4 (2014): 1381–416. http://dx.doi.org/10.2298/csis131126075s.
Texto completo da fonteLuo, Ya Li. "Research of Adaptive Control Algorithm Based on the Cached Playing of Streaming Media". Applied Mechanics and Materials 539 (julho de 2014): 502–6. http://dx.doi.org/10.4028/www.scientific.net/amm.539.502.
Texto completo da fonteHeirman, Wim, Stijn Eyerman, Kristof Du Bois e Ibrahim Hur. "Automatic Sublining for Efficient Sparse Memory Accesses". ACM Transactions on Architecture and Code Optimization 18, n.º 3 (junho de 2021): 1–23. http://dx.doi.org/10.1145/3452141.
Texto completo da fonteПуйденко, Вадим Олексійович, e Вячеслав Сергійович Харченко. "МІНІМІЗАЦІЯ ЛОГІЧНОЇ СХЕМИ ДЛЯ РЕАЛІЗАЦІЇ PSEUDO LRU ШЛЯХОМ МІЖТИПОВОГО ПЕРЕХОДУ У ТРИГЕРНИХ СТРУКТУРАХ". RADIOELECTRONIC AND COMPUTER SYSTEMS, n.º 2 (26 de abril de 2020): 33–47. http://dx.doi.org/10.32620/reks.2020.2.03.
Texto completo da fonteSasongko, Muhammad Aditya, Milind Chabbi, Mandana Bagheri Marzijarani e Didem Unat. "ReuseTracker : Fast Yet Accurate Multicore Reuse Distance Analyzer". ACM Transactions on Architecture and Code Optimization 19, n.º 1 (31 de março de 2022): 1–25. http://dx.doi.org/10.1145/3484199.
Texto completo da fonteZhang, Kang, Fan Fu Zhou e Alei Liang. "DCC: A Replacement Strategy for DBT System Based on Working Sets". Applied Mechanics and Materials 251 (dezembro de 2012): 114–18. http://dx.doi.org/10.4028/www.scientific.net/amm.251.114.
Texto completo da fonteDuangthong, Chatuporn, Pornchai Supnithi e Watid Phakphisut. "Two-Dimensional Error Correction Code for Spin-Transfer Torque Magnetic Random-Access Memory (STT-MRAM) Caches". ECTI Transactions on Computer and Information Technology (ECTI-CIT) 16, n.º 3 (18 de junho de 2022): 237–46. http://dx.doi.org/10.37936/ecti-cit.2022163.246903.
Texto completo da fonteGordon-Ross, Ann, Frank Vahid e Nikil Dutt. "Combining code reordering and cache configuration". ACM Transactions on Embedded Computing Systems 11, n.º 4 (dezembro de 2012): 1–20. http://dx.doi.org/10.1145/2362336.2399177.
Texto completo da fonteZhao, Yiqiang, Boning Shi, Qizhi Zhang, Yidong Yuan e Jiaji He. "Research on Cache Coherence Protocol Verification Method Based on Model Checking". Electronics 12, n.º 16 (11 de agosto de 2023): 3420. http://dx.doi.org/10.3390/electronics12163420.
Texto completo da fonteDing, Chen, Dong Chen, Fangzhou Liu, Benjamin Reber e Wesley Smith. "CARL: Compiler Assigned Reference Leasing". ACM Transactions on Architecture and Code Optimization 19, n.º 1 (31 de março de 2022): 1–28. http://dx.doi.org/10.1145/3498730.
Texto completo da fonteVishnekov, A. V., e E. M. Ivanova. "DYNAMIC CONTROL METHODS OF CACHE LINES REPLACEMENT POLICY". Vestnik komp'iuternykh i informatsionnykh tekhnologii, n.º 191 (maio de 2020): 49–56. http://dx.doi.org/10.14489/vkit.2020.05.pp.049-056.
Texto completo da fonteVishnekov, A. V., e E. M. Ivanova. "DYNAMIC CONTROL METHODS OF CACHE LINES REPLACEMENT POLICY". Vestnik komp'iuternykh i informatsionnykh tekhnologii, n.º 191 (maio de 2020): 49–56. http://dx.doi.org/10.14489/vkit.2020.05.pp.049-056.
Texto completo da fonteMa, Cong, Dinghao Wu, Gang Tan, Mahmut Taylan Kandemir e Danfeng Zhang. "Quantifying and Mitigating Cache Side Channel Leakage with Differential Set". Proceedings of the ACM on Programming Languages 7, OOPSLA2 (16 de outubro de 2023): 1470–98. http://dx.doi.org/10.1145/3622850.
Texto completo da fonteSahuquillo, Julio, Noel Tomas, Salvador Petit e Ana Pont. "Spim-Cache: A Pedagogical Tool for Teaching Cache Memories Through Code-Based Exercises". IEEE Transactions on Education 50, n.º 3 (agosto de 2007): 244–50. http://dx.doi.org/10.1109/te.2007.900021.
Texto completo da fonteLiu, Cong, Xinyu Xu, Zhenjiao Chen e Binghao Wang. "A Universal-Verification-Methodology-Based Testbench for the Coverage-Driven Functional Verification of an Instruction Cache Controller". Electronics 12, n.º 18 (9 de setembro de 2023): 3821. http://dx.doi.org/10.3390/electronics12183821.
Texto completo da fonteMakhkamova, Ozoda, e Doohyun Kim. "A Conversation History-Based Q&A Cache Mechanism for Multi-Layered Chatbot Services". Applied Sciences 11, n.º 21 (25 de outubro de 2021): 9981. http://dx.doi.org/10.3390/app11219981.
Texto completo da fonteLin, Bo, Shangwen Wang, Ming Wen e Xiaoguang Mao. "Context-Aware Code Change Embedding for Better Patch Correctness Assessment". ACM Transactions on Software Engineering and Methodology 31, n.º 3 (31 de julho de 2022): 1–29. http://dx.doi.org/10.1145/3505247.
Texto completo da fonteAnsari, Ali, Pejman Lotfi-Kamran e Hamid Sarbazi-Azad. "Code Layout Optimization for Near-Ideal Instruction Cache". IEEE Computer Architecture Letters 18, n.º 2 (1 de julho de 2019): 124–27. http://dx.doi.org/10.1109/lca.2019.2924429.
Texto completo da fonteTomiyama, Hiroyuki, e Hiroto Yasuura. "Code placement techniques for cache miss rate reduction". ACM Transactions on Design Automation of Electronic Systems 2, n.º 4 (outubro de 1997): 410–29. http://dx.doi.org/10.1145/268424.268469.
Texto completo da fonteRyoo, Jihyun, Mahmut Taylan Kandemir e Mustafa Karakoy. "Memory Space Recycling". Proceedings of the ACM on Measurement and Analysis of Computing Systems 6, n.º 1 (24 de fevereiro de 2022): 1–24. http://dx.doi.org/10.1145/3508034.
Texto completo da fonteBłaszyński, Piotr, e Włodzimierz Bielecki. "High-Performance Computation of the Number of Nested RNA Structures with 3D Parallel Tiled Code". Eng 4, n.º 1 (3 de fevereiro de 2023): 507–25. http://dx.doi.org/10.3390/eng4010030.
Texto completo da fonteBielecki, Włodzimierz, Piotr Błaszyński e Marek Pałkowski. "3D Tiled Code Generation for Nussinov’s Algorithm". Applied Sciences 12, n.º 12 (9 de junho de 2022): 5898. http://dx.doi.org/10.3390/app12125898.
Texto completo da fonteMurugan, Dr. "Hybrid LRU Algorithm for Enterprise Data Hub using Serverless Architecture". Turkish Journal of Computer and Mathematics Education (TURCOMAT) 12, n.º 4 (11 de abril de 2021): 441–49. http://dx.doi.org/10.17762/turcomat.v12i4.525.
Texto completo da fonteSteenkiste, P. "The impact of code density on instruction cache performance". ACM SIGARCH Computer Architecture News 17, n.º 3 (junho de 1989): 252–59. http://dx.doi.org/10.1145/74926.74954.
Texto completo da fonteMarathe, Jaydeep, e Frank Mueller. "Source-Code-Correlated Cache Coherence Characterization of OpenMP Benchmarks". IEEE Transactions on Parallel and Distributed Systems 18, n.º 6 (junho de 2007): 818–34. http://dx.doi.org/10.1109/tpds.2007.1058.
Texto completo da fonteNaik Dessai, Sanket Suresh, e Varuna Eswer. "Embedded Software Testing to Determine BCM5354 Processor Performance". International Journal of Software Engineering and Technologies (IJSET) 1, n.º 3 (1 de dezembro de 2016): 121. http://dx.doi.org/10.11591/ijset.v1i3.4577.
Texto completo da fonteOktrifianto, Rahmat, Dani Adhipta e Warsun Najib. "Page Load Time Speed Increase on Disease Outbreak Investigation Information System Website". IJITEE (International Journal of Information Technology and Electrical Engineering) 2, n.º 4 (10 de setembro de 2019): 114. http://dx.doi.org/10.22146/ijitee.46599.
Texto completo da fonteWang, Xiang, Zongmin Zhao, Dongdong Xu, Zhun Zhang, Qiang Hao, Mengchen Liu e Yu Si. "Two-Stage Checkpoint Based Security Monitoring and Fault Recovery Architecture for Embedded Processor". Electronics 9, n.º 7 (18 de julho de 2020): 1165. http://dx.doi.org/10.3390/electronics9071165.
Texto completo da fonteEswer, Varuna, e Sanket Suresh Naik Dessai. "Embedded Software Engineering Approach to Implement BCM5354 Processor Performance". International Journal of Software Engineering and Technologies (IJSET) 1, n.º 1 (1 de abril de 2016): 41. http://dx.doi.org/10.11591/ijset.v1i1.4568.
Texto completo da fonteWang, Weike, Xiang Wang, Pei Du, Yuntong Tian, Xiaobing Zhang, Qiang Hao, Zhun Zhang e Bin Xu. "Embedded System Confidentiality Protection by Cryptographic Engine Implemented with Composite Field Arithmetic". MATEC Web of Conferences 210 (2018): 02047. http://dx.doi.org/10.1051/matecconf/201821002047.
Texto completo da fonteBenini, L., A. Macii e A. Nannarelli. "Code compression architecture for cache energy minimisation in embedded systems". IEE Proceedings - Computers and Digital Techniques 149, n.º 4 (2002): 157. http://dx.doi.org/10.1049/ip-cdt:20020467.
Texto completo da fonteChen, W. Y., P. P. Chang, T. M. Conte e W. W. Hwu. "The effect of code expanding optimizations on instruction cache design". IEEE Transactions on Computers 42, n.º 9 (1993): 1045–57. http://dx.doi.org/10.1109/12.241594.
Texto completo da fonteFahringer, T., e A. Požgaj. "P3T+: A Performance Estimator for Distributed and Parallel Programs". Scientific Programming 8, n.º 2 (2000): 73–93. http://dx.doi.org/10.1155/2000/217384.
Texto completo da fonteShin, Dong-Jin, e Jeong-Joon Kim. "Cache-Based Matrix Technology for Efficient Write and Recovery in Erasure Coding Distributed File Systems". Symmetry 15, n.º 4 (6 de abril de 2023): 872. http://dx.doi.org/10.3390/sym15040872.
Texto completo da fonteSieck, Florian, Zhiyuan Zhang, Sebastian Berndt, Chitchanok Chuengsatiansup, Thomas Eisenbarth e Yuval Yarom. "TeeJam: Sub-Cache-Line Leakages Strike Back". IACR Transactions on Cryptographic Hardware and Embedded Systems 2024, n.º 1 (4 de dezembro de 2023): 457–500. http://dx.doi.org/10.46586/tches.v2024.i1.457-500.
Texto completo da fonteCho, Won, e Joonho Kong. "Memory and Cache Contention Denial-of-Service Attack in Mobile Edge Devices". Applied Sciences 11, n.º 5 (8 de março de 2021): 2385. http://dx.doi.org/10.3390/app11052385.
Texto completo da fonteSavage, John E., e Mohammad Zubair. "Evaluating Multicore Algorithms on the Unified Memory Model". Scientific Programming 17, n.º 4 (2009): 295–308. http://dx.doi.org/10.1155/2009/681708.
Texto completo da fonteXu, Xiaoran, Keith Cooper, Jacob Brock, Yan Zhang e Handong Ye. "ShareJIT: JIT code cache sharing across processes and its practical implementation". Proceedings of the ACM on Programming Languages 2, OOPSLA (24 de outubro de 2018): 1–23. http://dx.doi.org/10.1145/3276494.
Texto completo da fonteBottcher, Axel. "A visualization environment for super scalar machines". Facta universitatis - series: Electronics and Energetics 17, n.º 2 (2004): 199–208. http://dx.doi.org/10.2298/fuee0402199b.
Texto completo da fonteWang, Bei, Stephane Ethier, William Tang, Khaled Z. Ibrahim, Kamesh Madduri, Samuel Williams e Leonid Oliker. "Modern gyrokinetic particle-in-cell simulation of fusion plasmas on top supercomputers". International Journal of High Performance Computing Applications 33, n.º 1 (29 de junho de 2017): 169–88. http://dx.doi.org/10.1177/1094342017712059.
Texto completo da fonteIshitobi, Yuriko, Tohru Ishihara e Hiroto Yasuura. "Code and Data Placement for Embedded Processors with Scratchpad and Cache Memories". Journal of Signal Processing Systems 60, n.º 2 (5 de novembro de 2008): 211–24. http://dx.doi.org/10.1007/s11265-008-0306-3.
Texto completo da fontePARUCHURI, PAVAN KUMAR, Satyanarayana CH, Ananda Rao A e Radica Raju P. "Design and Implementation of Task Reprocessing on Medium-large Multi-core Architecture". Application and Theory of Computer Technology 2, n.º 3 (27 de abril de 2017): 25. http://dx.doi.org/10.22496/atct.v2i3.80.
Texto completo da fonteMorse, Gregory. "Self-Spectre, Write-Execute and the Hidden State". Tatra Mountains Mathematical Publications 73, n.º 1 (1 de agosto de 2019): 131–44. http://dx.doi.org/10.2478/tmmp-2019-0010.
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