Teses / dissertações sobre o tema "Analog and mixed-signal integrated circuits"
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Fayed, Ayman Adel. "Adaptive techniques for analog and mixed signal integrated circuits". Connect to this title online, 2004. http://rave.ohiolink.edu/etdc/view?acc%5Fnum=osu1097519730.
Texto completo da fonteTitle from first page of PDF file. Document formatted into pages; contains xix, 232 p.; also includes graphics (some col.). Includes bibliographical references (p. 222-230).
Liu, Zhi-Hong. "Mixed-signal testing of integrated analog circuits and modules". Ohio : Ohio University, 1999. http://www.ohiolink.edu/etd/view.cgi?ohiou1181174339.
Texto completo da fonteVariyam, Pramodchandran. "Efficient testing techniques for analog and mixed-signal circuits". Diss., Georgia Institute of Technology, 1999. http://hdl.handle.net/1853/13457.
Texto completo da fonteSadeghi, Nima. "Design techniques for high-temperature analog and mixed-signal integrated circuits". Thesis, University of British Columbia, 2012. http://hdl.handle.net/2429/43092.
Texto completo da fonteKasturi, Prasan. "A CAD tool for analog and mixed signal CMOS circuits /". View online ; access limited to URI, 2006. http://0-digitalcommons.uri.edu.helin.uri.edu/dissertations/AAI3248232.
Texto completo da fonteBhattacharya, Sambuddha. "Template-driven parasitic-aware optimization of analog/RF IC layouts /". Thesis, Connect to this title online; UW restricted, 2005. http://hdl.handle.net/1773/6121.
Texto completo da fonteFei, Haibo. "High linearity analog and mixed-signal integrated circuit design". [Ames, Iowa : Iowa State University], 2007.
Encontre o texto completo da fonteHedayati, Raheleh. "High-Temperature Analog and Mixed-Signal Integrated Circuits in Bipolar Silicon Carbide Technology". Doctoral thesis, KTH, Skolan för informations- och kommunikationsteknik (ICT), 2017. http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-213697.
Texto completo da fonteQC 20170905
Al-Qutayri, Mahmoud A. "Testing techniques for analogue and mixed-signal integrated circuits". Thesis, University of Bath, 1992. https://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.317309.
Texto completo da fonteElshamy, Mohamed. "Design for security in mixed analog-digital integrated circuits". Electronic Thesis or Diss., Sorbonne université, 2021. http://www.theses.fr/2021SORUS093.
Texto completo da fonteRecently, the enormous cost of owning and maintaining a modern semiconductor manufacturing plant has coerced many companies to go fabless. By outsourcing the manufacturing IC/IP to third-party and often off-shore companies, the process has been extended to potentially untrustworthy companies. This has resulted in several security threats to the semiconductor industry such as counterfeiting, reverse engineering, and HTs insertion. In this thesis, we propose an anti-piracy countermeasure to protect AMS ICs/IPs, a novel HT attack for AMS ICs/IPs, and a novel PUF. More specifically, we propose an anti-piracy technique based on locking for programmable analog circuits. The proposed technique leverages the programmability fabric to implement a natural lock-less locking. We discuss its implementation and its resilience capabilities against foreseen attacks. The proposed HT attack for analog circuits leverages the test infrastructure. The HT is hidden effectively in a digital core and transfers its payload to the analog circuit via the test bus and the interface of the analog circuit to the test bus. Its key characteristic is that it is invisible in the analog domain. The proposed HT is demonstrated on two case studies. This thesis sheds light on the importance of developing new security and trust countermeasures tailored for analog circuits. The proposed PUF, called "neuron-PUF", uses a single spiking neuron as the source of entropy. Its key characteristic is that it uses a single PUF cell and temporal redundancy to generate an arbitrarily long key, which results in significant low area and power overheads compared to mainstream PUFs, such as delay-based and memory-based PUFs
Chang, Yu-Hsu Henry. "Macromodeling and simulation of high-performance mixed Analog/Digital circuits /". Thesis, Connect to this title online; UW restricted, 1994. http://hdl.handle.net/1773/5956.
Texto completo da fontePovazanec, Juraj. "Test process evaluation techniques for analogue and mixed signal integrated circuits". Thesis, Leeds Beckett University, 1996. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.309793.
Texto completo da fonteSon, Kyung-Im. "A multi-class, multi-dimensional classifier as a topology selector for analog circuit design / by Kyung-Im Son". Thesis, Connect to this title online; UW restricted, 1998. http://hdl.handle.net/1773/5919.
Texto completo da fonteThomsen, Axel. "High speed high accuracy signal processing with parallel analog circuits". Diss., Georgia Institute of Technology, 1992. http://hdl.handle.net/1853/13846.
Texto completo da fonteCheung, Wing-tai. "Geometric programming and signal flow graph assisted design of interconnect and analog circuits". Click to view the E-thesis via HKUTO, 2007. http://sunzi.lib.hku.hk/HKUTO/record/B39558526.
Texto completo da fontePerkins, Andrew John. "Structural testing and DFT insertion for analogue and mixed signal integrated circuits". Thesis, University of Southampton, 1999. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.299287.
Texto completo da fonteTwigg, Christopher M. "Floating Gate Based Large-Scale Field-Programmable Analog Arrays for Analog Signal Processing". Diss., Georgia Institute of Technology, 2006. http://hdl.handle.net/1853/11601.
Texto completo da fonteWemple, Ivan L. "Parasitic substrate modeling for monolithic mixed analog/digital circuit design and verification /". Thesis, Connect to this title online; UW restricted, 1996. http://hdl.handle.net/1773/5944.
Texto completo da fonteWu, Pan. "The Design of High-Frequency Continuous-Time Integrated Analog Signal Processing Circuits". PDXScholar, 1993. https://pdxscholar.library.pdx.edu/open_access_etds/1162.
Texto completo da fonte張永泰 e Wing-tai Cheung. "Geometric programming and signal flow graph assisted design of interconnect and analog circuits". Thesis, The University of Hong Kong (Pokfulam, Hong Kong), 2007. http://hub.hku.hk/bib/B39558526.
Texto completo da fonteChakrabarti, Sudip. "Test generation for fault isolation in analog and mixed-mode circuits". Diss., Georgia Institute of Technology, 2001. http://hdl.handle.net/1853/14899.
Texto completo da fonteal-Sarʻāwī, Said Fares. "Design techniques for low power mixed analog-digital circuits with application to smart wireless systems /". Title page, contents and abstract only, 2003. http://web4.library.adelaide.edu.au/theses/09PH/09pha461.pdf.
Texto completo da fonteHirschman, Karl D. "Process development of an analog/digital mixed-mode BiCMOS system at RIT /". Online version of thesis, 1992. http://hdl.handle.net/1850/11238.
Texto completo da fonteHooper, Mark S. "Submicron CMOS programmable analog floating-gate circuits and arrays using DC-DC converters". Diss., Available online, Georgia Institute of Technology, 2005, 2005. http://etd.gatech.edu/theses/available/etd-12032004-155022/unrestricted/Hooper%5FMark%5FS%5F200505%5Fphd.pdf.
Texto completo da fonteKucic, Matthew, Committee Member ; Hasler, Paul, Committee Chair ; Heck, Bonnie, Committee Member ; Cressler, John, Committee Member ; Anderson, David, Committee Member. Vita. Includes bibliographical references.
Toner, Michael F. "MADBIST : a scheme for built-in self-test of mixed analog-digital integrated circuits". Thesis, McGill University, 1996. http://digitool.Library.McGill.CA:80/R/?func=dbin-jump-full&object_id=40451.
Texto completo da fontePark, Shinwoong. "Reconfigurable Discrete-time Analog FIR filters for Wideband Analog Signal Processing". Diss., Virginia Tech, 2019. http://hdl.handle.net/10919/99794.
Texto completo da fontePHD
Yu, Xinyu. "High-temperature Bulk CMOS Integrated Circuits for Data Acquisition". Case Western Reserve University School of Graduate Studies / OhioLINK, 2006. http://rave.ohiolink.edu/etdc/view?acc_num=case1144420886.
Texto completo da fonteKucic, Matthew R. "Analog programmable filters using floating-gate arrays". Thesis, Georgia Institute of Technology, 2000. http://hdl.handle.net/1853/13755.
Texto completo da fontePalakurthi, Praveen Kumar. "Design of a low voltage analog to digital converter". To access this resource online via ProQuest Dissertations and Theses @ UTEP, 2009. http://0-proquest.umi.com.lib.utep.edu/login?COPT=REJTPTU0YmImSU5UPTAmVkVSPTI=&clientId=2515.
Texto completo da fonteMore, Shailesh [Verfasser], Doris [Akademischer Betreuer] Schmitt-Landsiedel e Helmut [Akademischer Betreuer] Gräb. "Aging Degradation and Countermeasures in Deep-submicrometer Analog and Mixed Signal Integrated Circuits / Shailesh More. Gutachter: Helmut Gräb ; Doris Schmitt-Landsiedel. Betreuer: Doris Schmitt-Landsiedel". München : Universitätsbibliothek der TU München, 2012. http://d-nb.info/1024354938/34.
Texto completo da fonteOliveira, Vlademir de Jesus Silva [UNESP]. "Desenvolvimento de um sintetizador de freqüência de baixo custo em tecnologia CMOS". Universidade Estadual Paulista (UNESP), 2009. http://hdl.handle.net/11449/100280.
Texto completo da fonteConselho Nacional de Desenvolvimento Científico e Tecnológico (CNPq)
Nesta tese, propõe-se um sintetizador de freqüência baseado em phase locked loops (PLL) usando uma arquitetura que utiliza um dual-path loop filter, constituído de componentes passivos e um integrador digital. A proposta é empregar técnicas digitais, para reduzir o custo da implementação do sintetizador de freqüência, e flexibilizar o projeto do loop filter, para possibilitar que a arquitetura opere em uma faixa de freqüência larga de operação e com redução de tons espúrios. O loop filter digital é constituído de um contador crescente/ decrescente cujo clock é proveniente da amostragem da diferença de fase de entrada. As técnicas digitais aplicadas ao loop filter se baseiam em alterações da operação do contador, em tempos pré-estabelecidos, os quais são controlados digitalmente. Essas técnicas possibilitam reduzir o tempo de estabelecimento do PLL ao mesmo tempo em que problemas de estabilidade são resolvidos. No desenvolvimento da técnica de dual-path foi realizado o estudo de sua estabilidade, primeiramente, considerando a aproximação do PLL para um sistema linear e depois usando controle digital. Nesse estudo foram deduzidas as equações do sistema, no domínio contínuo e discreto, tanto para o projeto da estabilidade, quanto para descrever o comportamento do PLL. A metodologia top-down é usada no projeto do circuito integrado. As simulações em nível de sistema são usadas, primeiramente, para as criações das técnicas e posteriormente para a verificação do seu comportamento, usando modelos calibrados com os blocos projetados em nível de transistor. O circuito integrado é proposto para ser aplicado em identificação por rádio freqüência (RFID) na banda de UHF (Ultra High Frequency), usando multi-standard, e deve operar na faixa de 850 MHz a 1010 MHz. O sintetizador de freqüência foi projetado na tecnologia CMOS...
In this thesis, a frequency synthesizers phase locked loops (PLL) based with an architecture that uses a dual-path loop filter consisting of passive components and a digital integrator are proposed. The objective is to employ digital techniques to reduce the implementation cost and get loop filter design flexibility to enable the architecture to have a large tuning range operation and spurious reduction. The digital loop filter is based in an up/down counter where the phase difference is sampled to generate the clock of the counter. The techniques applied in the digital path are based in digitally controlled changes in the counter operation in predefined time points. These techniques provide PLL settling time reductions whiling the stability issues are solved. The stability study of the proposed dual path has been developed. First the linear system approximation for the PLL has been assumed and then employing digital control. The continuous and discrete time equations of architecture were derived in that study applied to stability design as well as to describe the architecture behavior. The top-down methodology has been applied to the integrated circuit design. In the beginning, the system level simulations are used for the techniques creation and then the behavioral models that were calibrated with transistor level blocks are simulated. The application of the circuit is proposed to Radio Frequency Identification (RFID) using UHF (Ultra High Frequency) band for multi-standards application and will operate in range of 850 MHz to 1010 MHz. The proposed frequency synthesizer has been designed in the AMS 0.35 μm CMOS technology with 2V power supply. A 300 μs of settling time and 140 Hz of resolution was obtained in simulations. The proposed frequency synthesizer have low complexity and shown a reference noise suppression about 45.6 dB better than the conventional architecture
Qureshi, Muhammad Shakeel. "Integrated front-end analog circuits for mems sensors in ultrasound imaging and optical grating based microphone". Diss., Atlanta, Ga. : Georgia Institute of Technology, 2009. http://hdl.handle.net/1853/29613.
Texto completo da fonteCommittee Chair: Hasler, Paul; Committee Co-Chair: Degertekin, Levent; Committee Member: Anderson, David; Committee Member: Ayazi, Farrokh; Committee Member: Brand, Oliver; Committee Member: Hesketh, Peter. Part of the SMARTech Electronic Thesis and Dissertation Collection.
Ramakrishnan, Shubha. "A system design approach to neuromorphic classifiers". Diss., Georgia Institute of Technology, 2013. http://hdl.handle.net/1853/51718.
Texto completo da fonteSadeghifar, Mohammad Reza. "On High-Speed Digital-to-Analog Converters and Semi-Digital FIR Filters". Licentiate thesis, Linköpings universitet, Elektroniska Kretsar och System, 2014. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-114274.
Texto completo da fontePetre, Csaba. "Sim2spice a tool for compiling simulink designs on FPAA and applications to neuromorphic circuits /". Thesis, Atlanta, Ga. : Georgia Institute of Technology, 2009. http://hdl.handle.net/1853/31820.
Texto completo da fonteCommittee Chair: Paul Hasler; Committee Member: Christopher Rozell; Committee Member: David Anderson. Part of the SMARTech Electronic Thesis and Dissertation Collection.
Xu, Ping. "High-frequency Analog Voltage Converter Design". PDXScholar, 1994. https://pdxscholar.library.pdx.edu/open_access_etds/4891.
Texto completo da fonteOliveira, Vlademir de Jesus Silva. "Desenvolvimento de um sintetizador de freqüência de baixo custo em tecnologia CMOS /". Ilha Solteira : [s.n.], 2009. http://hdl.handle.net/11449/100280.
Texto completo da fonteBanca: Suely Cunha Amaro Mantovani
Banca: Jozué Vieira Filho
Banca: Marcelo Arturo Jara Perez
Banca: Paulo Augusto Dal fabbro
Resumo: Nesta tese, propõe-se um sintetizador de freqüência baseado em phase locked loops (PLL) usando uma arquitetura que utiliza um dual-path loop filter, constituído de componentes passivos e um integrador digital. A proposta é empregar técnicas digitais, para reduzir o custo da implementação do sintetizador de freqüência, e flexibilizar o projeto do loop filter, para possibilitar que a arquitetura opere em uma faixa de freqüência larga de operação e com redução de tons espúrios. O loop filter digital é constituído de um contador crescente/ decrescente cujo clock é proveniente da amostragem da diferença de fase de entrada. As técnicas digitais aplicadas ao loop filter se baseiam em alterações da operação do contador, em tempos pré-estabelecidos, os quais são controlados digitalmente. Essas técnicas possibilitam reduzir o tempo de estabelecimento do PLL ao mesmo tempo em que problemas de estabilidade são resolvidos. No desenvolvimento da técnica de dual-path foi realizado o estudo de sua estabilidade, primeiramente, considerando a aproximação do PLL para um sistema linear e depois usando controle digital. Nesse estudo foram deduzidas as equações do sistema, no domínio contínuo e discreto, tanto para o projeto da estabilidade, quanto para descrever o comportamento do PLL. A metodologia top-down é usada no projeto do circuito integrado. As simulações em nível de sistema são usadas, primeiramente, para as criações das técnicas e posteriormente para a verificação do seu comportamento, usando modelos calibrados com os blocos projetados em nível de transistor. O circuito integrado é proposto para ser aplicado em identificação por rádio freqüência (RFID) na banda de UHF (Ultra High Frequency), usando multi-standard, e deve operar na faixa de 850 MHz a 1010 MHz. O sintetizador de freqüência foi projetado na tecnologia CMOS... (Resumo completo, clicar acesso eletrônico abaixo)
Abstract: In this thesis, a frequency synthesizers phase locked loops (PLL) based with an architecture that uses a dual-path loop filter consisting of passive components and a digital integrator are proposed. The objective is to employ digital techniques to reduce the implementation cost and get loop filter design flexibility to enable the architecture to have a large tuning range operation and spurious reduction. The digital loop filter is based in an up/down counter where the phase difference is sampled to generate the clock of the counter. The techniques applied in the digital path are based in digitally controlled changes in the counter operation in predefined time points. These techniques provide PLL settling time reductions whiling the stability issues are solved. The stability study of the proposed dual path has been developed. First the linear system approximation for the PLL has been assumed and then employing digital control. The continuous and discrete time equations of architecture were derived in that study applied to stability design as well as to describe the architecture behavior. The top-down methodology has been applied to the integrated circuit design. In the beginning, the system level simulations are used for the techniques creation and then the behavioral models that were calibrated with transistor level blocks are simulated. The application of the circuit is proposed to Radio Frequency Identification (RFID) using UHF (Ultra High Frequency) band for multi-standards application and will operate in range of 850 MHz to 1010 MHz. The proposed frequency synthesizer has been designed in the AMS 0.35 μm CMOS technology with 2V power supply. A 300 μs of settling time and 140 Hz of resolution was obtained in simulations. The proposed frequency synthesizer have low complexity and shown a reference noise suppression about 45.6 dB better than the conventional architecture
Doutor
Korhonen, E. (Esa). "On-chip testing of A/D and D/A converters:static linearity testing without statistically known stimulus". Doctoral thesis, University of Oulu, 2010. http://urn.fi/urn:isbn:9789514263064.
Texto completo da fonteMichal, Vratislav. "Design of CMOS analog integrated circuits as readout electronics for High-TC superconductor and semiconductor terahertz bolometric sensors". Phd thesis, Université Pierre et Marie Curie - Paris VI, 2006. http://tel.archives-ouvertes.fr/tel-00417838.
Texto completo da fonteChamas, Ibrahim. "The Analysis and Design of Phase-tunable Low-Power Low-Phase-Noise I/Q Signal Sources for Analog Phase Calibrated Transceivers". Diss., Virginia Tech, 2008. http://hdl.handle.net/10919/102076.
Texto completo da fontePh.D.
While resting in bed due to illness, the Dutch scientist Christiaan Huygens keenly observed that the pendulums of two clocks hanging on the wall moved synchronously when the clocks were hung close to each other. He concluded that these two oscillatory systems were forced to move in unison by virtue of mechanical coupling through the wall. In essence, each pendulum injected mechanical vibrations into the wall that was strong enough to lock the adjacent pendulum into synchronous motion. Injection locking of oscillatory systems plays a critical role in communication systems ranging from frequency division, to generating clocks (oscillators) with finer phase separation, to the synthesis of orthogonal (quadrature) clocks. All communication systems have the same basic form. Firstly, there will some type of an information or data source which can be a keyboard or a microphone in a smartphone. The source is connected to a receiver by some sort of a channel. In wireless systems, the channel is the air medium. Moreover, to comply with the FCC and 3GPP requirements, data can only be transmitted wirelessly within a predefined set of frequencies and with stringent emission requirements to avoid interference with other wireless systems. These frequencies are generated by high fidelity clock sources, also known as oscillators. Consider a group of people sharing the same room and hence the same channel want to share information. Without regulating the “loudness” of each communicating ensemble, the quality of communication can be severely impaired. Moreover, it is to be expected that information can be shared more efficiently if each pair is allocated non-overlapping timeslots – speak when others are quiet. Called time orthogonality, all wireless systems require precise orthogonal (quadrature) clock sources to improve the communication efficiency. The precision of quadrature clocks is determined by the amplitude and phase accuracy. This dissertation takes a deep dive into the analysis and implementation of high accuracy quadrature (I/Q) clock sources using the concept of injection locking. These I/Q clocks or oscillators, also known as quadrature voltage controlled oscillators (QVCOs), have gained enormous popularity in the last decade. The first part of this work focuses on the analysis and modeling of QVCOs. The analysis focuses on understanding the oscillator basic performance characteristics, and on examining the quadrature accuracy in presence of process variations. New design parameters and circuit insight are developed and a generalized first order linear model and a one-port model are proposed. A qualitative and quantitative study of the effect of mismatch on the phase imbalance and amplitude error is presented. Particularly, closed-form intuitive expressions of the phase imbalance and amplitude error are derived and verified via circuit simulation. Based on our understanding of the various mechanisms affecting the quadrature accuracy, the second part of this work introduces a very efficient quadrature phase calibration technique based The phase-tunable QVCO (PT-QVCO) achieves an ultra-wide I/Q phase tuning range without affecting the oscillator other performance metrics. The proposed topology was successfully verified in silicon using a 5GHz prototype. The third part of this work introduces a new low-power, low-phase-noise injection coupled QVCO (IC-QVCO) topology. An X-band IC-QVCO prototype was successfully verified in a 0.18m RF CMOS process. In the fourth part of this work, we explore the implementation of QVCOs as potential I/Q sources at millimeter-wave (MMW) frequencies. Among the several design challenges that emerge as the oscillator frequency is scaled into the MMW band, precise quadrature synthesis and adequate frequency tuning range are among the hardest to achieve. After describing the limitation of using an conventional frequency tuning techniques, we propose an alternative approach based on the fundamental operation of QVCOs that outperforms existing solutions.
Laraba, Asma. "Conception en vue de test de convertisseurs de signal analogique-numérique de type pipeline". Phd thesis, Université de Grenoble, 2013. http://tel.archives-ouvertes.fr/tel-00947360.
Texto completo da fonteFrança, Ferreira João Alberto de. "Contribution to the Design of a Real-Time Fourier Transformer in Integrated Technology". Thesis, Université Paris-Saclay (ComUE), 2019. http://www.theses.fr/2019SACLS502.
Texto completo da fonteThe constant increase of bandwidths and bitrates in everyday applications (e.g., telecommunications, internet of things), as also in more specialized applications (e.g., radar, radio astronomy observations), imposes stringent constraints in terms of speed, power consumption and heat dissipation at the analog-to-digital conversion stages of acquisition chains. Therefore, a current trend is to perform signal processing (e.g., Fourier transform) in the analog domain to be able to process ultra-wideband signals with low latency and in a more energy-efficient way. Many of the analog signal processing architectures rely on blocks that have not been widely explored in the literature: arbitrary group delay filters. These filters are generally realized in SAW technology or with discrete (non-integrated) microwave structures, leading to filters with limited bandwidth and high loss, in the case of SAW devices, or with a large size and weight, in the case of microwave filters. Very few integrated circuit implementations have been reported to date.The innovation presented in this thesis has two aspects, a system-level architectural aspect, which gave rise to the proposal for an analog Fourier transformer architecture that enables improve the precision performance when compared to the previously reported architectures, and an aspect concerning the development of linear group delay filter design methods and their implementation in an integrated circuit technology. Three different filter networks were designed using these methods, a minimum phase band-pass ladder filter, a balanced all-pass network with positive-slope linear group delay, and a balanced all-pass network with a linear group delay of negative slope. It has also been shown that the all-pass filters can be transformed into distributed amplifier-based transversal filters
Douglas, Dale Scott. "Flicker noise in cmos lc oscillators". Thesis, Georgia Institute of Technology, 2008. http://hdl.handle.net/1853/26550.
Texto completo da fonteChitnis, Danial. "Single photon avalanche diodes for optical communications". Thesis, University of Oxford, 2013. http://ora.ox.ac.uk/objects/uuid:5fd582dd-8167-4fe4-88f8-871ba905ade1.
Texto completo da fonteFisher, Andrew N. "Efficient, sound formal verification for analog/mixed-signal circuits". Thesis, The University of Utah, 2016. http://pqdtopen.proquest.com/#viewpdf?dispub=10003590.
Texto completo da fonteThe increasing demand for smaller, more efficient circuits has created a need for both digital and analog designs to scale down. Digital technologies have been successful in meeting this challenge, but analog circuits have lagged behind due to smaller transistor sizes having a disproportionate negative affect. Since many applications require small, low-power analog circuits, the trend has been to take advantage of digital's ability to scale by replacing as much of the analog circuitry as possible with digital counterparts. The results are known as \emph{digitally-intensive analog/mixed-signal} (AMS) circuits. Though such circuits have helped the scaling problem, they have further complicated verification. This dissertation improves on techniques for AMS property specifications, as well as, develops sound, efficient extensions to formal AMS verification methods. With the \emph{language for analog/mixed-signal properties} (LAMP), one has a simple intuitive language for specifying AMS properties. LAMP provides a more procedural method for describing properties that is more straightforward than temporal logic-like languages. However, LAMP is still a nascent language and is limited in the types of properties it is capable of describing. This dissertation extends LAMP by adding statements to ignore transient periods and be able to reset the property check when the environment conditions change. After specifying a property, one needs to verify that the circuit satisfies the property. An efficient method for formally verifying AMS circuits is to use the restricted polyhedral class of \emph{zones}. Zones have simple operations for exploring the reachable state space, but they are only applicable to circuit models that utilize constant rates. To extend zones to more general models, this dissertation provides the theory and implementation needed to soundly handle models with ranges of rates. As a second improvement to the state representation, this dissertation describes how octagons can be adapted to model checking AMS circuit models. Though zones have efficient algorithms, it comes at a cost of over-approximating the reachable state space. Octagons have similarly efficient algorithms while adding additional flexibility to reduce the necessary over-approximations. Finally, the full methodology described in this dissertation is demonstrated on two examples. The first example is a switched capacitor integrator that has been studied in the context of transforming the original formal model to use only single rate assignments. Th property of not saturating is written in LAMP, the circuit is learned, and the property is checked against a faulty and correct circuit. In addition, it is shown that the zone extension, and its implementation with octagons, recovers all previous conclusions with the switched capacitor integrator without the need to translate the model. In particular, the method applies generally to all the models produced and does not require the soundness check needed by the translational approach to accept positive verification results. As a second example, the full tool flow is demonstrated on a digital C-element that is driven by a pair of RC networks, creating an AMS circuit. The RC networks are chosen so that the inputs to the C-element are ordered. LAMP is used to codify this behavior and it is verified that the input signals change in the correct order for the provided SPICE simulation traces.
Hou, Junwei. "Concurrent fault simulation for mixed-signal circuits". Diss., Georgia Institute of Technology, 2001. http://hdl.handle.net/1853/15735.
Texto completo da fonteChen, Jin. "Fault modeling and test techniques for analog and mixed-signal circuits /". Digital version accessible at:, 1998. http://wwwlib.umi.com/cr/utexas/main.
Texto completo da fonteSAMPATH, HEMANTH KUMAR. "A MODULE GENERATION ENVIRONMENT FOR MIXED-SIGNAL CIRCUITS". University of Cincinnati / OhioLINK, 2003. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1052321882.
Texto completo da fonteKANKIPATI, SUNDER RAJAN. "MACRO MODEL GENERATION FOR SYNTHESIS OF ANALOG AND MIXED SIGNAL CIRCUITS". University of Cincinnati / OhioLINK, 2004. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1077297705.
Texto completo da fonteClewell, Matthew John. "Reducing signal coupling and crosstalk in monolithic, mixed-signal integrated circuits". Thesis, Kansas State University, 2013. http://hdl.handle.net/2097/18138.
Texto completo da fonteDepartment of Electrical Engineering
William B. Kuhn
Designers of mixed-signal systems must understand coupling mechanisms at the system, PC board, package and integrated circuit levels to control crosstalk, and thereby minimize degradation of system performance. This research examines coupling mechanisms in a RF-targeted high-resistivity partially-depleted Silicon-on-Insulator (SOI) IC process and applying similar coupling mitigation strategies from higher levels of design, proposes techniques to reduce coupling between sub-circuits on-chip. A series of test structures was fabricated with the goal of understanding and reducing the electric and magnetic field coupling at frequencies up to C-Band. Electric field coupling through the active-layer and substrate of the SOI wafer is compared for a variety of isolation methods including use of deep-trench surrounds, blocking channel-stopper implant, blocking metal-fill layers and using substrate contact guard-rings. Magnetic coupling is examined for on-chip inductors utilizing counter-winding techniques, using metal shields above noisy circuits, and through the relationship between separation and the coupling coefficient. Finally, coupling between bond pads employing the most effective electric field isolation strategies is examined. Lumped element circuit models are developed to show how different coupling mitigation strategies perform. Major conclusions relative to substrate coupling are 1) substrates with resistivity 1 kΩ·cm or greater act largely as a high-K insulators at sufficiently high frequency, 2) compared to capacitive coupling paths through the substrate, coupling through metal-fill has little effect and 3) the use of substrate contact guard-rings in multi-ground domain designs can result in significant coupling between domains if proper isolation strategies such as the use of deep-trench surrounds are not employed. The electric field coupling, in general, is strongly dependent on the impedance of the active-layer and frequency, with isolation exceeding 80 dB below 100 MHz and relatively high coupling values of 40 dB or more at upper S-band frequencies, depending on the geometries and mitigation strategy used. Magnetic coupling was found to be a strong function of circuit separation and the height of metal shields above the circuits. Finally, bond pads utilizing substrate contact guard-rings resulted in the highest degree of isolation and the lowest pad load capacitance of the methods tested.