Literatura científica selecionada sobre o tema "2T Memory Architecture"
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Artigos de revistas sobre o assunto "2T Memory Architecture"
Reis, Dayane, Michael Niemier e Xiaobo Sharon Hu. "The Implications of Ferroelectric FET Device Models to the Design of Computing-in-Memory Architectures". Journal of Integrated Circuits and Systems 16, n.º 1 (5 de abril de 2021): 1–8. http://dx.doi.org/10.29292/jics.v16i1.477.
Texto completo da fonteUmemoto, Yukiko, Koji Nii, Jiro Ishikawa, Makoto Yabuuchi, Kazuyoshi Okamoto, Yasumasa Tsukamoto, Shinji Tanaka et al. "28 nm 50% Power-Reducing Contacted Mask Read Only Memory Macro With 0.72-ns Read Access Time Using 2T Pair Bitcell and Dynamic Column Source Bias Control Technique". IEEE Transactions on Very Large Scale Integration (VLSI) Systems 22, n.º 3 (março de 2014): 575–84. http://dx.doi.org/10.1109/tvlsi.2013.2246201.
Texto completo da fonteWang, Yin, Hongwei Tang, Yufeng Xie, Xinyu Chen, Shunli Ma, Zhengzong Sun, Qingqing Sun et al. "An in-memory computing architecture based on two-dimensional semiconductors for multiply-accumulate operations". Nature Communications 12, n.º 1 (7 de junho de 2021). http://dx.doi.org/10.1038/s41467-021-23719-3.
Texto completo da fonteTeses / dissertações sobre o assunto "2T Memory Architecture"
Melul, Franck. "Développement d'une nouvelle génération de point mémoire de type EEPROM pour les applications à forte densité d'intégration". Electronic Thesis or Diss., Aix-Marseille, 2022. http://www.theses.fr/2022AIXM0266.
Texto completo da fonteThe objective of this thesis was to develop a new generation of EEPROM memory for high reliability and high density applications. First, an innovative memory cell developed by STMicroelectronics - eSTM (Split-gate charge storage memory with buried vertical selection transistor) - was studied as a reference cell. In a second part, to improve the reliability of the eSTM cell and to allow a more aggressive miniaturization of the EEPROM cell, a new memory architecture has been proposed: the BitErasable cell. It showed an excellent reliability and allowed to bring elements of under-standing on the degradation mechanisms present in these memory devices with buried selection transistor. This new architecture also offers the possibility to individually erase cells in a memory array: bit by bit. Aware of the great interest of bit-by-bit erasing, a new erasing mechanism by hot hole injection has been proposed for the eSTM cell. It has shown performances and a level of reliability perfectly compatible with the industrial requirements of Flash-NOR applications
Trabalhos de conferências sobre o assunto "2T Memory Architecture"
Zhao, Yuansheng, Zixuan Shen, Jiarui Xu, Kevin C. T. Chai, Yanqing Wu e Chao Wang. "A Novel Transpose 2T-DRAM based Computing-in-Memory Architecture for On-chip DNN Training and Inference". In 2023 IEEE 5th International Conference on Artificial Intelligence Circuits and Systems (AICAS). IEEE, 2023. http://dx.doi.org/10.1109/aicas57966.2023.10168641.
Texto completo da fonte