Rozprawy doktorskie na temat „Wireline communication”

This thesis consists of an introduction and five parts dealing with digital communication. Three parts address Discrete Multi-Tone modulation (DMT), a wireline form of Orthogonal Frequency Division Multiplexing (OFDM). One part addresses channel estimation in wireless OFDM and one addresses multiuser detection in wireless Direct Sequence-Code Division Multiple Access (DS- CDMA).The first part presents a new duplex method, called Zipper, for Very High bit rate Digital Subscriber Lines (VDSL). It is a duplex method that offer high flexibility and compatibility with existing services in the access network. The second part presents a digital Radio Frequency Interference (RFI) suppression method. It is located in the frequency domain and it can be used by any DMT-based VDSL system. The third part presents a method to run Zipper in an asynchronous mode with only a small performance loss. This can be of interest for telecom operators when constructing a VDSL system. The fourth part examines the trade-off between pilot symbol spacing and symbol error rate in a wireless OFDM system using Pilot Symbol Assisted Modulation (PSAM). The last part presents a low complexity multiuser detector for wireless DS-CDMA. It consists of a pipelined detector structure that produces Maximum Likelihood Secence Detector (MLSD) decisions on some of the received bits in the sequence. The remaining, previously undetected bits, are fed to a secondary post-processor.<br>Godkänd; 1999; 20070404 (ysko)

Clock and data recovery (CDR) circuit and frequency synthesizer are two essential timing circuits in wireline and wireless communication systems, respectively. With multigigabits/s high speed links and emerging 4G wireless system widely used in communication backbone infrastructures and consumer electronic devices, effective design of CDR and frequency synthesizer has become more and more important. The advanced scaled-down CMOS process has the limitations of leakage current, low supply voltage and process variation which pose great challenge to the analog circuit design. To overcome these issues, a digital intensive CDR solution is needed. Besides, it is desirable for the CDR to cover a wide range of data-rate and to be reference-less for improved flexibility. As for the frequency synthesizer design, the support for multi-standard to reduce the cost and area is desirable. In this work, a digital reference-less CDR is proposed to support continuous datarate ranging from 1 Gbps to 16 Gbps. The CDR adopts an 8 GHz~16 GHz DCO to achieve low random noise performance. A reference-less digital frequency locking loop is included in the system as the acquisition assistance for the CDR loop. To address the difficulty of jitter and stability evaluations for bang-band CDR, a Simulink model is developed to find out the jitter transfer (JTRAN), jitter generation (JGEN) and jitter tolerance (JTOL) performances for the CDR. The prototype CDR is implemented in a 65 nm CMOS process. The core area is 0.68 mm². At 16 Gbps, the CDR consumes a power of 92.5 mW and is able to tolerate a sinusoidal jitter with an amplitude of 0.4 UI and a frequency of 4 MHz. The second part of this dissertation develops a frequency synthesizer for multistandard wireless receivers. The frequency synthesizer is based on an analog fractional-N PLL. Optimally-coupled quadrature voltage-controlled-oscillator (QVCO), dividers and harmonic rejection single sideband mixer (HR-SSBmixer) are combined to synthesize the desired frequency range without posing much phase noise penalty on the QVCO. The QVCO adopts a new phase-shift scheme to improve phase noise and to eliminate bimodal oscillation. Combining harmonic rejection and single sideband mixing, the HR-SSBmixer is developed to suppress spurious signals. Designed in a 0.13-μm CMOS technology, the synthesizer occupies an active area of 1.86 mm² and consumes 35.6 to 52.62 mW of power. Measurement results show that the synthesizer frequency range, the phase noise, the settling time and the spur performances meet the specifications of the wireless receivers for the above standards. For a wide range frequency synthesizer, an automatic frequency calibration circuit (AFC) is needed to select proper oscillator tuning curve before the PLL settling. An improved counter-based AFC is proposed in this dissertation that provides a more robust and faster tuning curve searching process. The proposed AFC adopts a time-to-digital converter (TDC), which is able to captures the fractional VCO cycle information within the counting window, to improve the AFC frequency detection accuracy. The TDC-based AFC is designed in a 0.13-μm CMOS technology. Simulation results show that the TDCbased AFC greatly improves the frequency detection accuracy and consequently for a given frequency detection resolution reduces the AFC calibration time.

While the RF building blocks of narrowband system-on-chip designs have increasingly been created in CMOS during the past decade, researchers have started to look at the possibility of implementation of broadband transceivers in CMOS technology. High speed optical links with operating frequencies of up to 40 GHz and ultra wideband (UWB) wireless systems operating in 3 to 10 GHz frequency band are examples of these broadband applications. CMOS offers a low fabrication cost, and a higher level of integration compared with compound semiconductor technologies that currently claim broadband RFIC applications. <br /><br /> In this work, we focus on the design of broadband low-noise amplifiers: the fundamental building blocks of high data rate wireline and wireless telecommunication systems. A well established microwave engineering technique -distributed amplification- with a potential bandwidth up to the cut-off frequency of transistors is employed. However, the implementation of distributed amplifiers in CMOS imposes new challenges, such as gain attenuation because of substrate loss of on-chip inductors, a typical large die area, and a large noise-figure. These problems have been addressed in this dissertation as described below. <br /><br /> On-chip inductors, the essential components of the distributed amplifiers' gate and drain transmission lines, dissipate more and more power in silicon substrates as well as in metal lines as frequency increases, which in turn reduces the gain and deteriorates the input/output matching. Using active negative resistors implemented by a capacitively source degenerated configuration, we have fully compensated the loss of the transmission lines in order to achieve a flat gain of 10 dB over the entire DC-to-44 GHz bandwidth. <br /><br /> We have addressed another drawback of distributed amplifiers, large die area, by utilizing closely-placed RF transmission lines instead of spiral inductors. Because of a more compact implementation of transmission lines, the area of the distributed amplifiers is considerably reduced at the expense of extra design steps required for the modeling of the closely-placed RF transmission lines. A post-layout simulation method is developed to take into account the effect of inductive and capacitive coupling by incorporating a 3D EM simulator into the design process. A 9-dB 27-GHz distributed amplifier has been fabricated in an area as small as 0. 17 <em>mm</em>² using 180nm TSMC's CMOS process. <br /><br /> For wireless applications (UWB), a very low-noise figure is required for the broadband preamplifier. Conventional distributed amplifiers fail to provide a low noise figure mainly because of the noise injected by the terminating resistor of the gate transmission lines. We have replaced the terminating resistor with a frequency-dependent resistor which trades off the low frequency input matching of the distributed amplifier (not required for UWB) with a better noise performance. Our proposed design provides a gain of 12 dB with an average noise figure of 3. 4 dB over the entire 3-10 GHz band, advancing the state-of-the-art implementation of broadband LNAs.

The Community Broadband Investment Act, introduced in the Georgia legislature in 2012 and 2013 is a reflection of a broader national debate over the role of government investment in broadband infrastructure. The bill would limit local governments' ability to invest in broadband infrastructure for their communities because of arguments that government entry into the telecommunications sector crowds-out private competition, does not serve the public adequately, and lacks a comprehensive business model or best practices. A closer look at the history of utility regulation and various economic perspectives on the proper government role in utility provision reveals that government has had an extensive historical role in utility infrastructure investment and regulation, and several economic doctrines support the conclusion that government can be helpful in facilitating effective broadband service to their communities. Case studies of different models of municipal broadband networks in Georgia reveal that government entry can facilitate private sector competition, often provides quality service, and has a set of best practices. The success of municipal broadband reveals an evolution in the approach to telecommunications regulation from a regulated monopoly approach to a public-private cooperation approach which considers public participation with private entities on a dynamic scale. Government-entry into the broadband market was a rational decision for several Georgia communities due to their unique set of circumstances, and while municipal broadband may not be the answer to many communities' problems with meeting public demand, communities should be allowed to maintain flexibility in their decision-making about how to best serve their residents, effectively allowing them to decide which combination of public and private advantages they can leverage to meet the demand of their communities in relation to their unique local characteristics.

The objective of the research in this dissertation is to demonstrate the viability of using silicon-germanium (SiGe) bipolar/complementary metal-oxide semiconductor (BiCMOS) technologies in novel high-speed, high-performance wireless and wireline applications. These applications include self-healing integrated systems, W-Band phased array radar systems, and multi-gigabit wireline transceiver systems. The contributions from this research are summarized below: 1. Design of a wideband 8-18 GHz signal source with the best reported tuning range and die area combination for self-healing applications [95]. 2. Design of a robust, multi-band 8-10/ 16-20 GHz signal source with amplitude-locking for self-healing applications. A figure-of-merit (FoM) is proposed that combines tuning range and die area, and this work achieves the best FoM compared with state-of-the art [51]. 3. First ever reported on-die healing of image-rejection ratio of an 8-18 GHz mixer integrated with the multi-band test signal source [52], [96]. 4. Design of a 94 GHz differential Colpitts oscillator with 14% tuning range that spans 86-99 GHz for phased-array radar systems. 5. Identification of technology platform related bottlenecks in multi-gigabit wireline systems. A novel study of linearity of switching transistors in a current-mode logic (CML) gate. 6. A novel FoM that can be used to predict large-signal CML delay using small-signal Y-parameter techniques [97].

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No. of bitstreams: 1 thiagorodriguesoliveira.pdf: 11824049 bytes, checksum: ab8b7db8e1cc38ac7c875396e2379120 (MD5) Previous issue date: 2015-03-24<br>Essa tese de doutorado apresenta, inicialmente, uma metodologia a ser empregada para a caracterização de redes de energia elétrica para fins de comunicação de dados. Esta metodologia engloba todos os procedimentos e ferramentas de processamento de sinais necessárias para a estimação de características importantes para a avaliação de canais de comunicação de dados. Em seguida, são apresentados resultados da aplicação de tal metodologia em dados provenientes de uma campanha de medição realizada em ambientes internos em residências brasileiras. Algumas características importantes desses canais, tais como ganho médio, banda de coerência, tempo de coerência, o valor quadrático médio do espalhamento de atraso, capacidade do canal e densidade espectral de potência do ruído, são analizadas considerando três bandas de frequência: de 1,7 até 30 MHz, de 1,7 até 50 MHz e de 1,7 até 100 MHz. Comparando os resultados de canais power line communication (PLC) em ambientes residenciais brasileiros com aqueles medidos em outros países, tais como Espanha, Estados Unidos, França e Itália, podemos notar que canais PLC brasileiros apresentam, em geral, menores atenuações, são menos seletivos em frequência e possuem menores espalhamentos de atraso. Por fim, um novo meio de comunicação baseada nas tecnologias PLC e sem fio é apresentada e definida como híbrido PLC-sem fio o qual permite a comunicação física e à distância com a rede de energia elétrica para fins de comunicação de dados. Tal canal de comunicação é avaliado em residências brasileiras e importantes características são extraídas e discutidas. Embora o canal híbrido PLC-sem fio tenha se mostrado mais adverso que o canal PLC para a comunicação de dados, a introdução da mobilidade, de uma forma que é impossível de se obter em sistemas puramente PLC, constitui sua principal vantagem. Essa mobilidade é um importante atrativo que coloca sistemas híbridos em uma posição privilegiada dentre os candidatos para compor a infraestrutura de telecomunicações em redes inteligentes (smart grids), ou para ser usada como uma ferramenta para promover a inclusão digital da população carente de países pobres ou em desenvolvimento.<br>This work outlines initially a methodology to be applied to the characterization of electric power grids for data communication purposes. This methodology englobes all the procedures and required signal processing tools for a reliable estimation of features that allow the suitability of a media for data communication. Next, PLC (power line communication) channel results provided by the use of such methodology in a data set obtained from a measurement campaing in in-home Brazilian places are presented. The analyzed channel features are the average channel gain, the coherence bandwidth, the coherence time, the root mean squared delay spread, the channel capacity and the noise power spectral density by considering the following frequency bands: from 1.7 up to 30 MHz, from 1.7 up to 50 MHz and from 1.7 up to 100 MHz. Comparisons among the results for in-home Brazilian PLC channels with other provided for other countries such as Spain, United States, France and Italy showed that, in general, in-home Brazilian PLC channels present smaller attenuation, are less frequency selective and showed smaller delay spread than these countries. Finally, a new medium to provide data communication is presented and defined as hybrid PLC-wireless, in which PLC and wireless technologies are combined. Such novel communication channel is characterized in in-home Brazilian places and important channel features are estimated and discussed. Though the hybrid PLC-wireless channel has been shown more adverse than the PLC channel, the introduction of mobility is its main advantage, something that is impossible in traditional PLC technologies. Thus, this mobility is an important issue that puts hybrid PLC-wireless technologies in a privileged position among the candidates to form the communication infrastructure for smart grids, or to be used as a too to solve the digital divide problem that is more accentuated in poor and in developing countries.

This document is a thesis submitted in partial fulfilment of the requirements of the University of Hertfordshire for the degree of Doctor of Philosophy (Part Time) in 'EMC in Wire-line Communications' in the School of Electronic, Communication and Electrical Engineering at the University of Hertfordshire. It describes a programme of research into the modelling and measurement of radio frequency interference emissions from various communication networks including Power Line (Tele)communications (PLC/PLT) and Digital Subscriber Line (DSL). An introduction and literature review are followed by the results of practical measurements on installed networks. These measurements include antenna gain and Longitudinal Conversion Loss (LCL). Power line communication networks, splitterless DSL and home phoneline networks in buildings are studied and modelled and the models are compared with the measured results. Improved EMC test methods are also described, in particular the modelling and design of four types of portable antennas for use in radiated EMC measurements with improved sensitivity at frequencies up to 30 MHz. The first type is a set of three manually tuned loop antennas covering 100 kHz - 30 MHz. The second is a set of three loop antennas that cover a similar frequency range but with remote tuning via an optical fibre link, under the control of software which also controls an EMC measuring receiver. The third type is a larger (1.6 m diameter) tuned loop covering 1.75 - 10 MHz that allows the measuring system noise floor to be below the typical atmospheric noise floor. The fourth type is an electrically short dipole covering 10 - 30 MHz with improved matching. The protection requirements for various types of radio communication services are analysed and are compared with emission levels from various types of wireline communication network. A review of existing applicable EMC standards and standards under development is also presented.

This thesis discusses low-power wireline receivers with particular focus on clocking circuitry and architectures. These clocking solutions can be used for a 1-D partial response channel as well as for a conventional DC coupled channel. The receiver front end for a 1-D channel requires more consideration to recover an NRZ signal from the received narrow pulses. Two possible solutions are presented. First, a full-rate detection technique is presented, where the speed is limited by the settling time of a latch circuit which has to be less than 1 UI. Second, a novel demuxing technique is introduced. It is demonstrated through theory, simulation and measurement results that the half-rate architecture can improve maximum achievable speed by a factor of 1.6. The distribution and alignment of high-frequency clocks across a wide bus of links is a signi¯cant challenge in modern computing systems. A low power clock source is demonstrated by incorporating a bu®er into a cross-coupled oscillator. Because the load is isolated from the tank, the oscillator can directly drive 50-Ohm impedances or large capacitive loads with no additional bu®ering. Using this topology, a quadrature VCO (QVCO) is implemented in 0.13 um digital CMOS. The QVCO oscillates at 20 GHz, consumes 20 mW and provides 12% tuning range. Injection locked oscillators (ILOs) are an attractive clocking tool for low-power area- e±cient wireline receivers. In this work, we explored their use as a clock deskew element, a clock recovery unit and a programmable jitter lter. A study of both LC and ring ILOs indicates signi¯cant variation in their jitter tracking bandwidth when used to provide large phase shifts. By selectively injecting di®erent phases of a quadrature-LC or ring VCO, this problem is obviated resulting in reduced phase noise. First, an ILO based half-rate clock recovery technique is presented, which can be used for AC coupled links where low frequency signal components are attenuated by the channel. The nonlinear path comprises a hysteresis latch that recovers the missing low frequency content and a linear path that boosts the high frequency component by taking advantage of the high pass channel response. By optimally combining them, the front-end recovers NRZ signals up to 13 Gb/s burning only 26 mW in 90 nm CMOS. A simple theory and simulation technique for ILO-based receivers is discussed. The clock recovery technique is veried with experimental results at 5-10 Gb/s in 90 nm CMOS consuming 70 mW and acquiring lock within 1.5 ns. Second, a clock forwarded 65nm CMOS receiver uses two ILOs to frequency- multiply, deskew, and track correlated jitter on a pulsed clock forwarded from the transmitter. Di®erent data rates and latency mismatch between the clock and data paths are ac- commodated by a jitter tracking bandwidth that is controllable up to 300MHz. Each receiver consumes 0.92 pJ/bit operating at 7.4 Gb/s and has a jitter tolerance of 1.5 UI at 200MHz.

The advent of serial tera-bit telecommunication and multi-gigahertz I/O interfaces is posing challenges on the semiconductor and ATE industries. There is a gap in signal integrity testing between what has been specified in serial link standards and what can be practically tested in production. A thorough characterization and a more cost-effective test of the signal integrity, such as BER, jitter, and eye margin, are critical to identify and isolate the root cause of the system degradation and to the binning in production. In this dissertation, measurement and testing schemes on signal integrity are explored. A solution for diagnosing jitter and predicting the range of consequent BER is proposed. This solution is applicable to decomposition of correlated and uncorrelated jitter in both clock and data signals. The statistical information of jitter is estimated using TLC functions. TLC treats jitter in its original form, as a time series, resulting in good accuracy in the decomposition. Hardware results in a PLL indicate that the approach is still valid when the traditional histogram-based method fails. This approach can be implemented using only one-shot capture instead of multiple captures to average out the uncorrelated jitter from the correlated jitter. Therefore, the TLC functions enable test time reduction in jitter decomposition compared to traditional averaging methods. Hardware measurements on stressed data signals are presented to validate the proposed technique. We have also explored low cost, high bandwidth techniques using Built In Self Test(BIST) for on-chip jitter measurement. Undersampling provides a lowcost test solution for on-chip jitter measurement. However, it suffers from sampling clock phase error and time quantization noise. These timing uncertainties on the test accuracy of the traditional technique using a single channel structure can be alleviated by extracting the correlation between two channels using a single reference clock. Simulation results indicate that the proposed approach can achieve a better measurement accuracy and a higher degree of tolerance to sampling clock uncertainty and quantization error than does the single-channel structure, with little additional test overhead. TIADCs provide an attractive solution to the realization of analog front ends in high speed communication systems,such as 10GBASE-T and 10GBASEFiber. However, gain mismatch, offset mismatch, and sampling time mismatch between time-interleaved channels limit the performance of TIADCs. A low-cost test scheme is developed to measure timing mismatch using an undersampling clock. This method is applicable to an arbitrary number of channels, achieving picosecond resolution with low power consumption. Simulation results and hardware measurements on a 10GSps TIADC are presented to validate the proposed technique.<br>text

碩士<br>國立臺北科技大學<br>光電工程系研究所<br>102<br>In the future, access networks are driving the convergence of wireline and wireless networks to offer end users greater choice, convenience and variety in an efficient way. This study proposed a radio-over-fiber (RoF) system based on phase modulation technique, integrating fiber-to-the-home (FTTH) and RoF systems, are promising for multi-service access networks. This scheme can transmit both wireline and wireless signals on a single wavelength over a single fiber, which serves these two applications simultaneously. Experimental results show that the quality of wireline and wireless signals can be achieved user’s requirements. The system is sufficient to meet the standard of future communication network.

Network Coding is a technique which looks beyond traditional store-and-forward approach followed by routers and switches in communication networks, and as an extension introduces maps termed as ‘local encoding kernels’ and ‘global encoding kernels’ defined for each communication link in the network. The purpose of both these maps is to define rules as to how to combine the packets input on the node to form a packet going out on an edge. The paradigm of network coding was formally and for the first time introduced by Ahlswede et al. in [1], where they also demonstrated its use in case of single-source multiple-sink network multicast, although with use of much complex mathematical apparatus. In [1], examples of networks are also presented where it is shown that network coding can improve the overall throughput of the network which can not otherwise be realized by the conventional store-and-forward approach. The main result in [1], i.e. the capacity of single-source multiple-sinks information network is nothing but the minimum of the max-flows from source to each sink, was again proved by Li, Yeung, and Cai in [2] where they showed that only linear operations suffice to achieve the capacity of multicast network. The authors in [2] defined generalizations to the multicast problem, which they termed as linear broadcast, linear dispersion, and Generic LCM as strict generalizations of linear multicast, and showed how to build linear network codes for each of these cases. For the case of linear multicast, Koetter and Medard in [3] developed an algebraic framework using tools from algebraic geometry which also proved the multicast max-flow min-cut theorem proved in [1] and [2]. It was shown that if the size of the finite field is bigger than a certain threshold, then there always exists a solution to the linear multicast, provided it is solvable. In other words, a solvable linear multicast always has a solution in any finite field whose cardinality is greater than the threshold value. The framework in [3] also dealt with the general linear network coding problem involving multiple sources and multiple sinks with non-uniform demand functions at the sinks, but did not touched upon the key problem of finding the characteristic(s) of the field in which it may have solution. It was noted in [5] that a solvable network may not have a linear solution at all, and then introduced the notion of general linear network coding, where the authors conjectured that every solvable network must have a general linear solution. This was refuted by Dougherty, Freiling, Zeger in [6], where the authors explicitly constructed example of a solvable network which has no general linear solution, and also networks which have solution in a finite field of char 2, and not in any other finite field. But an algorithm to find the characteristic of the field in which a scalar or general linear solution(if at all) exists did not find any mention in [3] or [6]. It was a simultaneous discovery by us(as part of this thesis) as well as by Dougherty, Freiling, Zeger in [7] to determine the characteristics algorithmically. Applications of Network Coding techniques to wireless networks are seen in literature( [8], [9], [10]), where [8] provided a variant of max-flow min-cut theorem for wireless networks in the form of linear programming constraints. A new architecture termed as COPE was introduced in [10] which used opportunistic listening and opportunistic coding in wireless mesh networks.

碩士<br>國立臺灣大學<br>電子工程學研究所<br>101<br>The wireline communication has spawned a revival of interest in multimedia content distribution due to its high data bandwidth and reliability. Powerline communication (PLC) in digital home employs orthogonal frequency-division multiplexing (OFDM) modulation for high data rates in multi-path signal channels. The receiver estimates the channel’s characteristics during the reception of the preamble by the process of automatic gain control (AGC), which is an essential function in wireline receivers to adjust sensitivity to incoming signal strength. This work focuses on the analysis and design of high-linearity, fast-settling AGC in receiver front-end. Two key AGC building block applications, a high-linearity reconfiguration-based programmable gain amplifier (PGA) and a fast-settling feedforward AGC, are presented. In the PGA, linearity of amplifier is improved by adopting adaptive biasing circuit in a push-pull amplifier. Binary-weighted switching pseudo-exponential approximation technique is utilized for decibel-linear gain tuning. Reconfigurable PGA architecture is also employed to reduce parasitic effect and circuit complexity. In the AGC, a novel feedforward control scheme is proposed to achieve fast loop response requirement of OFDM-based receivers. The analysis and implementation consideration of key building blocks are provided in this work. Fabricated in 90-nm CMOS technology, the experimental results show that the linear characteristic of PGA is suitable for 1024 QAM in OFDM demodulation and 0.1 μs is used for the AGC system convergence while consuming 3.7 mW through 1.2-V supply.

碩士<br>國立臺灣大學<br>電子工程學研究所<br>105<br>This thesis presents a wide-rage wireline transmitter system in 40 nm CMOS technology. It can provide the receiver for testing with different standard of wireline communication such as 25 Gb/s、28 Gb/s and 32 Gb/s. It can also generate different types of PRBS data sequence：27-1、215-1、223-1、231-1 and four types of error injection rate to data sequence：10-3, 10-6, 10-9, and 0. With a built-in wide-rage phase-locked Loop, it can regard as a clock source of the system, which can be operated up to 32 Gb/s. This wireline transmitter system includes multiplexers, flip-flops, dividers, feed-forward equalizer and phase-locked loop. It can be triggered full-rate output data sequence by half-rate clock output from phase-locked loop integrated in the chip. Also, the channel loss can be compensated by the driver with feed-forward equalizer while transmitting data sequence. Also, the clock sample the data at the best sampling point under different frequency by the auto phase adjusted circuit. The measurement output data rate is up to 32 Gb/s and the output swing is 700mV in differential when feed-forward equalizer is ON. The whole system consumes 755mW. It can be selected different types of PRBS pattern, error injection and boosting amount of feed-forward equalizer by controlling the field programmable gate array (FPGA). The data sequence and error injection are confirmed in the operating range 20 Gb/s ~ 32 Gb/s under the bit-error-rate tester (BERT). Besides measuring the chip by bonding wire, the whole system is also packaged in QFN (Quad Flat No leads) to make the whole chip more complete.

Multiple users compete for a common resource like bandwidth to communicate data in interference networks. Existing approaches in dealing with interference limit the rate of communication due to paucity of shared resources. This limitation in the rate gets more glaring as the number of users in the network increases. For example, existing wireless systems either choose to orthogonalize the users (for example, Frequency Division Multiple Access (FDMA) systems or Code Division Multiple Access (CDMA) systems) or treat interference as Gaussian noise at the receivers. It is well known that these approaches are sub-optimal in general. Orthogonalization of users limit the number of available interference-free channels (known as degrees of freedom, abbreviated as DoF) and treating interference as noise means that the receiver cannot make use of the structure in the interfering signals. This motivates the need to analyze alternate transmit and decoding schemes in interference networks. This thesis mainly analyzes transmit schemes that use linear precoding for various configurations of interference networks with some practical constraints imposed by the use of finite input constellations, propagation delays, and channel state availability at the transmitters. The main contributions of this thesis are listed below. Achievable rates using precoding with finite constellation inputs in Gaussian Interference Channels (GIC) is analyzed. A metric for finding the approximate angle of rotation to maximally enlarge the Constellation Constrained (CC) capacity of two-user Gaussian Strong Interference Channel (GSIC) is proposed. Even as the Gaussian alphabet FDMA rate curve touches the capacity curve of the GSIC, with both the users using the same finite constellation, we show that the CC FDMA rate curve lies strictly inside the CC capacity curve at high powers. For a K-user MIMO GIC, a set of necessary and sufficient conditions on the precoders under which the mutual information between between relevant transmit-receive pairs saturate like in the single user case is derived. Gradient-ascent based algorithms to optimize the sum-rate achieved by precoding with finite constellation inputs and treating interference as noise are proposed. For a class of Gaussian interference networks with general message demands, identified as symmetrically connected interference networks, the expected sumspectral efficiency (in bits/sec/Hz) is shown to grow linearly with the number of transmitters at finite SNR, using a time-domain Interference Alignment (IA) scheme in the presence of line of sight (LOS) channels. For a 2×2 MIMO X-Network with M antennas at each node, we identify spacetime block codes that could be coupled with an appropriate precoding scheme to achieve the maximum possible sum-DoF of 4M 3 , for M = 3, 4. The proposed schemes are shown to achieve a diversity gain of M with SNR-independent finite constellation inputs. The proposed schemes have lower CSIT requirements compared to existing schemes. This thesis also makes an attempt to guarantee a minimum throughput when the zero-interference conditions cannot be satisfied in a wireline network with three unicast sessions with delays, using Precoding Based Network Alignment (PBNA). Three different PBNA schemes namely PBNA with time-varying local encoding coefficients (LECs), PBNA using transform approach and time-invariant LECs, and PBNA using transform approach and block time-varying LECs are proposed and their feasibility conditions analyzed.

Network coding has emerged as an attractive alternative to routing because of the through put improvement it provides by reducing the number of channel uses. In a wireless scenario, in addition, further improvement can be obtained through Physical layer Network Coding (PNC), a technique in which nodes are allowed to transmit simultaneously, instead of transmitting in orthogonal slots. In this thesis, the design and analysis of network coding schemes are considered, for wireless two-way relaying, multi-user Multiple Access Relay Channel (MARC) and wireline networks. In a wireless two-way relay channel with PNC, the simultaneous transmissions of user nodes result in Multiple Access Interference (MAI) at there lay node. The harmful effect of MAI is the presence of signal set dependent deep channel fade conditions, called singular fade states, under which the minimum distance of the effective constellation at the relay become zero. Adaptively changing the network coding map used at the relay according to channel conditions greatly reduces the impact of this MAI. In this work, we obtain these adaptive PNC maps, which are finite in number ,by completing partially filled Latin Squares and using graph vertex coloring. Having obtained the network coding maps, the set of all possible channel realizations is quantized into a finite number of regions, with a specific network coding map chosen in a particular region and such a quantization is obtained analytically for 2λ-PSK signal set. The performance of the adaptive PNC scheme for two-way relaying is analyzed and tight high SNR upper bounds are obtained for the average end-to-end symbol error probability, in terms of the average error probability of a point-to-point fading channel. The adaptive PNC scheme is generalized for two-way relaying with multiple antennas at the nodes. As an alternative to the adaptive PNC scheme for two-way relaying, a Distributed Space Time Coding (DSTC) scheme is proposed, which effectively re-moves the effect of singular fade states at the transmitting nodes itself without any Channel State Information at the Transmitter (CSIT), and without any need to change the PNC map as a function of channel fade conditions. It is shown that the singular fade states can be viewed equivalently as vector subspaces of C2, which are referred to as the singular fade subspaces. DSTC design criterion to minimize the number of singular fade subspaces and maximize the coding gain is formulated and explicit low decoding complexity DSTC designs are provided. For the K-user MARC, in which K source nodes want to transmit messages to a destination node D with the help of are lay node R, a new PNC scheme is proposed. Use of a many-to-one PNC map with conventional minimum squared Euclidean distance decoding at D, results in a loss of diversity order due to error propagation from the relay node. To counter this, we propose a novel low complexity decoder which offers the maximum diversity order of two. Next, we consider wire line networks and explore the connections between linear network coding, linear index coding and discrete polymatroids, which are the multi-set analogue of matroids. We define a discrete polymatroidal network and show that a fractional vector linear solution over a field Fq exists for a network if and only if the network is discrete polymatroidal with respect to a discrete polymatroid representable over Fq.An algorithm to construct networks starting from certain class of discrete polymatroids is provided. Every representation over Fq for the discrete polymatroid, results in a fractional vector linear solution over Fq for the constructed network. It is shown that a linear solution to an index coding problem exists if and only if there exists a representable discrete polymatroid satisfying certain conditions which are determined by the index coding problem considered. El Rouayheb et. al. showed that the problem of finding a multi-linear representation for a matroid can be reduced to finding a perfect linear index coding solution for an index coding problem obtained from that matroid. Multi-linear representation of a matroid can be viewed as a special case of representation of an appropriate discrete polymatroid. We generalize the result of El Rouayheb et. al. by showing that the problem of finding a representation for a discrete polymatroid can be reduced to finding a perfect linear index coding solution for an index coding problem obtained from that discrete polymatroid.

博士<br>國立清華大學<br>電子工程研究所<br>97<br>This study proposed new circuit design techniques to achieve high-performance CMOS integrated amplifiers for wireless/line communications at microwave frequencies. The design concepts were demonstrated by one narrowband and one broadband amplifiers, which were both realized in the standard 0.18-μm RF CMOS technology. The measured results presented superior performances compared with other published works using a similar or even more advanced CMOS technology. The designed narrowband amplifier is a 24-GHz balanced amplifier (BA) with a gain up to 45 dB. An effective technique, π–type parallel resonance (PPR), was proposed to boost the high frequency gain of a MOSFET by resonating out the inherent capacitances. The miniaturized lumped-element coupler in the circuit occupies a chip area of only ~ 2 % compared to that of the conventional transmission-line coupler. The BA consumes 123 mW from a supply voltage of 1 V. The proposed CMOS BA presents the highest gain of 45.0 dB with a chip area of 0.97 × 0.63 mm2 (core area: 0.78 × 0.43 mm2) among the published narrowband amplifiers with similar technologies and operation frequencies. The designed broadband amplifier is a 40-Gb/s transimpedance amplifier (TIA). From the measured S-parameters, a transimpedance gain of 51 dBΩ and a 3-dB bandwidth up to 30.5 GHz were observed. A gain-bandwidth product (GBW) enhancement technique, π-type inductor peaking (PIP), is proposed to achieve a bandwidth enhancement ratio (BWER) of 3.31. In addition, the PIP topology used at the input stage decreases the noise current as the operation frequency increases. Under a 1.8 V supply voltage, the TIA consumes 60.1 mW with a chip area of 1.17 × 0.46 mm2. The proposed CMOS TIA presents a GBW per DC power figure-of-merit (GBP/Pdc) of 180.1 GHzΩ/mW.

博士<br>國立清華大學<br>通訊工程研究所<br>99<br>This study proposes several circuit design techniques to achieve high performance CMOS transceiver chipset for wire-line communication. The circuit concepts are demonstrated by a 20-Gb/s CMOS 0.13-μm laser/modulator driver design and a 10-Gb/s CMOS 0.18-μm limiting amplifier design. The performance evaluation are as good as the advanced expensive III-V compound technology and the fabricated CMOS circuits are suitable for further integration with SERDES, CDR, and CODEC ICs for wire-line communication due to the small die size and low power consumption. The proposed 20-Gb/s laser/modulator driver is fabricated in 0.13-µm mixed-signal 1.2/2.5V 1P8M CMOS process. This work consists of a shunt-series inductor peaking pre-driver stage and a pre-emphasis output driver stage with source de-generation configuration including inductive local feedback network to enhance the operation bandwidth. The data rate is measured up to 20-Gb/s with 3.5VPP S.E. output amplitude in driving 50-Ω output load when the input amplitude is less than 0.15VPP and the rise/fall time of output waveform is less than 22-ps. The total power consumption is 900-mW with 1.2/4.0V dual supply and the chip die size is 900×800-µm2. The proposed 10-Gb/s current mode logic (CML) limiting amplifier is fabricated in 0.18-µm 1P6M CMOS process. This work consists of input equalizer, CML output buffer and gain stages with active-load inductive peaking, duty cycle correction (DCC) and gain control features. The circuit techniques include active load inductive peaking, source de-generation peaking and active feedback with current buffer in Cherry-Hooper topology to enhance operation bandwidth. The proposed design provides 600-mVpp differential voltage swing in driving 50-Ω output loads, 40-dB input dynamic range, 40-dB voltage gain and 8-mVpp input sensitivity. The total power consumption is 85-mW with 1.8V supply and the chip die size is 700×400-µm2.

This thesis examines the design of high-speed wireline receivers that can be adapted to a variety of operating conditions. In particular, the ability to adapt to varying received signal strengths, channel losses and operating frequencies is explored. In order to achieve this flexibility, this thesis examines several key components of such a receiver. First, a 15 Gb/s preamplifier with 10-dB gain control for the input stage of an analog front end (AFE) is presented that automatically adjusts its power consumption to suit the gain and linearity requirements of the AFE for various received signal strengths. The gain of this preamplifier, along with the amount of peaking delivered by a linear equalizer in the AFE are controlled using a new adaptation technique, which adds only a small amount of overhead to the receiver. This adaptation scheme is able to sense changes in the received signal conditions and automatically adjust the equalization and gain of the AFE in order to optimize the vertical opening of the received eye. In addition, this thesis presents the first clock multiplier with both a wide operating frequency range and the ability to transition between completely off and fully operational modes in under 10 cycles of the reference clock. This multiplier relies on the careful use of several injection-locked oscillators (ILOs) with an aggregate lock range of 55.7% of the 3.16-GHz centre frequency. The design of these ILOs was facilitated by the use of a new method for modeling the injection locking behaviour of oscillators. This model differs from existing techniques in the way that it relies on the simulated response of an oscillator to injected stimuli, instead of complex equations using quasi-physical parameters, to predict the behaviour of an ILO.

博士<br>國立交通大學<br>電信工程系所<br>96<br>There are growing demands for low-supply circuits and systems. This is especially true for system-on-a-chip application. Switching to use lower power supply voltage, digital circuits do not suffer the degradation of their performances too much. On the other hand, for analog circuits, the circuit performances are strongly affected by the low voltage supply. In addition, the chip area should also be taken into consideration to reduce large costs of advanced multi-function SOC design. Therefore, new design techniques for analog circuits are required to be developed. In this research work, novel transconductors with the applications to wireless and wireline systems are introduced. The transconductor is a basic building block for analog circuits, such as the Gm-C filter, continuous-time delta sigma modulator, voltage controlled oscillator and multiplier. Two transconductors working at high frequency is developed at first. The short channel effects in the nano-scale technology are discussed and eliminated, and the results show the high performance even at high speed operation. A wide tuning range Gm-C filter with a 5th-order Elliptic prototype for very low frequency is discussed. Through the use of switching technology, the filter can operate from the biomedical systems and the audio systems to part of wireless systems. The distortion performance maintained over the tuning range is also shown. Three multi-mode channel section filters for the Zero-IF direct conversion receiver are presented. These filters cover the wireless applications of GSM, bluetooth, cdma2000, wideband CDMA and IEEE 802.11 a/b/g/n Wireless LANs. The specific transconductors with required function are designed. Through the use of a 3th-order Butterworth prototype, the results are shown to meet the specifications of various wireless applications. Two high speed filters with a 4th-order equiripple prototype are presented. The high speed filter can be used for pulse signal systems. One is designed for the hard disk storage systems. A novel automatic tuning circuit is also implemented to account for process and temperature variations. The other is designed for the UWB system. This circuit can work well under a low supply voltage.