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Rozprawy doktorskie na temat „Wireline communication”

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Data publikacji: 6 września 2023

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1

Nilsson, Rickard. "Digital communication in wireline and wireless environments." Licentiate thesis, Luleå tekniska universitet, Signaler och system, 1999. http://urn.kb.se/resolve?urn=urn:nbn:se:ltu:diva-17330.

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This thesis consists of an introduction and five parts dealing with digital communication. Three parts address Discrete Multi-Tone modulation (DMT), a wireline form of Orthogonal Frequency Division Multiplexing (OFDM). One part addresses channel estimation in wireless OFDM and one addresses multiuser detection in wireless Direct Sequence-Code Division Multiple Access (DS- CDMA).The first part presents a new duplex method, called Zipper, for Very High bit rate Digital Subscriber Lines (VDSL). It is a duplex method that offer high flexibility and compatibility with existing services in the acces
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Huang, Deping. "Design Techniques for Timing Circuits in Wireline and Wireless Communication Systems." Diss., The University of Arizona, 2014. http://hdl.handle.net/10150/344107.

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Clock and data recovery (CDR) circuit and frequency synthesizer are two essential timing circuits in wireline and wireless communication systems, respectively. With multigigabits/s high speed links and emerging 4G wireless system widely used in communication backbone infrastructures and consumer electronic devices, effective design of CDR and frequency synthesizer has become more and more important. The advanced scaled-down CMOS process has the limitations of leakage current, low supply voltage and process variation which pose great challenge to the analog circuit design. To overcome these iss
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Lee, Sanghoon. "Foveated video compression and visual communications over wireless and wireline networks /." Digital version accessible at:, 2000. http://wwwlib.umi.com/cr/utexas/main.

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Khodayari, Moez Kambiz. "Design of CMOS Distributed Amplifiers for Broadband Wireline and Wireless Communication Applications." Thesis, University of Waterloo, 2006. http://hdl.handle.net/10012/2857.

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While the RF building blocks of narrowband system-on-chip designs have increasingly been created in CMOS during the past decade, researchers have started to look at the possibility of implementation of broadband transceivers in CMOS technology. High speed optical links with operating frequencies of up to 40 GHz and ultra wideband (UWB) wireless systems operating in 3 to 10 GHz frequency band are examples of these broadband applications. CMOS offers a low fabrication cost, and a higher level of integration compared with compound semiconductor technologies that currently claim broad
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Stevens, Irena. "Policy implications of municipal investment in Georgia's wireline broadband networks." Thesis, Georgia Institute of Technology, 2013. http://hdl.handle.net/1853/49081.

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The Community Broadband Investment Act, introduced in the Georgia legislature in 2012 and 2013 is a reflection of a broader national debate over the role of government investment in broadband infrastructure. The bill would limit local governments' ability to invest in broadband infrastructure for their communities because of arguments that government entry into the telecommunications sector crowds-out private competition, does not serve the public adequately, and lacks a comprehensive business model or best practices. A closer look at the history of utility regulation and various economic pers
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Shankar, Subramaniam. "High-speed, high-performance wireless and wireline applications using silicon-germanium BiCMOS technologies." Diss., Georgia Institute of Technology, 2013. http://hdl.handle.net/1853/48958.

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The objective of the research in this dissertation is to demonstrate the viability of using silicon-germanium (SiGe) bipolar/complementary metal-oxide semiconductor (BiCMOS) technologies in novel high-speed, high-performance wireless and wireline applications. These applications include self-healing integrated systems, W-Band phased array radar systems, and multi-gigabit wireline transceiver systems. The contributions from this research are summarized below: 1. Design of a wideband 8-18 GHz signal source with the best reported tuning range and die area combination for self-healing application
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Oliveira, Thiago Rodrigues. "The characterization of hybrid PLC-wireless and PLC channels in the frequency band between 1.7 and 100 MHz for data communication." Universidade Federal de Juiz de Fora, 2015. https://repositorio.ufjf.br/jspui/handle/ufjf/940.

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Submitted by Renata Lopes (renatasil82@gmail.com) on 2016-02-26T15:34:03Z No. of bitstreams: 1 thiagorodriguesoliveira.pdf: 11824049 bytes, checksum: ab8b7db8e1cc38ac7c875396e2379120 (MD5)<br>Rejected by Adriana Oliveira (adriana.oliveira@ufjf.edu.br), reason: Consertar sobrenome orientador on 2016-03-03T14:07:28Z (GMT)<br>Submitted by Renata Lopes (renatasil82@gmail.com) on 2016-03-03T14:41:56Z No. of bitstreams: 1 thiagorodriguesoliveira.pdf: 11824049 bytes, checksum: ab8b7db8e1cc38ac7c875396e2379120 (MD5)<br>Approved for entry into archive by Adriana Oliveira (adriana.oliveira@ufjf.edu.
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8

Lauder, David Maxwell. "Electromagnetic compatibility in wireline communications." Thesis, University of Hertfordshire, 2007. http://hdl.handle.net/2299/16518.

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This document is a thesis submitted in partial fulfilment of the requirements of the University of Hertfordshire for the degree of Doctor of Philosophy (Part Time) in 'EMC in Wire-line Communications' in the School of Electronic, Communication and Electrical Engineering at the University of Hertfordshire. It describes a programme of research into the modelling and measurement of radio frequency interference emissions from various communication networks including Power Line (Tele)communications (PLC/PLT) and Digital Subscriber Line (DSL). An introduction and literature review are followed by th
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9

Hossain, Masum. "Low-power Multi-Gb/s Wireline Communication." Thesis, 2011. http://hdl.handle.net/1807/29925.

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This thesis discusses low-power wireline receivers with particular focus on clocking circuitry and architectures. These clocking solutions can be used for a 1-D partial response channel as well as for a conventional DC coupled channel. The receiver front end for a 1-D channel requires more consideration to recover an NRZ signal from the received narrow pulses. Two possible solutions are presented. First, a full-rate detection technique is presented, where the speed is limited by the settling time of a latch circuit which has to be less than 1 UI. Second, a novel demuxing technique is introduce
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10

Dou, Qingqi. "I/O test methods in high-speed wireline communication systems." 2008. http://hdl.handle.net/2152/18345.

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The advent of serial tera-bit telecommunication and multi-gigahertz I/O interfaces is posing challenges on the semiconductor and ATE industries. There is a gap in signal integrity testing between what has been specified in serial link standards and what can be practically tested in production. A thorough characterization and a more cost-effective test of the signal integrity, such as BER, jitter, and eye margin, are critical to identify and isolate the root cause of the system degradation and to the binning in production. In this dissertation, measurement and testing schemes on signal integrit
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11

Su, Chun-Chia, and 蘇俊嘉. "Hybrid Wireline and Wireless Communication System Based on Phase Modulator." Thesis, 2014. http://ndltd.ncl.edu.tw/handle/65e2xn.

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碩士<br>國立臺北科技大學<br>光電工程系研究所<br>102<br>In the future, access networks are driving the convergence of wireline and wireless networks to offer end users greater choice, convenience and variety in an efficient way. This study proposed a radio-over-fiber (RoF) system based on phase modulation technique, integrating fiber-to-the-home (FTTH) and RoF systems, are promising for multi-service access networks. This scheme can transmit both wireline and wireless signals on a single wavelength over a single fiber, which serves these two applications simultaneously. Experimental results show that the quality
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12

Sharma, Deepak. "Linear Network Coding For Wireline And Wireless Networks." Thesis, 2007. http://hdl.handle.net/2005/638.

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Network Coding is a technique which looks beyond traditional store-and-forward approach followed by routers and switches in communication networks, and as an extension introduces maps termed as ‘local encoding kernels’ and ‘global encoding kernels’ defined for each communication link in the network. The purpose of both these maps is to define rules as to how to combine the packets input on the node to form a packet going out on an edge. The paradigm of network coding was formally and for the first time introduced by Ahlswede et al. in [1], where they also demonstrated its use in case of single-s
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13

Hung, Szu-Yao, and 洪偲僥. "Design of Fast-Settling, High-Linearity Automatic Gain Control for Broadband Wireline Communication." Thesis, 2013. http://ndltd.ncl.edu.tw/handle/71542441878861562201.

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碩士<br>國立臺灣大學<br>電子工程學研究所<br>101<br>The wireline communication has spawned a revival of interest in multimedia content distribution due to its high data bandwidth and reliability. Powerline communication (PLC) in digital home employs orthogonal frequency-division multiplexing (OFDM) modulation for high data rates in multi-path signal channels. The receiver estimates the channel’s characteristics during the reception of the preamble by the process of automatic gain control (AGC), which is an essential function in wireline receivers to adjust sensitivity to incoming signal strength. This work f
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14

Shen, Kun-Jui, and 沈坤叡. "A 20-32Gb/s Transmitter System for Wireline Communication Testing in CMOS Technology." Thesis, 2017. http://ndltd.ncl.edu.tw/handle/m8469y.

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碩士<br>國立臺灣大學<br>電子工程學研究所<br>105<br>This thesis presents a wide-rage wireline transmitter system in 40 nm CMOS technology. It can provide the receiver for testing with different standard of wireline communication such as 25 Gb/s、28 Gb/s and 32 Gb/s. It can also generate different types of PRBS data sequence：27-1、215-1、223-1、231-1 and four types of error injection rate to data sequence：10-3, 10-6, 10-9, and 0. With a built-in wide-rage phase-locked Loop, it can regard as a clock source of the system, which can be operated up to 32 Gb/s. This wireline transmitter system includes multiplexers, fl
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15

Ganesan, Abhinav. "Precoding for Interference Management in Wireless and Wireline Networks." Thesis, 2014. http://hdl.handle.net/2005/3190.

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Multiple users compete for a common resource like bandwidth to communicate data in interference networks. Existing approaches in dealing with interference limit the rate of communication due to paucity of shared resources. This limitation in the rate gets more glaring as the number of users in the network increases. For example, existing wireless systems either choose to orthogonalize the users (for example, Frequency Division Multiple Access (FDMA) systems or Code Division Multiple Access (CDMA) systems) or treat interference as Gaussian noise at the receivers. It is well known that these app
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16

Vijayvaradharaj, T. M. "Network Coding for Wirless Relaying and Wireline Networks." Thesis, 2014. http://etd.iisc.ernet.in/handle/2005/2892.

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Network coding has emerged as an attractive alternative to routing because of the through put improvement it provides by reducing the number of channel uses. In a wireless scenario, in addition, further improvement can be obtained through Physical layer Network Coding (PNC), a technique in which nodes are allowed to transmit simultaneously, instead of transmitting in orthogonal slots. In this thesis, the design and analysis of network coding schemes are considered, for wireless two-way relaying, multi-user Multiple Access Relay Channel (MARC) and wireline networks. In a wireless two-way relay
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17

Jin, Jun-De, and 金俊德. "Microwave CMOS Integrated Amplifiers for Wireless/Wireline Communications." Thesis, 2008. http://ndltd.ncl.edu.tw/handle/17724076327544554783.

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博士<br>國立清華大學<br>電子工程研究所<br>97<br>This study proposed new circuit design techniques to achieve high-performance CMOS integrated amplifiers for wireless/line communications at microwave frequencies. The design concepts were demonstrated by one narrowband and one broadband amplifiers, which were both realized in the standard 0.18-μm RF CMOS technology. The measured results presented superior performances compared with other published works using a similar or even more advanced CMOS technology. The designed narrowband amplifier is a 24-GHz balanced amplifier (BA) with a gain up to 45 dB. An effect
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18

Kao, Min-Sheng, and 高旻聖. "CMOS Analog Front-end Transceiver IC for Wireline Communications." Thesis, 2011. http://ndltd.ncl.edu.tw/handle/68305604504950596777.

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博士<br>國立清華大學<br>通訊工程研究所<br>99<br>This study proposes several circuit design techniques to achieve high performance CMOS transceiver chipset for wire-line communication. The circuit concepts are demonstrated by a 20-Gb/s CMOS 0.13-μm laser/modulator driver design and a 10-Gb/s CMOS 0.18-μm limiting amplifier design. The performance evaluation are as good as the advanced expensive III-V compound technology and the fabricated CMOS circuits are suitable for further integration with SERDES, CDR, and CODEC ICs for wire-line communication due to the small die size and low power consumption. The propo
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19

Dunwell, Dustin. "Adaptive Receivers for High-speed Wireline Links." Thesis, 2013. http://hdl.handle.net/1807/35810.

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This thesis examines the design of high-speed wireline receivers that can be adapted to a variety of operating conditions. In particular, the ability to adapt to varying received signal strengths, channel losses and operating frequencies is explored. In order to achieve this flexibility, this thesis examines several key components of such a receiver. First, a 15 Gb/s preamplifier with 10-dB gain control for the input stage of an analog front end (AFE) is presented that automatically adjusts its power consumption to suit the gain and linearity requirements of the AFE for various received signal
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20

Lo, Tien-Yu, and 羅天佑. "High Performance CMOS Transconductors and Gm-C Filters for Wireless Communications and Wireline Systems." Thesis, 2007. http://ndltd.ncl.edu.tw/handle/89842446152267168562.

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博士<br>國立交通大學<br>電信工程系所<br>96<br>There are growing demands for low-supply circuits and systems. This is especially true for system-on-a-chip application. Switching to use lower power supply voltage, digital circuits do not suffer the degradation of their performances too much. On the other hand, for analog circuits, the circuit performances are strongly affected by the low voltage supply. In addition, the chip area should also be taken into consideration to reduce large costs of advanced multi-function SOC design. Therefore, new design techniques for analog circuits are required to be developed
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