Rozprawy doktorskie na temat „VERILOG IMPLEMENTATION”
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Skärpe, Anders. "Implementation of an SDR in Verilog". Thesis, Linköpings universitet, Kommunikationssystem, 2016. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-132325.
Pełny tekst źródłaChen, Adam Y. (Adam Yu-Chih). "Implementation of the Intel 486 SX microprocessor in Verilog hardware description language". Thesis, Massachusetts Institute of Technology, 1993. http://hdl.handle.net/1721.1/79470.
Pełny tekst źródłaRAGHURAMAN, SRINIVASAN. "IMPLEMENTATION AND PERFORMANCE MEASUREMENTS OF A VERILOG-AMS MODEL OF BSIM3v3.3 TRANSISTOR". University of Cincinnati / OhioLINK, 2006. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1163711277.
Pełny tekst źródłaNARAYANAN, SHRUTHI. "HARDWARE IMPLEMENTATION OF GENETIC ALGORITHM MODULES FOR INTELLIGENT SYSTEMS". University of Cincinnati / OhioLINK, 2005. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1122909070.
Pełny tekst źródłaKasarabada, Yasaswy. "A Verilog Description and Efficient Hardware Implementation of the Baillie-PSW Primality Test". University of Cincinnati / OhioLINK, 2016. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1471347471.
Pełny tekst źródłaPark, Sungho. "A verilog-hdl implementation of virtual channels in a network-on-chip router". [College Station, Tex. : Texas A&M University, 2008. http://hdl.handle.net/1969.1/ETD-TAMU-2890.
Pełny tekst źródłaSampath, Kumar Santhiya. "Implementation of Low-Bit Rate Audio Codec, Codec2, in Verilog on Modern FPGAS". Miami University / OhioLINK, 2020. http://rave.ohiolink.edu/etdc/view?acc_num=miami158819886466373.
Pełny tekst źródłaPampana, Srilaxmi. "FPGA BASED IMPLEMENTATION OF A POSITION ESTIMATOR FOR CONTROLLING A SWITCHED RELUCTANCE MOTOR". UKnowledge, 2004. http://uknowledge.uky.edu/gradschool_theses/254.
Pełny tekst źródłaThakur, Ravi Bhushan. "Low power design implementation of a signal acquisition module". Thesis, Kansas State University, 2010. http://hdl.handle.net/2097/4617.
Pełny tekst źródłaDepartment of Electrical and Computer Engineering
Don M. Gruenbacher
As semiconductor technologies advance, the smallest feature sizes that can be fabricated get smaller. This has led to the development of high density FPGAs capable of supporting high clock speeds, which allows for the implementation of larger more complex designs on a single chip. Over the past decade the technology market has shifted toward mobile devices with low power consumption at or near the top of design considerations. By reducing power consumption in FPGAs we can achieve greater reliability, lower cooling cost, simpler power supply and delivery, and longer battery life. In this thesis, FPGA technology is discussed for the design and commercial implementation of low power systems as compared to ASICs or microprocessors, and a few techniques are suggested for lowering power consumption in FPGA designs. The objective of this research is to implement some of these approaches and attempt to design a low power signal acquisition module. Designing for low power consumption without compromising performance requires a power-efficient FPGA architecture and good design practices to leverage the architectural features. With various power conservation techniques suggested for every stage of the FPGA design flow, the following approach was used in the design process implementation: the switching activity is addressed in the design entry, and synthesis level and software tools are utilized to get an initial estimate of and optimize the design’s power consumption. Finally, the device choice is made based on its features that will enhance the optimization achieved in the previous stages; it is configured and real time board level power measurements are made to verify the implementation’s efficacy
Gumus, Rasit. "Implementation Of A Risc Microcontroller Using Fpga". Master's thesis, METU, 2005. http://etd.lib.metu.edu.tr/upload/2/12606694/index.pdf.
Pełny tekst źródłaNicodemus, Joshua. "An implementation of the usf/ calvo model in verilog-a to enforce charge conservation in applicable fet models". [Tampa, Fla.] : University of South Florida, 2005. http://purl.fcla.edu/fcla/etd/SFE0001107.
Pełny tekst źródłaJin, Chuan. "Test implementation of embedded cores-based sequential circuits using Verilog HDL under Altera MAX Plus II development environment". Thesis, University of Ottawa (Canada), 2004. http://hdl.handle.net/10393/26669.
Pełny tekst źródłaKora, Venugopal Rishvanth. "FPGA BASED PARALLEL IMPLEMENTATION OF STACKED ERROR DIFFUSION ALGORITHM". UKnowledge, 2010. http://uknowledge.uky.edu/gradschool_theses/40.
Pełny tekst źródłaStröm, Marcus. "System Design of RF Receiver and Digital Implementation of Control Logic". Thesis, Linköping University, Department of Science and Technology, 2003. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-1848.
Pełny tekst źródłaThis report is the outcome of a thesis work done at Linköpings University, campus Norrköping. The thesis work was part of the development of a RF transceiver chip for implantable medical applications. The development was done in cooperation with Zarlink Semiconductor AB, located in Järfälla, Stockholm.
The transceiver is divided into three main blocks, which are the wakeup block, the MAC block and the RF block. The wakeup block is always operating and is awaiting a wakeup request in the 2,45GHz ISM-band. The RF-block is operating in the 400MHz ISM-band and is powered up after wakeup The MAC is the controller of the whole chip. All three blocks in the transceiver structure should be integrated on the same chip, using TSMC 0,18µm process design kit for CMOS (Mixed Signal /RF).
The purpose of the thesis work was to develop the wakeup circuit for the transceiver. The main purpose was to develop the digital control logic in the circuitry, using RTL-coding (mainly VHDL) but the thesis work also included a system analysis of the whole wakeup block, including the front-end, for getting a better overview and understanding of the project.
A complete data packet or protocol for the wakeup message on 2,45GHz, is defined in the report and is one of the results of the project. The packet was developed continuously during progress in the project. Once the data packet was defined the incoming RF stage could be investigated. The final proposal to a complete system design for the wakeup block in the RF transceiver is also one of the outcomes of the project. The front-end consists mainly of a LNA, a simple detector and a special decoder. Since the total power consumption on the wakeup block was set to 200nA, this had to be taken under consideration continuously. There was an intention not to have an internal clock signal or oscillator available in the digital part (for keeping the power consumption down). The solution to this was a self-clocking method used on the incoming RF signal. A special decoder distinguishes the incoming RF signal concerning the burst lengths in time. The decoder consists of a RC net that is uploaded and then has an output of 1, if the burst length is long enough and vice versa.
When it was decided to use a LNA in the front-end, it was found that it could not be active continuously, because of the requirements on low power consumption. The solution to this was to use a strobe signal for the complete front-end, which activates it. This strobe signal was extracted in the digital logic. The strobe signal has a specific duty cycle, depending on the time factors in the detector and in the decoder in the front-end. The total strobing time is in the implemented solution 250µs every 0,5s.
The digital implementation of the control logic in the wakeupblock was made in VHDL (source code) and Verilog (testbenches). The source code was synthesized against the component library for the process 0,18µm from TSMC, which is a mixed/signal and RF process. The netlist from the synthesizing was stored as a Verilog file and simulated together with the testbenches using the simulator Verilog-XL. The results from the simulations were examined and reviewed in the program Simvison from Cadence. The result was then verified during a pre-layout review together with colleagues at Zarlink Semiconductor AB. During the implementation phase a Design report was written continuously and then used for the pre-layout review. Extracts (source code and testbench) from this document can be found as appendixes to the report.
Shen, Jue. "Quantization Effects Analysis on Phase Noise and Implementation of ALL Digital Phase Locked-Loop". Thesis, KTH, Skolan för informations- och kommunikationsteknik (ICT), 2011. http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-37212.
Pełny tekst źródłaKay, James T. "Development of future course content requirements supporting the Department of Defense's Internet Protocol verison 6 transition and implementation". Thesis, Monterey, Calif. : Springfield, Va. : Naval Postgraduate School ; Available from National Technical Information Service, 2006. http://library.nps.navy.mil/uhtbin/hyperion/06Jun%5FKay.pdf.
Pełny tekst źródłaThesis Advisor(s): Geoffrey Xie, John Gibson. "June 2006." Includes bibliographical references (p. 47-48). Also available in print.
Bayer, Tomáš. "Návrh hardwarového šifrovacího modulu". Master's thesis, Vysoké učení technické v Brně. Fakulta elektrotechniky a komunikačních technologií, 2009. http://www.nusl.cz/ntk/nusl-218076.
Pełny tekst źródłaSATYAN. "VERILOG IMPLEMENTATION OF DIGITAL IMAGE WATERMARKING". Thesis, 2017. http://dspace.dtu.ac.in:8080/jspui/handle/repository/16024.
Pełny tekst źródłaFerreira, Carlos Alberto Pereira. "Verilog implementation of the VESA DSC compression algorithm". Master's thesis, 2016. https://hdl.handle.net/10216/89000.
Pełny tekst źródłaFerreira, Carlos Alberto Pereira. "Verilog implementation of the VESA DSC compression algorithm". Dissertação, 2016. https://hdl.handle.net/10216/89000.
Pełny tekst źródłaWU, TAI-YU, i 吳岱祐. "Implementation of SDRAM controller By Verilog Hardware Description Language". Thesis, 2015. http://ndltd.ncl.edu.tw/handle/crfhnk.
Pełny tekst źródła國立臺北科技大學
電機工程研究所
103
This thesis focuses on the extension of SRAM(Static Random Access Memory). Firstly, We propose a SDRAM controller to instead of SRAM extension on the ARM system. This is the SRAM extension in replaced with the SDRAM controller which is implemented with SDRAM. Secondly, the Modelsim software is selected to complete the simulation of SDRAM controller. The operating frequence of 166MHz and the operating voltage of 3.3 voltage are considered for SDRAM input/output interface. Notify that the SDRAM can not work in precharge time. This thesis provides a Bank method to resolve this problem by accessing a temporary memory in the precharge time. After the precharge ,the missed data will be recover in SDRAM. The Verilog HDL is used not only to complete the simution but also to verify the function of SDRAM. Finally, the DDR SDRAM specification will be confirmed that the proposed SDRAM controller works correctly.
Shiao, Yat-Tai, i 蕭義泰. "An Implementation of Space Time Block Codes by Verilog HDL". Thesis, 2005. http://ndltd.ncl.edu.tw/handle/39828380361265411230.
Pełny tekst źródła中原大學
電機工程研究所
93
Foschini,Gans and Telatar proved that multiple input multiple output can introduce spatial diversity and increased information capacity. These results have motivated a new area in error correcting codes . The Space Time Block Codes (STBC) proposed by Tarkoh .Space-Time Coding (STC) schemes can combine the channel code design and the use of multiple transmit antennas . The Verilog language be Gateway Design Automation company build up since 1994 , Verilog language already become a standard hardware description language, Popularly use in VLSI and Digital System Design . Otherwise, Verilog language was first language can support any mix design level , At the same time provide Switch level、Logic level、Register Transfer Level and more than High-level describe. The Verilog simulation environment to provide a powerful combine environment to improve Digital Design step and test process. In our thesis, We will simply introduce Space Time Block Codes and Verilog HDL, we firstly use Matlab program to verify the correctness of our design ,After write Verilog HDL code to describe its function, Let the function can implement on chip.
Tsuei, Jrchiuan, i 崔致銓. "Implementation of FH 16FSK Communication Systems Based on FPGA Verilog". Thesis, 2012. http://ndltd.ncl.edu.tw/handle/77946157374867767230.
Pełny tekst źródła中華科技大學
電子工程研究所碩士班
100
This paper simulates and implements the Frequency-Hopping (FH) 16 Frequency Shift Keying (16FSK) communication system by Xilinx Integrated Synthesis Environment (ISE) platform. At the transmitter, the FH signal is generated pseudo-randomly, and then modulated by the same Quadrature Frequency Shift Keying (QFSK) four times. Finally, the simulated FH signal is transmitted by frequency mixing for computing. The signal going to the receiver goes into the narrow-band pass filter, in order to retain the low frequency signal and to filter out the high-frequency signal. After that, the filtered signal is then converted back to binary signal using a non-coherent FSK demodulator. During the simulation and implementation process, the system is designed using a Verilog hardware description language, and then processed by a simulation software- Xilinx ISim. Finally, the system is written into the Xilinx Spartan-6 FPGA SP605 simulation board for implementation.
Liao, Yi-Bo, i 廖翊博. "Implementation of Temperature-Based Phase Change Memory Model Using Verilog-A". Thesis, 2008. http://ndltd.ncl.edu.tw/handle/06799417656002571077.
Pełny tekst źródła國立宜蘭大學
電子工程學系碩士班
96
Non-volatile memory (NVM) has been very popular for data storage. The continuous scaling of MOSFET is a challenging task due to physical limitations, so developing a new memory device is important. The phase change memory (PCM) has been a promising candidate for next generation memory device. In this thesis, we developed PCM SPICE compact model using Verilog-A. There are two phase states of the PCM which can store the digital data. Different current pulses can generate heat levels to change phase of the PCM. The physical compact model discussed in this thesis includes the theories of Joule heating, thermal dissIpation and crystalline fraction, and it is accurate and predictive. As PCM technology is emerging, the predictive compact model can expedite the novel technology development.
P, S. Arun Kumar. "Implementation of Image Compression Algorithm using Verilog with Area, Power and Timing Constraints". Thesis, 2009. http://ethesis.nitrkl.ac.in/1358/1/Thesis.pdf.
Pełny tekst źródłaAlam, Md Monjur. "FPGA Based Binary Heap Implementation: With an Application to Web Based Anomaly Prioritization". 2015. http://scholarworks.gsu.edu/cs_theses/80.
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