Artykuły w czasopismach na temat „VEDIC MULTIPLIERS”
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Eshack, Ansiya, i S. Krishnakumar. "Pipelined vedic multiplier with manifold adder complexity levels". International Journal of Electrical and Computer Engineering (IJECE) 10, nr 3 (1.06.2020): 2951. http://dx.doi.org/10.11591/ijece.v10i3.pp2951-2958.
Pełny tekst źródłaKhubnani, Rashi, Tarunika Sharma i Chitirala Subramanyam. "Applications of Vedic multiplier - A Review". Journal of Physics: Conference Series 2225, nr 1 (1.03.2022): 012003. http://dx.doi.org/10.1088/1742-6596/2225/1/012003.
Pełny tekst źródłaRashno, Meysam, Majid Haghparast i Mohammad Mosleh. "A new design of a low-power reversible Vedic multiplier". International Journal of Quantum Information 18, nr 03 (kwiecień 2020): 2050002. http://dx.doi.org/10.1142/s0219749920500021.
Pełny tekst źródłaBhairannawar, Satish s., Raja K B, Venugopal K R i L. M. Patnaik. "EFFICIENT FPGA BASED MATRIX MULTIPLICATION USING MUX AND VEDIC MULTIPLIER". INTERNATIONAL JOURNAL OF COMPUTERS & TECHNOLOGY 12, nr 5 (30.01.2014): 3452–63. http://dx.doi.org/10.24297/ijct.v12i5.2915.
Pełny tekst źródłaNandha Kumar, P. "Design of Accuracy Based Fixed-Width Booth Multipliers Using Data Scaling Technology". Asian Journal of Electrical Sciences 11, nr 2 (15.12.2022): 24–30. http://dx.doi.org/10.51983/ajes-2022.11.2.3524.
Pełny tekst źródłaCVS, Chaitanya, Sundaresan C, P. R. Venkateswaran, Keerthana Prasad i V. Siva Ramakrishna. "Design of High-Speed Multiplier Architecture Based on Vedic Mathematics". International Journal of Engineering & Technology 7, nr 2.4 (10.03.2018): 105. http://dx.doi.org/10.14419/ijet.v7i2.4.11228.
Pełny tekst źródłaKuruvilla, Siya Susan, Stephani Sunil, Abisha Susan Alichan i Abraham K. Thomas. "Comparison of Vedic Multiplier Implementation Using Gate Diffusion Input and Modified Gate Diffusion Input Techniques". Journal of Signal Processing 8, nr 2 (22.06.2022): 1–5. http://dx.doi.org/10.46610/josp.2022.v08i02.001.
Pełny tekst źródłaCVS, Chaitanya, Sundaresan C i P. R Venkateswaran. "ASIC design of low power-delay product carry pre-computation based multiplier". Indonesian Journal of Electrical Engineering and Computer Science 13, nr 2 (1.02.2019): 845. http://dx.doi.org/10.11591/ijeecs.v13.i2.pp845-852.
Pełny tekst źródłaGanjikunta, Ganesh Kumar, Sibghatullah I. Khan i M. Mahaboob Basha. "A High-Performance Signed-Unsigned Multiplier Using Vedic Mathematics". Journal of Low Power Electronics 15, nr 3 (1.09.2019): 302–8. http://dx.doi.org/10.1166/jolpe.2019.1616.
Pełny tekst źródłaProf. Parvaneh Basaligheh. "Design and Implementation of High Speed Vedic Multiplier in SPARTAN 3 FPGA Device". International Journal of New Practices in Management and Engineering 6, nr 01 (31.03.2017): 14–19. http://dx.doi.org/10.17762/ijnpme.v6i01.51.
Pełny tekst źródłaProf. Sharayu Waghmare. "Vedic Multiplier Implementation for High Speed Factorial Computation". International Journal of New Practices in Management and Engineering 1, nr 04 (31.12.2012): 01–06. http://dx.doi.org/10.17762/ijnpme.v1i04.8.
Pełny tekst źródłaC, Pradeepa S., Gowri G. Bennur, Hruthika G, Adithya M i Acharya Vinay Vasudeva. "Design and VLSI Implementation of Vedic Multiplier using 45nm Technology". International Journal for Research in Applied Science and Engineering Technology 11, nr 5 (31.05.2023): 964–68. http://dx.doi.org/10.22214/ijraset.2023.51676.
Pełny tekst źródłaJoshi, Shubhangi M. "Modified Vedic Multipliers: A Review". International Journal of Advanced Research in Computer Science and Software Engineering 7, nr 5 (30.05.2017): 421–26. http://dx.doi.org/10.23956/ijarcsse/sv7i5/0255.
Pełny tekst źródłaSafoev, Nuriddin, i Jun-Cheol Jeon. "Design and Evaluation of Cell Interaction Based Vedic Multiplier Using Quantum-Dot Cellular Automata". Electronics 9, nr 6 (23.06.2020): 1036. http://dx.doi.org/10.3390/electronics9061036.
Pełny tekst źródłaParadhasaradhi, Damarla, Bharinala Haridhar, A. V. Sreekanth Reddy, Dudipalli Sri Charan i Atyam Lekhaz. "Implementation of Fast Convolution using Robust Vedic Multiplier of Radix-2". International Journal of Engineering & Technology 7, nr 2.7 (18.03.2018): 626. http://dx.doi.org/10.14419/ijet.v7i2.7.10895.
Pełny tekst źródłaEt. al., Srilakshmi Kaza,. "Performance Analysis of Adiabatic Vedic Multipliers". Turkish Journal of Computer and Mathematics Education (TURCOMAT) 12, nr 5 (11.04.2021): 1429–35. http://dx.doi.org/10.17762/turcomat.v12i5.2039.
Pełny tekst źródłaPradhan, Manoranjan, i Rutuparna Panda. "Speed Comparison of 16x16 Vedic Multipliers". International Journal of Computer Applications 21, nr 6 (31.05.2011): "12"—"19". http://dx.doi.org/10.5120/2516-3417.
Pełny tekst źródłaEshack, Ansiya, i S. Krishnakumar. "Reversible logic in pipelined low power vedic multiplier". Indonesian Journal of Electrical Engineering and Computer Science 16, nr 3 (1.12.2019): 1265. http://dx.doi.org/10.11591/ijeecs.v16.i3.pp1265-1272.
Pełny tekst źródłaSharma, Tarunika, Rashi Khubnani i Chitiralla Subramanyam. "Study of mathematics through indian veda’s : A review". Journal of Physics: Conference Series 2332, nr 1 (1.09.2022): 012006. http://dx.doi.org/10.1088/1742-6596/2332/1/012006.
Pełny tekst źródłaGowreesrinivas, K. V., Sabbavarapu Srinivas i Punniakodi Samundiswary. "FPGA Implementation of a Resource Efficient Vedic Multiplier using SPST Adders". Engineering, Technology & Applied Science Research 13, nr 3 (2.06.2023): 10698–702. http://dx.doi.org/10.48084/etasr.5797.
Pełny tekst źródłaG., Suresh. "Approximate Compressors based Inexact Vedic Dadda Multipliers". HELIX 8, nr 1 (1.01.2018): 2683–90. http://dx.doi.org/10.29042/2018-2683-2690.
Pełny tekst źródłaHari Kishore, K., Fazal Noorbasha, Katta Sandeep, D. N. V. Bhupesh, SK Khadar Imran i K. Sowmya. "Linear convolution using UT Vedic multiplier". International Journal of Engineering & Technology 7, nr 2.8 (19.03.2018): 409. http://dx.doi.org/10.14419/ijet.v7i2.8.10471.
Pełny tekst źródłaDeokate, Rajesh. "A Review on IEEE-754 Standard Floating Point Multiplier using Vedic Mathematics". International Journal for Research in Applied Science and Engineering Technology 9, nr VI (20.06.2021): 1300–1303. http://dx.doi.org/10.22214/ijraset.2021.35242.
Pełny tekst źródłaMukkara, Lakshmi kiran, i K. Venkata Ramanaiah. "Neuronal Logic gates Realization using CSD algorithm". International Journal of Reconfigurable and Embedded Systems (IJRES) 8, nr 2 (1.07.2019): 145. http://dx.doi.org/10.11591/ijres.v8.i2.pp145-150.
Pełny tekst źródłaGaur, F. Nidhi, S. Anu Mehra i T. Pradeep Kumar. "Power and Area Efficient Vedic Multipliers Using Modified CSLA Architectures for DSP". Journal of Advanced Research in Dynamical and Control Systems 11, nr 10 (31.10.2019): 44–51. http://dx.doi.org/10.5373/jardcs/v11i10/20193004.
Pełny tekst źródłaMOHANA KANNAN, LOGANATHAN, i DHANASKODI DEEPA. "LOW POWER VERY LARGE SCALE INTEGRATION (VLSI) DESIGN OF FINITE IMPULSE RESPONSE (FIR) FILTER FOR BIOMEDICAL IMAGING APPLICATION". DYNA 96, nr 5 (1.09.2021): 505–11. http://dx.doi.org/10.6036/10214.
Pełny tekst źródłaPoornima, Y., i M. Kamalanathan. "Design of Low Power Vedic Multiplier Based Reconfigurable Fir Filter for DSP Applications". International Journal of Advance Research and Innovation 7, nr 2 (2019): 57–60. http://dx.doi.org/10.51976/ijari.721908.
Pełny tekst źródłaSreelakshmi, G., Kaleem Fatima i B. K. Madhavi. "Efficient Realization of Vinculum Vedic BCD Multipliers for High Speed Applications". Circuits and Systems 09, nr 06 (2018): 87–99. http://dx.doi.org/10.4236/cs.2018.96009.
Pełny tekst źródłaP. VINAY, MALLIK, i HEMACHANDRA G. "Design of 2D-DCT and Quantization Using Dadda and Vedic Multipliers". i-manager's Journal on Digital Signal Processing 4, nr 3 (2016): 21. http://dx.doi.org/10.26634/jdp.4.3.8144.
Pełny tekst źródłaAnjana, S., C. Pradeep i Philip Samuel. "Synthesize of High Speed Floating-point Multipliers Based on Vedic Mathematics". Procedia Computer Science 46 (2015): 1294–302. http://dx.doi.org/10.1016/j.procs.2015.01.054.
Pełny tekst źródłaSavadi, Anuradha, Raju Yanamshetti i Shewta Biradar. "Design and Implementation of 64 Bit IIR Filters Using Vedic Multipliers". Procedia Computer Science 85 (2016): 790–97. http://dx.doi.org/10.1016/j.procs.2016.05.267.
Pełny tekst źródłaMehra, Anu, Vinay Verma, Rana Majumdar, Nidhi Gaur, Alok Kumar, Chanda Pandey i Ansh Awasthi. "Comparative analysis of different Vedic algorithms for 8 × 8 binary multipliers". International Journal of Industrial and Systems Engineering 33, nr 2 (2019): 129. http://dx.doi.org/10.1504/ijise.2019.10024258.
Pełny tekst źródłaMehra, Anu, Vinay Verma, Rana Majumdar, Nidhi Gaur, Alok Kumar, Ansh Awasthi i Chanda Pandey. "Comparative analysis of different Vedic algorithms for 8 × 8 binary multipliers". International Journal of Industrial and Systems Engineering 33, nr 2 (2019): 129. http://dx.doi.org/10.1504/ijise.2019.102466.
Pełny tekst źródłaS., Nagaraj. "Design and Analysis of 8-bit Array, Carry Save Array, Braun, Wallace Tree and Vedic Multipliers". International Journal of Psychosocial Rehabilitation 24, nr 3 (30.03.2020): 2687–97. http://dx.doi.org/10.37200/ijpr/v24i3/pr2020305.
Pełny tekst źródłaBhargavi, Sandugari. "Design and Implementation of Area Efficient BIST Based Vedic and Wallace Tree Multipliers on FPGA". International Journal for Research in Applied Science and Engineering Technology 7, nr 4 (30.04.2019): 3650–55. http://dx.doi.org/10.22214/ijraset.2019.4612.
Pełny tekst źródłaFatima, Nashrah, Taha Tanveer i Brahmi Shrman. "Implementation for Minimization of Computation Time of Partial Products for Designing Multipliers using Tabulated Vedic Mathematics". International Journal of Computer Applications 128, nr 10 (15.10.2015): 1–5. http://dx.doi.org/10.5120/ijca2015906638.
Pełny tekst źródłaNaveen, R. "Design and Analysis of Low Power Full Adders and 4*4 Vedic Multipliers Based on Urdhva Triyagbhyam". Asian Journal of Research in Social Sciences and Humanities 6, nr 7 (2016): 950. http://dx.doi.org/10.5958/2249-7315.2016.00479.2.
Pełny tekst źródłaSM, Vijaya, i Suresh K. "An Efficient Design Approach of ROI Based DWT Using Vedic and Wallace Tree Multiplier on FPGA Platform". International Journal of Electrical and Computer Engineering (IJECE) 9, nr 4 (1.08.2019): 2433. http://dx.doi.org/10.11591/ijece.v9i4.pp2433-2442.
Pełny tekst źródłaSaraswathi, N., Lokesh Modi i Aatish Nair. "Complex Number Vedic Multiplier and its Implementation in a Filter". International Journal of Engineering & Technology 7, nr 2.24 (25.04.2018): 336. http://dx.doi.org/10.14419/ijet.v7i2.24.12078.
Pełny tekst źródłaJhamb, Mansi, i Manoj Kumar. "Optimized vedic multiplier using low power 13T hybrid full adder". Journal of Information and Optimization Sciences 44, nr 4 (2023): 675–87. http://dx.doi.org/10.47974/jios-1222.
Pełny tekst źródłaSharma, Vaishali. "Design, Implementation & Performance of Vedic Multiplier Based on Look Ahead Carry Adder for Different Bit Lengths". International Journal for Research in Applied Science and Engineering Technology 10, nr 1 (31.01.2022): 24–30. http://dx.doi.org/10.22214/ijraset.2022.39759.
Pełny tekst źródłaKunchigik, Vaijyanath, Linganagouda Kulkarni i Subhash Kulkarni. "Pipelined Vedic-Array Multiplier Architecture". International Journal of Image, Graphics and Signal Processing 6, nr 6 (8.05.2014): 58–64. http://dx.doi.org/10.5815/ijigsp.2014.06.08.
Pełny tekst źródłaKivi Sona, M., i V. Somasundaram. "Vedic Multiplier Implementation in VLSI". Materials Today: Proceedings 24 (2020): 2219–30. http://dx.doi.org/10.1016/j.matpr.2020.03.748.
Pełny tekst źródłaPrabhu, E., H. Mangalam i P. R. Gokul. "A Delay Efficient Vedic Multiplier". Proceedings of the National Academy of Sciences, India Section A: Physical Sciences 89, nr 2 (9.02.2018): 257–68. http://dx.doi.org/10.1007/s40010-017-0464-4.
Pełny tekst źródłaKumar, M. Siva, Sanath Kumar Tulasi, N. Srinivasulu, Vijaya Lakshmi Bandi i K. Hari Kishore. "Bit wise and delay of vedic multiplier". International Journal of Engineering & Technology 7, nr 1.5 (31.12.2017): 26. http://dx.doi.org/10.14419/ijet.v7i1.5.9117.
Pełny tekst źródłaYadav, Jatin, Anupam Kumar, Shaik Shareef, Sandeep Bansal i Navjot Rathour. "Comparative Analysis of Vedic Multiplier using Various Adder Architectures". Journal of Physics: Conference Series 2327, nr 1 (1.08.2022): 012022. http://dx.doi.org/10.1088/1742-6596/2327/1/012022.
Pełny tekst źródłaBhavani, M., M. Siva Kumar i K. Srinivas Rao. "Delay Comparison for 16x16 Vedic Multiplier Using RCA and CLA". International Journal of Electrical and Computer Engineering (IJECE) 6, nr 3 (1.06.2016): 1205. http://dx.doi.org/10.11591/ijece.v6i3.9457.
Pełny tekst źródłaBhavani, M., M. Siva Kumar i K. Srinivas Rao. "Delay Comparison for 16x16 Vedic Multiplier Using RCA and CLA". International Journal of Electrical and Computer Engineering (IJECE) 6, nr 3 (1.06.2016): 1205. http://dx.doi.org/10.11591/ijece.v6i3.pp1205-1212.
Pełny tekst źródłaPrasad, M. V. Tejendra. "Development and Realization of a 4x4 Vedic Multiplier Utilizing Cadence Platform". Journal of VLSI Design and Signal Processing 9, nr 2 (4.08.2023): 39–51. http://dx.doi.org/10.46610/jovdsp.2023.v09i02.004.
Pełny tekst źródłaManikrao, Kaustubh, i Mahesh Shrikant. "Analysis of Array Multiplier and Vedic Multiplier using Xilinx". Communications on Applied Electronics 5, nr 1 (24.05.2016): 13–16. http://dx.doi.org/10.5120/cae2016652140.
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