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Artykuły w czasopismach na temat "VEDIC MULTIPLIERS"
Eshack, Ansiya, i S. Krishnakumar. "Pipelined vedic multiplier with manifold adder complexity levels". International Journal of Electrical and Computer Engineering (IJECE) 10, nr 3 (1.06.2020): 2951. http://dx.doi.org/10.11591/ijece.v10i3.pp2951-2958.
Pełny tekst źródłaKhubnani, Rashi, Tarunika Sharma i Chitirala Subramanyam. "Applications of Vedic multiplier - A Review". Journal of Physics: Conference Series 2225, nr 1 (1.03.2022): 012003. http://dx.doi.org/10.1088/1742-6596/2225/1/012003.
Pełny tekst źródłaRashno, Meysam, Majid Haghparast i Mohammad Mosleh. "A new design of a low-power reversible Vedic multiplier". International Journal of Quantum Information 18, nr 03 (kwiecień 2020): 2050002. http://dx.doi.org/10.1142/s0219749920500021.
Pełny tekst źródłaBhairannawar, Satish s., Raja K B, Venugopal K R i L. M. Patnaik. "EFFICIENT FPGA BASED MATRIX MULTIPLICATION USING MUX AND VEDIC MULTIPLIER". INTERNATIONAL JOURNAL OF COMPUTERS & TECHNOLOGY 12, nr 5 (30.01.2014): 3452–63. http://dx.doi.org/10.24297/ijct.v12i5.2915.
Pełny tekst źródłaNandha Kumar, P. "Design of Accuracy Based Fixed-Width Booth Multipliers Using Data Scaling Technology". Asian Journal of Electrical Sciences 11, nr 2 (15.12.2022): 24–30. http://dx.doi.org/10.51983/ajes-2022.11.2.3524.
Pełny tekst źródłaCVS, Chaitanya, Sundaresan C, P. R. Venkateswaran, Keerthana Prasad i V. Siva Ramakrishna. "Design of High-Speed Multiplier Architecture Based on Vedic Mathematics". International Journal of Engineering & Technology 7, nr 2.4 (10.03.2018): 105. http://dx.doi.org/10.14419/ijet.v7i2.4.11228.
Pełny tekst źródłaKuruvilla, Siya Susan, Stephani Sunil, Abisha Susan Alichan i Abraham K. Thomas. "Comparison of Vedic Multiplier Implementation Using Gate Diffusion Input and Modified Gate Diffusion Input Techniques". Journal of Signal Processing 8, nr 2 (22.06.2022): 1–5. http://dx.doi.org/10.46610/josp.2022.v08i02.001.
Pełny tekst źródłaCVS, Chaitanya, Sundaresan C i P. R Venkateswaran. "ASIC design of low power-delay product carry pre-computation based multiplier". Indonesian Journal of Electrical Engineering and Computer Science 13, nr 2 (1.02.2019): 845. http://dx.doi.org/10.11591/ijeecs.v13.i2.pp845-852.
Pełny tekst źródłaGanjikunta, Ganesh Kumar, Sibghatullah I. Khan i M. Mahaboob Basha. "A High-Performance Signed-Unsigned Multiplier Using Vedic Mathematics". Journal of Low Power Electronics 15, nr 3 (1.09.2019): 302–8. http://dx.doi.org/10.1166/jolpe.2019.1616.
Pełny tekst źródłaProf. Parvaneh Basaligheh. "Design and Implementation of High Speed Vedic Multiplier in SPARTAN 3 FPGA Device". International Journal of New Practices in Management and Engineering 6, nr 01 (31.03.2017): 14–19. http://dx.doi.org/10.17762/ijnpme.v6i01.51.
Pełny tekst źródłaRozprawy doktorskie na temat "VEDIC MULTIPLIERS"
ANTONY, SAJI M. "DESIGN OF ENERGY EFFICIENT TRANSCEIVER BLOCKS FOR WIRELESS SENSOR NODES". Thesis, DELHI TECHNOLOGICAL UNIVERSITY, 2020. http://dspace.dtu.ac.in:8080/jspui/handle/repository/18771.
Pełny tekst źródłaJiang, CunHao, i 蔣存皓. "An Efficient Vedic Multiplier Design". Thesis, 2017. http://ndltd.ncl.edu.tw/handle/65n6nm.
Pełny tekst źródła國立臺北科技大學
電子工程系研究所
105
Multiplier is one of core operations of the digital signal processing and microprocessor. the multiplier in the digital circuit needs to increase the speed, decrease the area and consume less memory. So an efficient multiplier is very important in nowadays. This paper is about designing traditional Vedic multiplier through the Urdhva-Tiryagbhyam sutra. Changing the adder from the traditional Vedic multiplier which designed with the sutra, it can become two kinds of efficient Vedic multipliers. After designing 4-bit, 8-bit, 16-bit, 32-bit traditional Vedic multiplier and two kinds of efficient Vedic multipliers, their time delay and areas are analyzed through the Quartus II. According to the results of the experiment, time delay of the original efficient Vedic multiplier decreases 5.88% but the area increases 37.298%. Besides, time delay of the resolved efficient Vedic multiplier decreases 7.4% but the area increases 21.6%. If the multiplier needs to be faster on work afterwards, 4-bit and 16-bit original efficient Vedic multiplier and 8-bit, 32-bit and 64-bit resolved efficient Vedic multiplier are suggested. If the multiplier needs to be smaller, traditional Vedic multiplier is suggested. If both delay time and chip area cost are considered comprehensively, 8-bit or 64-bit resolved efficient Vedic multiplier are suggested.
RUHELA, DIKSHA. "DESIGN AND IMPLEMENTATION OF EFFICIENT REVERSIBLE MULTIPLIER USING VEDIC MATHEMATICS TOOL". Thesis, 2016. http://dspace.dtu.ac.in:8080/jspui/handle/repository/14759.
Pełny tekst źródłaKUMAR, SHIVAM. "DESIGN AND IMPLEMENTATION OF EFFICIENT MATRIX MULTIPLICATION USING VARIOUS ARCHITECTURE". Thesis, 2023. http://dspace.dtu.ac.in:8080/jspui/handle/repository/19896.
Pełny tekst źródłaKsiążki na temat "VEDIC MULTIPLIERS"
Design of a High Speed Multiplier (Ancient Vedic Mathematics Approach) . Innovative Research Publications, 2013.
Znajdź pełny tekst źródłaCzęści książek na temat "VEDIC MULTIPLIERS"
Sai Ramya, A., B. S. S. V. Ramesh Babu, E. Srikala, M. Pavan, P. Unita i A. V. S. Swathi. "Performance of Optimized Reversible Vedic Multipliers". W Lecture Notes in Networks and Systems, 587–93. Singapore: Springer Singapore, 2017. http://dx.doi.org/10.1007/978-981-10-3226-4_60.
Pełny tekst źródłaEshack, Ansiya, i S. Krishnakumar. "Design of Low-Power Vedic Multipliers Using Pipelining Technology". W Proceedings of the Third International Conference on Computational Intelligence and Informatics, 281–87. Singapore: Springer Singapore, 2020. http://dx.doi.org/10.1007/978-981-15-1480-7_24.
Pełny tekst źródłaPasuluri, Bindu Swetha, i V. J. K. Kishor Sonti. "Performance Analysis of 8-Bit Vedic Multipliers Using HDL Programming". W Lecture Notes in Electrical Engineering, 1036–46. Singapore: Springer Singapore, 2020. http://dx.doi.org/10.1007/978-981-15-1420-3_114.
Pełny tekst źródłaLoganathan, Haripriya, Patnaikuni Rohit, Polamarasetty Sai Suneel i Karthi Balasubramanian. "Low-Power and Area-Efficient Design of Higher-Order Floating-Point Multipliers Using Vedic Mathematics". W Lecture Notes in Electrical Engineering, 475–86. Singapore: Springer Singapore, 2019. http://dx.doi.org/10.1007/978-981-13-8942-9_39.
Pełny tekst źródłaSudhamsu Preetham, J. V. R., Perli Nethra, D. Chandrasekhar, Mathangi Akhila, N. Arun Vignesh i Asisa Kumar Panigrahy. "Vedic Multiplier for High-Speed Applications". W Communication, Software and Networks, 349–56. Singapore: Springer Nature Singapore, 2022. http://dx.doi.org/10.1007/978-981-19-4990-6_31.
Pełny tekst źródłaPavan Kumar, N., i K. Shashi Raj. "Delay Analysis of Hybrid Vedic Multiplier". W Advances in Intelligent Systems and Computing, 91–103. Singapore: Springer Singapore, 2022. http://dx.doi.org/10.1007/978-981-16-7330-6_8.
Pełny tekst źródłaLachireddy, Dhanunjay, i S. R. Ramesh. "Power and Delay Efficient ALU Using Vedic Multiplier". W Lecture Notes in Electrical Engineering, 703–11. Singapore: Springer Singapore, 2020. http://dx.doi.org/10.1007/978-981-15-5558-9_61.
Pełny tekst źródłaKumari, Sabita, i Kanchan Sharma. "Implementation of Nobel Vedic Multiplier Using Arithmetic Adder". W Data Intelligence and Cognitive Informatics, 209–16. Singapore: Springer Singapore, 2022. http://dx.doi.org/10.1007/978-981-16-6460-1_15.
Pełny tekst źródłaAwade, Anirudh, Prachi Jain, S. Hemavathy i V. S. Kanchana Bhaaskaran. "Design of Vedic Multiplier Using Reversible Logic Gates". W Lecture Notes in Electrical Engineering, 435–48. Singapore: Springer Singapore, 2021. http://dx.doi.org/10.1007/978-981-15-9019-1_38.
Pełny tekst źródłaSrimani, Supriyo, Diptendu Kumar Kundu, Saradindu Panda i B. Maji. "Implementation of High Performance Vedic Multiplier and Design of DSP Operations Using Vedic Sutra". W Computational Advancement in Communication Circuits and Systems, 443–49. New Delhi: Springer India, 2015. http://dx.doi.org/10.1007/978-81-322-2274-3_49.
Pełny tekst źródłaStreszczenia konferencji na temat "VEDIC MULTIPLIERS"
Jain, Ankita, i Atush Jain. "Design, implementation & comparison of vedic multipliers with conventional multiplier". W 2017 International Conference on Energy, Communication, Data Analytics and Soft Computing (ICECDS). IEEE, 2017. http://dx.doi.org/10.1109/icecds.2017.8389596.
Pełny tekst źródłaKumar, Akash, Tarun Chaudhary i Vijay Kumar Ram. "Comparative Analysis of Multiplications Technique Conventional, Booth, Array Multiplier and Vedic Arithmetic Using VHDL". W International Conference on Women Researchers in Electronics and Computing. AIJR Publisher, 2021. http://dx.doi.org/10.21467/proceedings.114.63.
Pełny tekst źródłaGujamagadi, Pavan, Pramod R. Sankolli, Praveen Kumar V, Raghavendra Nayak B, Namita Palecha i Suma MS. "Design of Vedic multiplier for high fault coverage and comparative analysis with conventional multipliers". W 2015 IEEE International Advance Computing Conference (IACC). IEEE, 2015. http://dx.doi.org/10.1109/iadcc.2015.7154805.
Pełny tekst źródłaSaligram, Rakshith, i T. R. Rakshith. "Optimized reversible vedic multipliers for high speed low power operations". W 2013 IEEE Conference on Information & Communication Technologies (ICT). IEEE, 2013. http://dx.doi.org/10.1109/cict.2013.6558205.
Pełny tekst źródłaMulkalapally, Mounika, Jacob Manning, Paul Gatewood i Tooraj Nikoubin. "High Speed, Area and Power Efficient 32-bit Vedic Multipliers". W ICCCNT '16: 7th International Conference on Computing Communication and Networking Technologies. New York, NY, USA: ACM, 2016. http://dx.doi.org/10.1145/2967878.2967890.
Pełny tekst źródłaKumari, Raj, i Rajesh Mehra. "Power and delay analysis of CMOS multipliers using Vedic algorithm". W 2016 IEEE 1st International Conference on Power Electronics, Intelligent Control and Energy Systems (ICPEICES). IEEE, 2016. http://dx.doi.org/10.1109/icpeices.2016.7853344.
Pełny tekst źródłaVijayan, Aravind E., Arlene John i Deepak Sen. "Efficient implementation of 8-bit vedic multipliers for image processing application". W 2014 International Conference on Contemporary Computing and Informatics (IC3I). IEEE, 2014. http://dx.doi.org/10.1109/ic3i.2014.7019675.
Pełny tekst źródłaRaj, Rishi, Darsana S i Ramesh P. "Performance Analysis of 32-Bit Vedic Multipliers for Different Adder Configurations". W 2022 IEEE 19th India Council International Conference (INDICON). IEEE, 2022. http://dx.doi.org/10.1109/indicon56171.2022.10040134.
Pełny tekst źródłaRao, K. Deergha, P. V. Muralikrishna i Ch Gangadhar. "FPGA Implementation of 32 Bit Complex Floating Point Multiplier Using Vedic Real Multipliers with Minimum Path Delay". W 2018 5th IEEE Uttar Pradesh Section International Conference on Electrical, Electronics and Computer Engineering (UPCON). IEEE, 2018. http://dx.doi.org/10.1109/upcon.2018.8597031.
Pełny tekst źródłaPatil, Abhijeet, Shreyas Kapare, Ganesh Shinde, Arti Tekade, Maithili Andhare i Vijayalaxmi Kumbar. "Create a 32-bit Vedic Multiplier and Compare it Against Other Multipliers Using A Carry Look-Ahead Adder". W 2023 4th International Conference for Emerging Technology (INCET). IEEE, 2023. http://dx.doi.org/10.1109/incet57972.2023.10170076.
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