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Gotowa bibliografia na temat „VEDIC MATHEMATICS TOOL”

Autor: Grafiati

Data publikacji: 11 września 2023

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Artykuły w czasopismach na temat "VEDIC MATHEMATICS TOOL"

Rešić, Sead, i Adin Lemo. "VEDIC MATHEMATICS". Journal Human Research in Rehabilitation 5, nr 2 (wrzesień 2015): 23–30. http://dx.doi.org/10.21554/hrr.091509.

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It is very difficult to motivate students when it comes to a school subject like Mathematics. Teachers spend a lot of time trying to find something that will arouse interest in students. It is particularly difficult to find materials that are motivating enough for students that they eagerly wait for the next lesson. One of the solutions may be found in Vedic Mathematics. Traditional methods of teaching Mathematics create fear of this otherwise interesting subject in the majority of students. Fear increases failure. Often the traditional, conventional mathematical methods consist of very long lessons which are difficult to understand. Vedic Mathematics is an ancient system that is very flexible and encourages the development of intuition and innovation. It is a mental calculating tool that does not require a calculator because the calculator is embedded in each of us. Starting from the above problems of fear and failure in Mathematics, the goal of this paper is to do research with the control and the experimental group and to compare the test results. Two tests should be done for each of the groups. The control group would do the tests in the conventional way. The experimental group would do the first test in a conventional manner and then be subjected to different treatment, that is to say, be taught on the basis of Vedic Mathematics. After that, the second group would do the second test according to the principles of Vedic Mathematics. Expectations are that after short lectures on Vedic mathematics results of the experimental group would improve and that students will show greater interest in Mathematics.

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Khan, Angshuman, Sudip Halder i Shubhajit Pal. "Design of ASIC Square Calculator Using AncientVedic Mathematics". International Journal of Engineering & Technology 7, nr 2.23 (20.04.2018): 464. http://dx.doi.org/10.14419/ijet.v7i2.23.15334.

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This article includes a simple design of Vedic square calculator for Application Specific Integrated Circuit (ASIC). This is a straightforward and innovative design of Vedic calculator using only few basic digital logic gates. Among the all sutras and sub sutras of ancient Vedic mathematics, the sutra ‘Urdhva Tiryagbyham’ is used here for square calculation of two bits numbers which results in an effortless and faster method of square calculation than all the existing methods. The design and minimization of the circuit has been carried out to achieve a standard architecture that is the simplest too. Here Xilinx ISE software tool is used rigorously to simulate the architecture.

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Kuruvilla, Siya Susan, Stephani Sunil, Abisha Susan Alichan i Abraham K. Thomas. "Comparison of Vedic Multiplier Implementation Using Gate Diffusion Input and Modified Gate Diffusion Input Techniques". Journal of Signal Processing 8, nr 2 (22.06.2022): 1–5. http://dx.doi.org/10.46610/josp.2022.v08i02.001.

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Vedic maths is an ancient mathematical theory based on 16 sutras that has a unique computation technique. We employ the fourteenth sutra, 'Urdhva Tiryakbhyam', from the 16 sutras. Multiplication can be done 'vertically and crosswise' using this sutra. The creation of a high-speed Vedic Multiplier based on ancient Indian Vedic Mathematics principles that have been tweaked to boost efficiency. Power, area, and latency are the three fundamental restrictions in modern VLSI technological advancements. Multipliers are used in high-speed arithmetic logic units, multiplier and accumulate units, and other similar applications. With the rising limits on latency, the design of faster multiplications is becoming increasingly important. Many changes are being done to improve speed. Vedic multipliers based on Vedic Mathematics are among them. Power, area, and latency are the three fundamental restrictions in modern VLSI technological advancements. CMOS (Complementary metal-oxide-semiconductor) designs take up more space and use more energy. Power dissipation causes an IC to heat up, which has a direct impact on its reliability and performance. Gate Diffusion Input (GDI) technology reduces the size, propagation delay, and power consumption of digital circuits while also lowering logic complexity as compared to traditional CMOS and existing pass transistor logic approaches. We compared a 2x2 Vedic multiplier based on the GDI and mGDI (Modified GDI) techniques in this study. In comparison to the GDI approach, the mGDI technology employs much less transistors. The Vedic multiplier is implemented in the cadence virtuoso tool, on 180nm and 90nm technology.

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Khubnani, Rashi, Tarunika Sharma i Chitirala Subramanyam. "Applications of Vedic multiplier - A Review". Journal of Physics: Conference Series 2225, nr 1 (1.03.2022): 012003. http://dx.doi.org/10.1088/1742-6596/2225/1/012003.

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Abstract Vedic Multiplier is a key tool in rapidly growing technology especially in the immense domain of Image processing, Digital Signal Processing, real-time signal. Multipliers are important block in digital systems and play a critical role in digital designs. Along with accuracy demand for minimizing time area, power, and delay of the processor by enhancing speed is the focus point. Vedic mathematics rules and Algorithms generate partial products concurrently and save time. This paper is a review of the application and modification of Vedic multiplier in different fields and a comparison of Vedic multiplier with other multipliers for enhancing performance parameters.

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Bharatha Babu, K., i V. Anupriya. "VLSI Design Based Delay and Power Performance Comparison and Analysis of Multipliers". Multidisciplinary Journal for Applied Research in Engineering and Technology I, nr I (29.08.2021). http://dx.doi.org/10.54228/mjaret08210009.

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Recently, the problem of power dissipation has become more important in VLSI design. The multiplier is a major drain on resources. The multiplier is a basic operation in arithmetic. This article examines a variety of multipliers at the algorithmic, circuit, and layout levels. The multiplier schematic was designed using TANNER TOOL. It has been possible to increase the speed and area of multipliers by utilising Vedic mathematics for multiplication. Vedic mathematics' "Ni khilam sutra" formula can multiply large numbers. One of the primary objectives is to increase speed while simultaneously decreasing power, area, and delay.

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PATRO, ARUN K., i KUNAL N. DEKATE. "A TRANSISTOR LEVEL ANALYSIS FOR A 8-BIT VEDIC MULTIPLIER". International Journal of Electronics Signals and Systems, październik 2012, 78–83. http://dx.doi.org/10.47893/ijess.2012.1086.

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Power and area efficient multiplier using CMOS logic circuits for applications in various digital signal processors is designed. This multiplier is implemented using Vedic multiplication algorithms mainly the "Urdhvatiryakbhyam sutra" , which is the most generalized one Vedic multiplication algorithm [1] . A multiplier is a very important element in almost all the processors and contributes substantially to the total power consumption of the system. The novel point is the efficient use of Vedic algorithm (sutras) that reduces the number of computational steps considerably compared with any conventional method . The schematic for this multiplier is designed using TANNER TOOL. The design is then verified in T-SPICE using 0.18 um CMOS technology library file. The analysis is made for various voltages across a range of 2.5V to 5V, to validate the design. A CMOS digital multiplier, with low power consumption and high linearity is proposed. The results prove that the proposed multiplier consumes 80% less power compared to the gate level analysis done earlier. The core area of the proposed multiplier is 737 um2 . Paper presents a systematic design methodology for this improved performance digital multiplier based on Vedic mathematics.

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"Delay Efficient Vedic Multiplier for DSP". International Journal of Innovative Technology and Exploring Engineering 8, nr 9S (23.08.2019): 499–501. http://dx.doi.org/10.35940/ijitee.i1078.0789s19.

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Multipliers are very essential blocks in any arithmetic and logic unit, accumulators and Digital signal processors. Due to the enlarging check on delay, design of faster multipliers is desired. Amidst numerous multipliers, Vedic multipliers are favored for their speed of operation. There are sixteen sutras in Vedic mathematics out of which four are multiplication techniques. “URDHVA TIRYAKBHYAM” is the most efficient vedic multiplication technique in terms of speed. In this paper we aim to develop a multiplier using Ripple Carry Adder and parallel prefix adders which carry out the “URDHVA TIRYAKBHYAM” sutra with improved speed of operation by providing the minimum delay for the multiplication of numbers regardless of their bit sizes. A vast majority of the engineering domain consists of ubiquitous technologies like DSP. As it is one of the most rapid growing technologies of the 21st Century, it faces challenges and improvisation at each step. Engineers are working diligently to improve the quality of Digital Signal processors and major breakthroughs are being made at a very good rate. Proposed multiplier could be applied for such DSP applications. Verilog language has been used for the coding. Xilinx Vivado Tool is used for synthesis and Model Sim 5.4 has been used for simulation.

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Gopinath, Jini K., i Rita Krishnan. "Vedic mathematics training in specific learning difficulty: A study on upper primary children". Indian Journal of Positive Psychology 9, nr 01 (6.04.2018). http://dx.doi.org/10.15614/ijpp.v9i01.11750.

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The aim of the present study was to examine the efficacy of vedic mathematics training on children with specific learning difficulty. The mean age of the participants was 11.39 with a standard deviation of 0.63, and were divided into three groups. One group underwent training in Vedic Mathematics, the second group underwent conventional remediation for mathematics and the third group had sessions on general knowledge. The tools included Diagnostic Arithmetic Test (DAT) from the NIMHANS index of learning disability and a Visual Analogue Scale. One way Analysis of Variance showed that children who underwent Vedic Mathematics training and Remediation training performed significantly better on the DAT at post training assessment. The study points the option of including Vedic Mathematics Training in Schools to help children understand mathematics concepts better.

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Khan, Angshuman, Sudip Halder, Souvik Saha i Rajeev Arya. "FPGA Implementation of Vedic Squarer for Communication Systems". International Journal of Sensors, Wireless Communications and Control 09 (11.06.2019). http://dx.doi.org/10.2174/2210327909666190611143919.

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The squarer or squaring circuit is extensively used in communication systems as a mathematical function with applications of frequency doublers, finite impulse response (FIR) filters, peak amplitude detectors, digital processors and analog multipliers, etc. and especially for square law detection circuits. Vedic multipliers are popular mainly for it’s simplicity in the literature of digital multipliers. Recently proposed 2-bit square calculator or self-multiplier already took the attraction of the researchers. In this paper, two bits squarer or self-multiplier or square calculator has been successfully coded using VHDL, verified in Xilinx tool and finally implemented in popular FPGA Spartan kit.

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Baranov, V. M. "An Original Analytical Study of Innovative Legal Technologies. Review of the Monograph By Degtyarev M.V. “The Latest Regulatory Technologies and Tools: Regulatory Experiments, Sandboxes, Guillotines, Ecosystems, Platforms” / Edited by Prof. I.V. Ponkin / Moscow State Law University Named After O.E. Kutafin (MSLA). M.: Buki Vedi, 2022. 424 p.)". Proceedings of the Institute of State and Law of the RAS, 28.07.2022, 168–81. http://dx.doi.org/10.35427/2073-4522-2022-17-3-baranov.

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Rozprawy doktorskie na temat "VEDIC MATHEMATICS TOOL"

RUHELA, DIKSHA. "DESIGN AND IMPLEMENTATION OF EFFICIENT REVERSIBLE MULTIPLIER USING VEDIC MATHEMATICS TOOL". Thesis, 2016. http://dspace.dtu.ac.in:8080/jspui/handle/repository/14759.

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Multiplier is one of the important block in almost all the arithmetic logic units. These multipliers are mostly used in the fields of the Digital Signal Processing (DSP), Fast Fourier Transform, convolution, filtering and microprocessor applications. A system's performance is generally determined by the performance of the multiplier, because the multiplier is generally the slowest element in the system. Furthermore, it is generally the most area consuming. Hence, optimizing the speed and area of the multiplier is a major design issue. Since multiplier is the main component and hence a high speed and area efficient multiplier can be achieve by using Vedic mathematics. In this work we have implemented the Vedic multiplier using Chinese Abacus Adder with and without using Reversible logic gates. Reversible logic is one of the promising fields for future low power design technologies. Since one of the requirements of all DSP processors and other embedded devices is to minimize power dissipation multipliers with high speed and lower dissipations are critical. This work is devoted to the design of a high speed Vedic multiplier using reversible logic gates. For arithmetic multiplication, various Vedic multiplication techniques like Urdhva Tiryakbhyam, Nikhilam and Anurupye have been thoroughly discussed. It has been found that Urdhva Tiryakbhyam Sutra is the most efficient Sutra (Algorithm), giving minimum delay for multiplication of all types of numbers, either small or large. Further, the Verilog HDL coding of Urdhva Tiryakbhyam Sutra for 32x32 bits and 64x64 bits multiplication and their FPGA implementation by Xilinx Synthesis Tool on Spartan 3E kit have been done. The synthesis results show that the computation time for calculating the product of 4x4 multiplication is less as compared with other conventional multipliers.

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