Gotowe bibliografie tematyczne / Tunnel FETs

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  1. Artykuły w czasopismach
  2. Rozprawy doktorskie
  3. Książki
  4. Części książek
  5. Streszczenia konferencji

Gotowa bibliografia na temat „Tunnel FETs”

Autor: Grafiati
Data publikacji: 6 września 2023
Data aktualizacji: 31 lipca 2025

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Artykuły w czasopismach na temat "Tunnel FETs"

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Lind, Erik, Elvedin Memisevic, Anil W. Dey, and Lars-Erik Wernersson. "III-V Heterostructure Nanowire Tunnel FETs." IEEE Journal of the Electron Devices Society 3, no. 3 (2015): 96–102. http://dx.doi.org/10.1109/jeds.2015.2388811.

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Pandey, Rahul, Saurabh Mookerjea, and Suman Datta. "Opportunities and Challenges of Tunnel FETs." IEEE Transactions on Circuits and Systems I: Regular Papers 63, no. 12 (2016): 2128–38. http://dx.doi.org/10.1109/tcsi.2016.2614698.

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Sedighi, Behnam, Xiaobo Sharon Hu, Huichu Liu, Joseph J. Nahas, and Michael Niemier. "Analog Circuit Design Using Tunnel-FETs." IEEE Transactions on Circuits and Systems I: Regular Papers 62, no. 1 (2015): 39–48. http://dx.doi.org/10.1109/tcsi.2014.2342371.

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Moselund, K. E., H. Schmid, C. Bessire, M. T. Bjork, H. Ghoneim, and H. Riel. "InAs–Si Nanowire Heterojunction Tunnel FETs." IEEE Electron Device Letters 33, no. 10 (2012): 1453–55. http://dx.doi.org/10.1109/led.2012.2206789.

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Ortiz-Conde, Adelmo, Francisco J. García-Sánchez, Juan Muci, et al. "Threshold voltage extraction in Tunnel FETs." Solid-State Electronics 93 (March 2014): 49–55. http://dx.doi.org/10.1016/j.sse.2013.12.010.

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Wu, Jianzhi, Jie Min, and Yuan Taur. "Short-Channel Effects in Tunnel FETs." IEEE Transactions on Electron Devices 62, no. 9 (2015): 3019–24. http://dx.doi.org/10.1109/ted.2015.2458977.

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Verhulst, Anne S., William G. Vandenberghe, Karen Maex, Stefan De Gendt, Marc M. Heyns, and Guido Groeseneken. "Complementary Silicon-Based Heterostructure Tunnel-FETs With High Tunnel Rates." IEEE Electron Device Letters 29, no. 12 (2008): 1398–401. http://dx.doi.org/10.1109/led.2008.2007599.

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Huang, Jun Z., Pengyu Long, Michael Povolotskyi, Gerhard Klimeck, and Mark J. W. Rodwell. "P-Type Tunnel FETs With Triple Heterojunctions." IEEE Journal of the Electron Devices Society 4, no. 6 (2016): 410–15. http://dx.doi.org/10.1109/jeds.2016.2614915.

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Avedillo, M. J., and J. Núñez. "Improving speed of tunnel FETs logic circuits." Electronics Letters 51, no. 21 (2015): 1702–4. http://dx.doi.org/10.1049/el.2015.2416.

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Pandey, Rahul, Bijesh Rajamohanan, Huichu Liu, Vijaykrishnan Narayanan, and Suman Datta. "Electrical Noise in Heterojunction Interband Tunnel FETs." IEEE Transactions on Electron Devices 61, no. 2 (2014): 552–60. http://dx.doi.org/10.1109/ted.2013.2293497.

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Rozprawy doktorskie na temat "Tunnel FETs"

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Horst, Fabian. "Compact DC Modeling of Tunnel-FETs." Doctoral thesis, Universitat Rovira i Virgili, 2019. http://hdl.handle.net/10803/668957.

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En l'última dècada, el transistor d'efecte de camp amb efecte túnel (TFET) ha guanyat molt interès i es maneja com un possible successor de la tecnologia MOSFET convencional. El transport de càrrega en un TFET es basa en el mecanisme de túnel de banda a banda (B2B) i, per tant, el pendent sub-llindar a temperatura ambient pot superar el límit de 60 mV / dec. Per descriure i analitzar el comportament del TFET en les simulacions de circuits, aquesta dissertació introdueix un model compacte de CC per TFET de doble comporta. L'enfocament de modelatge considera l'efecte túnel B2B amb l'efecte p
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Gräf, Michael. "Two-Dimensional Analytical Modeling of Tunnel-FETs." Doctoral thesis, Universitat Rovira i Virgili, 2017. http://hdl.handle.net/10803/450516.

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Basat en un mecanisme de transport de corrent de banda a banda, el túnel-FET és capaç de superar la limitació de pendent sub-llindar física del MOSFET de 60 mV /dec. Per tant, s'ha convertit en un dels dispositius més prometedors per ser el successor del MOSFET clàssic en els últims anys. Aquesta tesi descriu tots els passos necessaris per modelar analíticament un Túnel-FET de doble porta. El model inclou una solució electrostàtica de dues dimensions en totes les regions del dispositiu, el que permet fins i tot simulacions hetero-unió del dispositiu. Per a un comportament més realista del dis
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Yu, Tao Ph D. Massachusetts Institute of Technology. "InGaAs/GaAsSb type-Il heterojunction vertical tunnel-FETs." Thesis, Massachusetts Institute of Technology, 2013. http://hdl.handle.net/1721.1/84857.

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Thesis (S.M.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2013.<br>Cataloged from PDF version of thesis.<br>Includes bibliographical references (pages 59-62).<br>The supply voltage (VDD) scaling of conventional CMOS technology is approaching its limit due to the physical limit of 60 mV/dec subthreshold swing (SS) at room temperature and the requirement for controlled leakage current. In order to continue VDD scaling for low power applications, novel device structures with steep SS have been proposed. Tunnel-FETs (TFETs) are among the most attra
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Farokhnejad, Atieh. "Compact Modeling of Intrinsic Capacitances in Double-Gate Tunnel-FETs." Doctoral thesis, Universitat Rovira i Virgili, 2020. http://hdl.handle.net/10803/669806.

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La miniaturització dels MOSFET en els circuits integrats ha elevat la tecnologia microelectrònica. Aquesta tendència també augmenta el grau de complexitat d'aquests circuits i els seus components bàsics. En els MOSFET convencionals, el corrent es basa en l'emissió termoiònica de portadors de càrrega, que per això limita el pendent subumbral en aquests transistors a 60 mV / dec. Per tant, per superar aquest límit i continuar amb la miniaturització per mantenir el ritme de la llei de Moore, es requereixen estructures alternatives. Entre aquestes, el transistor d'efecte de camp per túnel (TFET) e
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Yu, Tao Ph D. Massachusetts Institute of Technology. "InGaAs/GaAsSb quantum-well Tunnel-FETs for ultra-low power applications." Thesis, Massachusetts Institute of Technology, 2016. http://hdl.handle.net/1721.1/106101.

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Thesis: Ph. D., Massachusetts Institute of Technology, Department of Electrical Engineering and Computer Science, 2016.<br>Cataloged from PDF version of thesis.<br>Includes bibliographical references.<br>The Tunnel-FET (TFET), where carrier injection is determined by gate-controlled tunneling from the source to the channel, has been attractive as one of the promising candidates for future ultra-low power applications. In this thesis, inline-TFETs with tunneling direction aligned to the gate electric field are designed, fabricated and analyzed based on InGaAs/GaAsSb material. Using ultrathin In
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Cavalheiro, David. "Ultra-low power circuits based on tunnel FETs for energy harvesting applications." Doctoral thesis, Universitat Politècnica de Catalunya, 2017. http://hdl.handle.net/10803/406391.

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There has been a tremendous evolution in integrated circuit technology in the past decades. With the scaling of complementary metal-oxide-semiconductor (CMOS) transistors, faster, less power consuming and more complex chips per unit area have made possible electronic gadgets to evolve to what we see today. The increasing demand in electronic portability imposes low power consumption as a key metric to analog and digital circuit design. While dynamic power consumption decreases quadratically with the decrease of power supply voltage, leakage power presents a limitation due to the inverse sub-t
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Richter, Simon [Verfasser]. "Strained silicon and silicon-germanium nanowire tunnel FETs and inverters / Simon Richter." Aachen : Hochschulbibliothek der Rheinisch-Westfälischen Technischen Hochschule Aachen, 2014. http://d-nb.info/1059533189/34.

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Narimani, Keyvan [Verfasser], Joachim [Akademischer Betreuer] Knoch, and Siegfried [Akademischer Betreuer] Mantl. "Silicon tunnel FETs for digital and analogue applications / Keyvan Narimani ; Joachim Knoch, Siegfried Mantl." Aachen : Universitätsbibliothek der RWTH Aachen, 2018. http://d-nb.info/121148758X/34.

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Narimani, Keyvan Verfasser], Joachim [Akademischer Betreuer] [Knoch, and Siegfried [Akademischer Betreuer] Mantl. "Silicon tunnel FETs for digital and analogue applications / Keyvan Narimani ; Joachim Knoch, Siegfried Mantl." Aachen : Universitätsbibliothek der RWTH Aachen, 2018. http://d-nb.info/121148758X/34.

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Blaeser, Sebastian Verfasser], Siegfried [Akademischer Betreuer] [Mantl, and Christoph [Akademischer Betreuer] Stampfer. "Strained Silicon-Germanium/Silicon Heterostructure Tunnel FETs for Low Power Applications / Sebastian Blaeser ; Siegfried Mantl, Christoph Stampfer." Aachen : Universitätsbibliothek der RWTH Aachen, 2016. http://d-nb.info/1126646431/34.

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Książki na temat "Tunnel FETs"

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Bessire, Cédric Dominic. Semiconducting nanowire tunnel devices: From all-Si tunnel diodes to III-V heterostructure tunnel FETs. Hartung-Gorre Verlag, 2013.

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Moll, Francesc, David Cavalheiro, and Stanimir Valtchev. Ultra-Low Input Power Conversion Circuits Based on Tunnel-FETs. River Publishers, 2022.

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Moll, Francesc, David Cavalheiro, and Stanimir Valtchev. Ultra-Low Input Power Conversion Circuits Based on Tunnel-FETs. River Publishers, 2018.

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Moll, Francesc, David Cavalheiro, and Stanimir Valtchev. Ultra-Low Input Power Conversion Circuits Based on Tunnel-FETs. River Publishers, 2022.

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Moll, Francesc, David Cavalheiro, and Stanimir Valtchev. Ultra-Low Input Power Conversion Circuits Based on Tunnel-FETs. River Publishers, 2022.

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Donovan, Sandra. The Channel Tunnel (Great Building Feats). Lerner Publications, 2003.

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Bridges And Tunnels Investigate Feats Of Engineering. Nomad Press (VT), 2012.

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Demshuk, Andrew. Missed Chances, 1949–1959. Oxford University Press, 2017. http://dx.doi.org/10.1093/oso/9780190645120.003.0002.

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After a sketch of Leipzig’s immediate postwar reconstruction efforts before the founding of the DDR in 1949, this chapter features ten years of public enthusiasm for the young Communist State’s early planning initiatives. Press publications and planning exhibitions stimulated optimistic public participation and proposals, because most plans generally adhered to a platform of moderate reconstruction of the historic core alongside startling modern feats that the people desired, such as an underground rail tunnel and an array of new trade fair (Messe) palaces. Such remarkable goodwill from the po
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Britain, Great. The Channel Tunnel Rail Link (Fees for Requests for Planning Approval) Regulations 1997 (Statutory Instruments: 1997: 822). Stationery Office Books, 1997.

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Davidson, Frank P., and Kathleen Lusk Brooke. Building the World. Greenwood Publishing Group, Inc., 2006. http://dx.doi.org/10.5040/9798216193371.

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Humans are builders—we make structures to span rivers, to connect points of land, to offer shelter. Indeed, throughout history, civilizations have created structures of such immense scale, requiring such tremendous resources, that they might have been thought impossible. From the Taj Mahal to the Suez Canal, from Solomon's Temple to the Trans-Alaska Pipeline, these feats of macro-engineering are a testament to the creativity and foresight of engineers, architects, government officials, and diplomats. Who came up with the ideas for these projects? How did they see them through to completion? Wh
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Części książek na temat "Tunnel FETs"

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Cavalheiro, David, Francesc Moll, and Stanimir Valtchev. "Tunnel FET: Physical Properties." In Ultra-Low Input Power Conversion Circuits based on Tunnel-FETs. River Publishers, 2022. http://dx.doi.org/10.1201/9781003339892-3.

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Cavalheiro, David, Francesc Moll, and Stanimir Valtchev. "Tunnel FET: Electrical Properties." In Ultra-Low Input Power Conversion Circuits based on Tunnel-FETs. River Publishers, 2022. http://dx.doi.org/10.1201/9781003339892-4.

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Cavalheiro, David, Francesc Moll, and Stanimir Valtchev. "Tunnel FET-based Rectifiers." In Ultra-Low Input Power Conversion Circuits based on Tunnel-FETs. River Publishers, 2022. http://dx.doi.org/10.1201/9781003339892-6.

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Le Royer, Cyrille, Anthony Villalon, Mikaël Cassé, et al. "High-Performance Tunnel FETs on Advanced FDSOI Platform." In Functional Nanomaterials and Devices for Electronics, Sensors and Energy Harvesting. Springer International Publishing, 2014. http://dx.doi.org/10.1007/978-3-319-08804-4_4.

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Manikandan, S., and Adhithan Pon. "Historical Development of MOS Technology to Tunnel FETs." In Tunneling Field Effect Transistors. CRC Press, 2023. http://dx.doi.org/10.1201/9781003327035-3.

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Ehteshamuddin, Mohammad, S. Manikandan, and Adhithan Pon. "Investigation on Ambipolar Current Suppression in Tunnel FETs." In Tunneling Field Effect Transistors. CRC Press, 2023. http://dx.doi.org/10.1201/9781003327035-9.

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El Kazzi, Salim. "Molecular Beam Epitaxy for Steep Switching Tunnel FETs." In Molecular Beam Epitaxy. John Wiley & Sons Ltd, 2019. http://dx.doi.org/10.1002/9781119354987.ch8.

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Cavalheiro, David, Francesc Moll, and Stanimir Valtchev. "Tunnel FET-based Charge Pumps." In Ultra-Low Input Power Conversion Circuits based on Tunnel-FETs. River Publishers, 2022. http://dx.doi.org/10.1201/9781003339892-5.

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Cavalheiro, David, Francesc Moll, and Stanimir Valtchev. "Tunnel FET: State of the Art." In Ultra-Low Input Power Conversion Circuits based on Tunnel-FETs. River Publishers, 2022. http://dx.doi.org/10.1201/9781003339892-2.

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Lakshmi Priya, G., M. Venkatesh, S. Preethi, T. Venish Kumar, and N. B. Balamurugan. "Performance Analysis of Emerging Low-Power Junctionless Tunnel FETs." In Emerging Low-Power Semiconductor Devices. CRC Press, 2022. http://dx.doi.org/10.1201/9781003240778-6.

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Streszczenia konferencji na temat "Tunnel FETs"

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Koteshwar, Anirudh, Deepjyoti Deb, Shanidul Hoque, and Rupam Goswami. "Analysis of Interface Trap Position Variation in Tunnel FETs." In 2024 IEEE International Conference of Electron Devices Society Kolkata Chapter (EDKCON). IEEE, 2024. https://doi.org/10.1109/edkcon62339.2024.10870770.

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Bhatt, Jai Kumar, Girdhar Gopal, and Tarun Verma. "Analysis of Highly Sensitive Gas Sensor Based on Tunnel FETs: A Review." In 2024 IEEE Third International Conference on Power Electronics, Intelligent Control and Energy Systems (ICPEICES). IEEE, 2024. http://dx.doi.org/10.1109/icpeices62430.2024.10719188.

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Panda, Shwetapadma, Devika Jena, and Aruna Tripathy. "A Review of Ambipolarity Suppression in Tunnel FETs Using Significant Engineering Techniques." In 2025 Devices for Integrated Circuit (DevIC). IEEE, 2025. https://doi.org/10.1109/devic63749.2025.11012170.

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"Tunnel FETs." In 2011 69th Annual Device Research Conference (DRC). IEEE, 2011. http://dx.doi.org/10.1109/drc.2011.5994501.

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Riel, H., K. E. Moselund, C. Bessire, et al. "InAs-Si heterojunction nanowire tunnel diodes and tunnel FETs." In 2012 IEEE International Electron Devices Meeting (IEDM). IEEE, 2012. http://dx.doi.org/10.1109/iedm.2012.6479056.

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Wang, P. Y., and B. Y. Tsui. "Epitaxial Tunnel Layer Structure for Complementary Tunnel FETs Enhancement." In 2012 International Conference on Solid State Devices and Materials. The Japan Society of Applied Physics, 2012. http://dx.doi.org/10.7567/ssdm.2012.ps-3-4.

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Ionescu, A. M. "Energy efficient computing with tunnel FETs." In 2014 10th International Conference on Advanced Semiconductor Devices & Microsystems (ASDAM). IEEE, 2014. http://dx.doi.org/10.1109/asdam.2014.6998670.

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Vandooren, Anne, Alireza Alian, Anne Verhulst, et al. "Tunnel FETs for low power electronics." In 2016 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S). IEEE, 2016. http://dx.doi.org/10.1109/s3s.2016.7804386.

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Schenk, Andreas, Reto Rhyner, Mathieu Luisier, and Cedric Bessire. "Simulation study of nanowire tunnel FETs." In 2012 70th Annual Device Research Conference (DRC). IEEE, 2012. http://dx.doi.org/10.1109/drc.2012.6257023.

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Mizubayashi, W., T. Mori, K. Fukuda, et al. "Understanding of BTI for tunnel FETs." In 2015 IEEE International Electron Devices Meeting (IEDM). IEEE, 2015. http://dx.doi.org/10.1109/iedm.2015.7409695.

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