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Artykuły w czasopismach na temat „Triple gate transistor”

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Data publikacji: 25 maja 2024

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1

Grossl Bade, Tamiris, Hassan Hamad, Adrien Lambert, Hervé Morel i Dominique Planson. "Threshold Voltage Measurement Protocol “Triple Sense” Applied to GaN HEMTs". Electronics 12, nr 11 (3.06.2023): 2529. http://dx.doi.org/10.3390/electronics12112529.

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The threshold voltage instability in p-GaN gate high electron mobility transistors (HEMTs) has been brought into evidence in recent years. It can lead to reliability issues in switching applications, and it can be followed by other degradation mechanisms. In this paper, a Vth measurement protocol established for SiC MOSFETs is applied to GaN HEMTs: the triple sense protocol, which uses voltage bias to precondition the transistor gate. It has been experimentally verified that the proposed protocol increased the stability of the Vth measurement, even for measurements following degrading voltage bias stress on both drain and gate.
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2

Cho, Seong-Kun, i Won-Ju Cho. "Highly Sensitive and Transparent Urea-EnFET Based Point-of-Care Diagnostic Test Sensor with a Triple-Gate a-IGZO TFT". Sensors 21, nr 14 (12.07.2021): 4748. http://dx.doi.org/10.3390/s21144748.

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In this study, we propose a highly sensitive transparent urea enzymatic field-effect transistor (EnFET) point-of-care (POC) diagnostic test sensor using a triple-gate amorphous indium gallium zinc oxide (a-IGZO) thin-film pH ion-sensitive field-effect transistor (ISFET). The EnFET sensor consists of a urease-immobilized tin-dioxide (SnO2) sensing membrane extended gate (EG) and an a-IGZO thin film transistor (TFT), which acts as the detector and transducer, respectively. To enhance the urea sensitivity, we designed a triple-gate a-IGZO TFT transducer with a top gate (TG) at the top of the channel, a bottom gate (BG) at the bottom of the channel, and a side gate (SG) on the side of the channel. By using capacitive coupling between these gates, an extremely high urea sensitivity of 3632.1 mV/pUrea was accomplished in the range of pUrea 2 to 3.5; this is 50 times greater than the sensitivities observed in prior works. High urea sensitivity and reliability were even obtained in the low pUrea (0.5 to 2) and high pUrea (3.5 to 5) ranges. The proposed urea-EnFET sensor with a triple-gate a-IGZO TFT is therefore expected to be useful for POC diagnostic tests that require high sensitivity and high reliability.
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3

Conde, Jorge E., Antonio Cereira i M. Estrada. "Distortion Analysis of Triple-Gate Transistor in Saturation". ECS Transactions 9, nr 1 (19.12.2019): 67–73. http://dx.doi.org/10.1149/1.2766875.

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4

Gay, R., V. Della Marca, H. Aziza, P. Laine, A. Regnier, S. Niel i A. Marzaki. "Gate stress reliability of a novel trench-based Triple Gate Transistor". Microelectronics Reliability 126 (listopad 2021): 114233. http://dx.doi.org/10.1016/j.microrel.2021.114233.

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SHAHHOSEINI, ALI, KAMYAR SAGHAFI, MOHAMMAD KAZEM MORAVVEJ-FARSHI i RAHIM FAEZ. "TRIPLE-TUNNEL JUNCTION SINGLE ELECTRON TRANSISTOR (TTJ-SET)". Modern Physics Letters B 25, nr 17 (10.07.2011): 1487–501. http://dx.doi.org/10.1142/s0217984911026346.

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We propose a triple-tunnel junction single electron transistor (TTJ-SET). The proposed structure consists of a metallic quantum-dot island that is capacitive coupled to a gate contact and surrounded by three tunnel junctions. To the best of our knowledge, this is the first instance of introducing this new structure that is suitable for both digital and analog applications. I–V D characteristics of the proposed TTJ-SET, simulated by a HSPICE macro model for various gate voltages, are in excellent agreement with those obtained by SIMON, which is a Monte-Carlo based simulator. We show how one can design a digital inverter by using a single TTJ-SET. We also show that, under suitable conditions, a TTJ-SET can operate as a full- or half-wave analog rectifier.
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6

Pandey, Neeta, Kirti Gupta i Bharat Choudhary. "New Proposal for MCML Based Three-Input Logic Implementation". VLSI Design 2016 (19.09.2016): 1–10. http://dx.doi.org/10.1155/2016/8712768.

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This paper presents a new proposal for three-input logic function implementation in MOS current mode logic (MCML) style. The conventional realization of such logic employs three levels of stacked source-coupled transistor pairs. It puts restriction on minimum power supply requirement and results in increased static power. The new proposal presents a circuit element named as quad-tail cell which reduces number of stacked source-coupled transistor levels by two. A three-input exclusive-OR (XOR) gate, a vital element in digital system design, is chosen to elaborate the approach. Its behavior is analyzed and SPICE simulations using TSMC 180 nm CMOS technology parameters are included to support the theoretical concept. The performance of the proposed circuit is compared with its counterparts based on CMOS complementary pass transistor logic, conventional MCML, and cascading of existing two input tripple-tail XOR cells and applying triple-tail concept in conventional MCML topology. It is found that the proposed XOR gate performs best in terms of most of the performance parameters. The sensitivity of the proposed XOR gate towards process variation shows a variation of 1.54 between the best and worst case. As an extension, a realization of 4 : 1 multiplexer has also been included.
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7

Manikandan, S., P. Suveetha Dhanaselvam i M. Karthigai Pandian. "A Quasi 2-D Electrostatic Potential and Threshold Voltage Model for Junctionless Triple Material Cylindrical Surrounding Gate Si Nanowire Transistor". Journal of Nanoelectronics and Optoelectronics 16, nr 2 (1.02.2021): 318–23. http://dx.doi.org/10.1166/jno.2021.2951.

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A mathematical model used for determining the threshold voltage characteristics and electrostatic potential of a Junctionless Triple Material Cylindrical Surrounding Gate Silicon Nanowire Transistor (JLTMCSGSiNWT) is proposed in this research work and is obtained by resolving the poison equation. Three materials with dissimilar metal functions are used in the construction of the device gate structure. Device parameters used to determine the electrical characteristics are also included in the model. Behavior of the device is investigated through its vertical electrical field distribution along the device channel. Higher drain bias conditions leading to DIBL are reduced in the proposed structure by minimal variation of voltages owing to three different gate materials that maintain a steady field distribution along the channel. This model explicitly shows the impact of various criteria like drain bias voltage, gate bias voltage, thickness of the silicon layer, thickness of the oxide layer, and length of the channel on electrostatic potential and the deterioration of threshold voltage. The proposed analytical model is validated with TCAD simulations and it could be further extended to study the advanced electrical characteristics of the JL Triple Material CSG Silicon Nanowire Transistor.
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8

de Araujo, Gustavo Vinicius, Joao Martino i Paula Agopian. "Operational Transconductance Amplifier Designed with Experimental Omega-Gate Nanowire SOI MOSFETs". ECS Meeting Abstracts MA2023-01, nr 33 (28.08.2023): 1861. http://dx.doi.org/10.1149/ma2023-01331861mtgabs.

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The nanowire omega-gate technology is one of the possible technologies to replace the FinFET one in the semiconductor chip market. The omega-gate nanowire SOI MOSFET is considered a triple plus gate device, near the gate-all-around performance (figure 1) [1]. Due to the omega gate structure this device presents a better gate to channel electrostatic coupling than the FinFET devices, resulting in a greater immunity to short channel effects [1,2]. The Operational Transconductance Amplifier (OTA) is a frequently used analog block in the integrated circuits. The studied OTA consists in a two-stage amplifier, where the first stage is a differential amplifier with active load and the second one is a common source amplifier, as can be seen in figure 2. This analog block is biased through the current source and the bias current is mirrored for each stage. In addition, negative feedback is used between the first and second stages with a compensation capacitor (miller capacitor) in order to stabilize the amplifier response. In this work, an OTA circuit is designed with SOI omega-gate nanowire experimental transistors. In order to find the best device to be used in the project, some measurements were carried out of several nanowire devices with different channel lengths (ranging from 20 nm to 200 nm). The schematic structure of the measured devices is presented in figure 3 [2]. Basic device parameters such as: transconductance (gm), output conductance (gd), Early voltage (VEA), threshold voltage (VT), transistor efficiency (gm/ID) and subthreshold slope (SS) were analyzed. The model of the experimental omega-gate transistors was performed using the Look Up Table (LUT) method. The capacitance measurements of the nanowire transistor were also considered, to simulate the frequency responses more faithfully. The simulator used to design the OTA circuit was Cadence using the Verilog-A language. It was obtained the main figure of merit of this block like voltage gain (Av), gain-bandwidth product (GBW), phase margin and power. A transistor efficiency (gm/ID) near 8 V-1 was chosen in order to compare the performance of OTA designed with omega-gate nanowire devices (NW-OTA) of this work with anothers OTAs designed with triple gate FinFETs (FinFET-OTA) and with nanosheets (NS-OTA) from the literature (Table 1) [3,4]. Table 1 shows that the phase margin is close to 60o in all cases, ensuring the stability of the circuit. The NW-OTA presents higher voltage gain compared to FinFET-OTA due to the better gate to channel coupling. The NS-OTA presents the highest voltage gain of all cases, but it is the more expensive technology [4]. When GBW is analyzed for all 3 designs, the NW-OTA shows better results than the NS-OTA, using the same load capacitance of 200fF, thanks to the lower miller capacitance (Cc) required to keep the frequency behavior. The FinFET-OTA shows the best result in relation to GBW, but the FinFET-OTA project doesn’t consider a load capacitance, making the comparison unfair [3]. Figure 4 shows the gain and phase of the OTA using a SOI omega-gate nanowire transistors. In summary, the OTA designed with SOI omega-gate nanowire technology presents a better performance than FinFET one, can be implemented in a smaller area on the chip (smaller Cc capacitor and smaller number of fins in parallel) and it is a cheaper option compared to nanosheet one. Figure 1
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9

Müller, M. R., A. Gumprich, F. Schütte, K. Kallis, U. Künzelmann, S. Engels, C. Stampfer, N. Wilck i J. Knoch. "Buried triple-gate structures for advanced field-effect transistor devices". Microelectronic Engineering 119 (maj 2014): 95–99. http://dx.doi.org/10.1016/j.mee.2014.02.001.

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10

Fui, Tan Chun, Ajay Kumar Singh i Lim Way Soong. "Performance Characterization of Dual-Metal Triple- Gate-Dielectric (DM_TGD) Tunnel Field Effect Transistor (TFET)". International Journal of Robotics and Automation Technology 8 (31.12.2021): 83–89. http://dx.doi.org/10.31875/2409-9694.2021.08.8.

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Abstract: Since, Dual Metal Gate (DMG) technology alone is not enough to rectify the problem of low ON current and large ambipolar current in the TFET, therefore, a novel TFET structure, known as dual metal triple-gate-dielectric (DM_TGD) TFET, has been proposed. We have combined the dielectric and gate material work function engineering to enhance the performance of the conventional FET. In the proposed structure, the gate region is divided into three dielectric materials: TiO2/Al2O3/SiO2. This approach is chosen because high dielectric material alone near the source cannot improve the performance due to increase in fringing fields. This paper presents the detail processing of the proposed structure. We have evaluated and optimized the dc performance of the proposed N-DM_TGD TFET with the help of 2-D ATLAS simulator. The results were compared with those exhibited by dual metal hetero-gate-dielectric TFET, single metal hetero- gate-dielectric TFET and single metal triple-gate-dielectric TFET of identical dimensions. It has been observed that the DM_TGD device offers better transconductance (gm), lower subthreshold slope, lower ambipolar current and larger ON current.
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11

Darwin, S., i T. S. Arun Samuel. "Mathematical Modeling of Junctionless Triple Material Double Gate MOSFET for Low Power Applications". Journal of Nano Research 56 (luty 2019): 71–79. http://dx.doi.org/10.4028/www.scientific.net/jnanor.56.71.

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This paper describes the analytical modeling and simulation of Triple Material Double Gate Metal Oxide Semiconductor Field Effect Transistor (TMDG MOSFET) with no junctions. Three kind of gate materials with different work function values over the channel helps to improve the ON current and to form a barrier in the channel helps to reduce OFF current. It has been found from the obtained results that the OFF current or leakage current of the device is exactly low (IOFF =10-11 A) which is fit for low power applications. Also, the extracted value of ION current (10-3 A) has proved that there is a remarkable improvement with decreasing device dimensions. The overall gate length (L), work functions of gate materials, oxide thickness (tox), silicon thickness (tsi) and doping concentration (Nd) are optimized at 60nm, 4.8eV, 4.6eV, 4.4eV, 1nm, 10nm and 1019 cm-3 respectively. The 2-D Poisson equation has been solved by using parabolic approximation technique to obtain the potential distribution function in the channel. Based on this expression, analytical models of the lateral electric field, subthreshold slope and drain current for Junctionless Triple Material Double Gate Metal oxide semiconductor Field Effect Transistor (JL TMDG MOSFET) were derived. Finally, the validity of the proposed analytical model is compared with numerical solution simulation data results which are obtained by using TCAD device simulator.
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12

Gowthami, Yadala, Bukya Balaji i Karumuri Srinivasa Rao. "Design and performance analysis of front and back Pi 6 nm gate with high K dielectric passivated high electron mobility transistor". International Journal of Electrical and Computer Engineering (IJECE) 13, nr 4 (1.08.2023): 3788. http://dx.doi.org/10.11591/ijece.v13i4.pp3788-3795.

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Advanced high electron mobility transistor (HEMT) with dual front gate, back gate with silicon nitride/aluminum oxide (Si3N4/Al2O3) as passivation layer, has been designed. The dependency on DC characteristics and radio frequency characteristics due to GaN cap layers, multi gate (FG and BG), and high K dielectric material is established. Further compared single gate (SG) passivated HEMT, double gate (DG) passivated HEMT, double gate triple (DGT) tooth passivated HEMT, high K dielectric front Pi gate (FG) and back Pi gate (BG) HEMT. It is observed that there is an increased drain current (Ion) of 5.92 (A/mm), low leakage current (Ioff) 5.54E-13 (A) of transconductance (Gm) of 3.71 (S/mm), drain conductance (Gd) of 1.769 (S/mm), Cutoff frequency (fT) of 743 GHz maximum oscillation frequency (Fmax) 765 GHz, minimum threshold voltage (V<sub>th</sub>) of -4.5 V, on resistance (Ron) of 0.40 (Ohms) at V<sub>gs</sub>=0 V. These outstanding characteristics and transistor structure of proposed HEMT and materials involved to apply for upcoming generation high-speed GHz frequency applications.
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13

Gay, R., V. Della Marca, H. Aziza, M. Mantelli, F. Trenteseaux, F. La Rosa, A. Regnier, S. Niel i A. Marzaki. "A Novel Trench-Based Triple Gate Transistor With Enhanced Driving Capability". IEEE Electron Device Letters 42, nr 6 (czerwiec 2021): 832–34. http://dx.doi.org/10.1109/led.2021.3076609.

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14

Lim, Sang Woo, i Brian Winstead. "Surface Preparation for Transistor Performance Improvement in Triple Gate Oxide Integration". Journal of The Electrochemical Society 152, nr 9 (2005): G714. http://dx.doi.org/10.1149/1.1973245.

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15

Molaei Imen Abadi, Rouzbeh, i Seyed Ali Sedigh Ziabari. "A Comparative Numerical Study of Junctionless and p-i-n Tunneling Carbon Nanotube Field Effect Transistor". Journal of Nano Research 45 (styczeń 2017): 55–75. http://dx.doi.org/10.4028/www.scientific.net/jnanor.45.55.

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In this paper, a gate-all-around junctionless tunnel field effect transistor (JL-TFET) based on carbon nanotube (CNT) material is introduced and simulated. The JL-TFET is a CNT-channel heavily n-type-doped junctionless field effect transistor (JLFET) which utilizes two insulated gates (Control-Gate, P-Gate) with two different metal workfunctions in order to treat like tunnel field effect transistor (TFET). In this design, the privileges of JLTFET and TFET are mixed together. The numerical comparative study on the performance characteristics of JL-TFET and conventional p-i-n TFET demonstrated that the proposed JL-TFET has a higher ON-state current driveability (ION), a larger ON/OFF-current ratio (ION/IOFF), a lower drain induced barrier lowering (DIBL), a shorter delay time (τ), and also a superior cut-off frequency (ƒT). Moreover, in order to further performance improvement of proposed JLTFET, three novel device structures namely as junctionless linear descending gate workfunction TFET (JL-LDWTFET), junctionless linear ascending gate workfunction TFET (JL-LAWTFET) and junctionless triple metal gate TFET (JL-TMGTFET) are proposed by gate workfunction engineering approach. According to simulation results, the JL-TMGTFET with the gate composed of three segments of different work functions shows excellent characteristics with high ION/IOFF ratio, a superior ambipolar characteristic, a shorter delay time and a better cut-off frequency compared to conventional p-i-n TFET and other proposed junctionless-based features. All the simulations are done with the full quantum mechanical simulator for a channel length of 60-nm using nonequilibrium Green’s function (NEGF) method.
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16

Zakarya, Kourdi, i Abdelkhader Hamdoun. "A modeling and performance of the triple field plate HEMT". International Journal of Power Electronics and Drive Systems (IJPEDS) 10, nr 1 (1.03.2019): 398. http://dx.doi.org/10.11591/ijpeds.v10.i1.pp398-405.

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We present this work by two steps. In the first one, the new structure proposed of the FP-HEMTs device (Field plate High Electron Mobility Transistor) with a T-gate on an 4H-SIC substrate to optimize these electrical performances, multiple field-plates were used with aluminum oxide to split the single electric field peak into several smaller peaks, and as passivation works to reduce scaling leakage current. In the next, we include a modeling of a simulation in the Tcad-Silvaco Software for realizing the study of the influence of negative voltage applied to gate T-shaped in OFF state time and high power with ambient temperature, the performance differences between the 3FP and the SFP devices are discussed in detail.
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17

Gowthami, Y., B.Balaji i K. Srinivasa Rao. "Qualitative Analysis & Advancement of Asymmetric Recessed Gates with Dual Floating Material GaN HEMT for Quantum Electronics". Journal of Integrated Circuits and Systems 18, nr 1 (22.05.2023): 1–8. http://dx.doi.org/10.29292/jics.v18i1.657.

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The Impact of Aluminium nitride (AlN) Spacer, Gallium Nitride (GaN) Cap Layer, Front Pi Gate (FG) and Back Pi Gate(BG), High K dielectric material such as Hafnium dioxide(HfO2), Aluminium Oxide (Al2O3), Silicon nitride (Si3N4) on Aluminium Galium Nitride/ Gallium Nitride (AlGaN/GaN), Heterojunction High Electron Mobility Transistor (HEMT) of 6nm(nanometer) technology is simulated and extracted the results using the Silvaco Atlas TCAD tool. The importance of High K dielectric materials like Al2O3 and Si3N4 are studied for the proposal of GaN HEMT. AlN, GaN Cap Layers, and High K Dielectric material are layered one on another to overcome the conventional transistor draw backs like surface defects, scattering of the electron, and less mobility of electron. Hot electron effect is overcome by Pi type gate. Therefore, by optimizing the HEMT structure the abilities for certain devices are converted to abilities. The dependency on DC characteristics and RF characteristics due to GaN Cap Layers, Multi gate (FG &BG), and High K Dielectric material is established. Further Compared Single Gate (SG) Passivated HEMT, Double Gate (DG) Passivated HEMT, Double Gate Triple(DGT) Tooth Passivated HEMT, High K Dielectric Front Pi Gate (FG) and Back Pi Gate (BG) Nanowire HEMT. It is observed that there is an increased Drain Current (Ion) of 5.92(A/mm), low Leakage current(Ioff) 5.54E-13 (A) of Transconductance (Gm) of 3.71(S/mm), Drain Conductance (Gd) of 1.769(S/mm), Cutoff frequency(fT) of 743 GHz Maximum Oscillation frequency (Fmax) 765 GHz, Minimum Threshold Voltage (Vth) of -4.5V, On Resistance (Ron)of 0.40(Ohms) at Vgs =0V. These outstanding characteristics and transistor structure of proposed HEMT and materials involved to apply for upcoming generation High-speed GHz frequency applications.
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18

Dubey, Shashank Kumar, i Aminul Islam. "Al0.30Ga0.70N /GaN MODFET with triple-teeth metal for RF and high-power applications". Physica Scripta 97, nr 3 (10.02.2022): 034003. http://dx.doi.org/10.1088/1402-4896/ac50c3.

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Abstract A modulation-doped field-effect transistor (MODFET) has been investigated in this paper. It is also called HEMT (high electron mobility transistor). The proposed MODFET is made up of Al0.30Ga0.70N as supply layer and GaN as channel or buffer layer, in which floating metal is embedded. Its T-gate is recessed to obtain higher gm, which results in improved RF characteristics. T-gate is used to minimize the gate resistance which reduces the power consumption of the proposed HEMT. A floating metal having triple teeth (TT), which resembles a comb is developed in GaN channel/buffer layer between the gate and drain electrodes to improve the device performance without increasing the dimensions of the device. The transition or cutoff frequency (f T) of 125 GHz and unity power gain (also called) maximum oscillation) frequency (f MAX) of 530 GHz at V DS = 10 V with V GS = 0.4 V have been reported in this paper. Analysis of power consumption of the proposed FET such as power gain (A P), output power (P OUT), and power-added efficiency (PAE) have been analyzed at 10 GHz in continuous wave mode and V DS = 35 V have been analyzed. The value obtained for P OUT, A P, and PAE is 67.5 dBmW, 11.6 dB, and 24.6%, respectively. All the obtained results from the Silvaco TCAD software have been verified with the mathematical model.
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Samuel, T. S. Arun, i S. Komalavalli. "Analytical Modelling and Simulation of Triple Material Quadruple Gate Tunnel Field Effect Transistors". Journal of Nano Research 54 (sierpień 2018): 146–57. http://dx.doi.org/10.4028/www.scientific.net/jnanor.54.146.

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We build up the electrostatic model for Triple Material Quadruple Gate (TMQG) Tunnel Field Effect Transistor of rectangular cross area, in view of semi 3D strategy in this paper. The Parabolic approximation method is utilized to tackle the 2-D Poisson condition with appropriate device boundary conditions and logical articulations for surface potential and electric fields are determined. The electric field dispersion is additionally used to ascertain the tunneling generation rate. The created show furnishes the plan rules of TMQG with enhanced IONcurrent. The diagnostic outcomes are contrasted and TCAD recreation comes about.
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Pizzanelli, Riccardo, Rhaycen Prates, Marcelo Antonio Pavanello i Michelly de Souza. "(Digital Presentation) Comparison of Width and Temperature Influence on DIBL Effect in Junctionless and Inversion Mode Nanowire MOSFETs". ECS Meeting Abstracts MA2023-01, nr 33 (28.08.2023): 1872. http://dx.doi.org/10.1149/ma2023-01331872mtgabs.

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Nanowire transistors constitute an alternative for the continuous downscaling of MOSFETs. These devices present a trigate architecture featuring the fin width (WFIN) and height (HFIN) with similar dimensions, in the order of tenths of nanometers [1], which improves the gate control on the channel charges, reducing short-channel effects (SCE) and improves electrical properties in both digital and analog applications [1]. Junctionless nanowire transistors (JL) are easier to fabricate than inversion-mode MOSFETs [2]. They also are less vulnerable to the occurrence of SCE, which is one of the main concerns when downscaling the MOS transistor [3, 4]. Unlike inversion mode (IM) transistors, the junctionless device is made with a heavily doped silicon layer with the same doping type from source to drain [2, 5]. To lower the series resistance, the source and drain receive an additional doping step to increase their concentration. Although JL transistors are a good alternative for the continuous downscaling of MOS transistors, they still have their basic operation like any other transistor MOSFET. Therefore, it is not completely immune from SCE, such as Drain-Induced Barrier Lowering (DIBL) effect. In this work, a comparison between the DIBL effect in junctionless and inversion-mode nanowire transistors is performed. Experimental results at room and high temperatures are presented for devices with different channel widths. The JL and IM nanowire transistors used in this work were fabricated at CEA-Leti, as described in reference [6]. Devices with 10 parallel channels and channel length (L) of 40 nm and 100 nm were measured, fin width (WFIN) of 12 nm, 17 nm, 22 nm, and 42 nm. Two different values of drain voltage (VD) were applied for all devices, VD1 = 40 mV and VD2 = 800 mV. Finally, the DIBL has been calculated as DIBL=|VT2 – VT1| /(VD2 – VD1). The threshold voltage in both VD has been extracted as described in ref. [7]. The analysis for DIBL as a function of fin width is shown in Figure 1(A). For devices with L=100nm, no SCE has been observed and all devices present Subthreshold Slope (SS) close to the theoretical limit. Also, for WFIN up to 22 nm, DIBL is the same both for IM and JL nanowires. When downscaling the length to 40 nm, despite of DIBL increase for all devices, no degradation on SS is seen for JL, whereas IM devices exhibit SS>82mV/dec. Considering reasonable characteristics, i.e., DIBL=100mV/V and S=80 mV/dec [8], except from WFIN=42nm, all JL devices meet these requirements, whereas no IM nanowire with L=40 nm could be used. Even if maximum allowable DIBL were increased to 120mV/V, only the narrowest IM with L=40nm would be acceptable. Aiming to verify the influence of the temperature on the DIBL, Figure 1(B) shows the variation of DIBL in relation to room temperature for IM and JL nanowires with L=100nm and WFIN=12nm, which have similar DIBL at 300K. One can see that DIBL variation with temperature in the IM device is larger than in JL. While the IM transistor presented a DIBL variation of 0.15(mV/V)/K, for the JL one, it is 0.11(mV/V)/K. These results indicate that apart from the good immunity to SCE, JL nanowires are less susceptible to DIBL variation with temperature. Acknowledgements The authors thank financial support from CAPES, CNPq and FAPESP. References [1] T. A. Oproglidis, T. A. Karatsori, S. Barraud, G. Ghibaudo and C. A. Dimitriadis, Effect of Temperature on the Performance of Triple-Gate Junctionless Transistors, in IEEE Transactions on Electron Devices, vol.65, no.8, pp.3562-3566, 2018. [2] J.-P. Colinge et al, Junctionless Nanowire Transistor (JNT): Properties and design guidelines, Solid-State Electronics, Volumes 65–66, 2011, Pages 33-37. [3] J.-P. Colinge, Junctionless transistors, 2012 IEEE International Meeting for Future of Electron Devices, Kansai, 2012, pp. 1-2. [4] M. Ehteshamuddin, Sajad A. Loan and M. Rafat, Excellent DIBL Immunity in Junctionless Transistor on a High -k Buried, 2017 14th IEEE India Council International Conference (INDICON). [5] T. A. Ribeiro, M. A. Pavanello, Analysis of the electrical parameters of SOI junctionless nanowire transistors at high temperatures, Journal of the Electron Devices Society, April 2021. [6] D. Bosch et al., All-Operation-Regime Characterization and Modeling of Drain Current Variability in Junctionless and Inversion-Mode FDSOI Transistors, 2020 IEEE Symposium on VLSI Technology, 2020, pp. 1-2. [7] M. De Souza et al, Experimental Assessment of Variability in Junctionless Nanowire nMOS Transistors, ESSDERC 2021, pp. 223-226, 2021. [8] J.-W. Yang and J. G. Fossum, On the feasibility of nanoscale triple-gate CMOS transistors, in IEEE Transactions on Electron Devices, vol. 52, no. 6, pp. 1159-1164, June 2005. Figure 1
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Liu, Fayong, Kouta Ibukuro, Muhammad Khaled Husain, Zuo Li, Joseph Hillier, Isao Tomita, Yoshishige Tsuchiya, Harvey Rutt i Shinichi Saito. "Manipulation of random telegraph signals in a silicon nanowire transistor with a triple gate". Nanotechnology 29, nr 47 (25.09.2018): 475201. http://dx.doi.org/10.1088/1361-6528/aadfa6.

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Et.al, R. Jeyarohini. "A performance Analysis of DM-DG and TM-DG TFETs Analytical Models for Low Power Applications". Turkish Journal of Computer and Mathematics Education (TURCOMAT) 12, nr 3 (10.04.2021): 4642–51. http://dx.doi.org/10.17762/turcomat.v12i3.1874.

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Device Modeling is utilized to engendering incipient device models for the demeanor of the electrical devices predicated on fundamental physics. Modeling of the device may also include the creation of Compact models. An emerging device type of transistor is the Tunnel Field-Effect transistor that achieves compactness and speed during device modeling. This article presents an analytical comparative study of duel material DG TFETs and triple Material DG TFETs with gate oxide structure . Here the implementation of device modeling is done by solving Poisson’s equation with Parabolic Approximation Technique(PAT).The process of formulation of drain current(Id) model is based on integrating the BTBT generation. A Transconductance model of the device is additionally developed utilizing this drain current model of TFET. Surface potential is calculated by utilizing the channel potential model. The electrical properties like Surface potential〖(Ψ〗_(s,i)), Drain current (Id ), and Electric field(Ei) have been compared for both Duel material DG-TFET and Triple material DG-TFET. The comparison statement of DMDG-TFETs and TMDG-TFETs provide improved performance. The analytical model of the device results are compared with simulated results for DMDG TFET and TMDG TFET and good acquiescent is examined.
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Venkatesh, M., i N. B. Balamurugan. "New subthreshold performance analysis of germanium based dual halo gate stacked triple material surrounding gate tunnel field effect transistor". Superlattices and Microstructures 130 (czerwiec 2019): 485–98. http://dx.doi.org/10.1016/j.spmi.2019.05.016.

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Lima, Vitor Gonçalves, Guilherme Paim, Rodrigo Wuerdig, Leandro Mateus Giacomini Rocha, Leomar Da Rosa Júnior, Felipe Marques, Vinicius Valduga, Eduardo Costa, Rafael Soares i Sergio Bampi. "Enhancing Side Channel Attack-Resistance of the STTL Combining Multi-Vt Transistors with Capacitance and Current Paths Counterbalancing". Journal of Integrated Circuits and Systems 15, nr 1 (26.05.2020): 1–11. http://dx.doi.org/10.29292/jics.v15i1.100.

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Differential power analysis (DPA) exploits the difference between the instantaneous power of the circuit arches transitions to stole the state as information aiming to unveil the cryptographic key. Secure triple track logic (STTL) is a circuit-level countermeasure to DPA attacks based on dual-rail precharge logic (DPL). STTL is robust to attacks due to the delay in an insensitive feature that mitigates the logic glitches generated by the different path delays that lead to the logic gate inputs until they stabilize. The main STTL drawback, however, is the asymmetry of the transistor topology. Asymmetry causes unbalanced internal capacitances and different internal paths for the current flow, and DPA exploits it as a source of information leakage. Our work proposes three circuit topologies, combining multi-Vt transistors with a circuit counterbalancing strategy, aiming to improve the STTL DPA attack-resistance. Data encryption standard substitution-box circuit, designed in a TSMC 40 nm CMOS process, is our application case study to evaluate the DPA attack-resistance. Results gathered at the application-level show that our proposals outperform DPA attack-resistance of the prior work.
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Kumar, A., A. Chaudhry, V. Kumar i V. Sharma. "A Two Dimensional Surface Potential Model for Triple Material Double Gate Junctionless Field Effect Transistor". Journal of Nano- and Electronic Physics 8, nr 4(1) (2016): 04042–1. http://dx.doi.org/10.21272/jnep.8(4(1)).04042.

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Chien, Feng-Tso, Zhi-Zhe Wang, Cheng-Li Lin, Tsung-Kuei Kang, Chii-Wen Chen i Hsien-Chin Chiu. "150–200 V Split-Gate Trench Power MOSFETs with Multiple Epitaxial Layers". Micromachines 11, nr 5 (15.05.2020): 504. http://dx.doi.org/10.3390/mi11050504.

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A rating voltage of 150 and 200 V split-gate trench (SGT) power metal-oxide- semiconductor field-effect transistor (Power MOSFET) with different epitaxial layers was proposed and studied. In order to reduce the specific on-resistance (Ron,sp) of a 150 and 200 V SGT power MOSFET, we used a multiple epitaxies (EPIs) structure to design it and compared other single-EPI and double-EPIs devices based on the same fabrication process. We found that the bottom epitaxial (EPI) layer of a double-EPIs structure can be designed to support the breakdown voltage, and the top one can be adjusted to reduce the Ron,sp. Therefore, the double-EPIs device has more flexibility to achieve a lower Ron,sp than the single-EPI one. When the required voltage is over 100 V, the on-state resistance (Ron) of double-EPIs device is no longer satisfying our expectations. A triple-EPIs structure was designed and studied, to reduce its Ron, without sacrificing the breakdown voltage. We used an Integrated System Engineering-Technology Computer-Aided Design (ISE-TCAD) simulator to investigate and study the 150 V SGT power MOSFETs with different EPI structures, by modulating the thickness and resistivity of each EPI layer. The simulated Ron,sp of a 150 V triple-EPIs device is only 62% and 18.3% of that for the double-EPIs and single-EPI structure, respectively.
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Koide, Yasuo. "(Invited) Leading-Edge Diamond FET, MEMS, and Photodetector Devices". ECS Meeting Abstracts MA2023-02, nr 30 (22.12.2023): 1541. http://dx.doi.org/10.1149/ma2023-02301541mtgabs.

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Diamond is a candidate material for next-generation power electronics, micro-electro mechanical systems (MEMS), and solar-blind deep-ultraviolet (DUV) photodetector devices with excellent thermal stability and radiation hardness, which operate under extreme environment. In order to use an advantage of high-density hole channel of hydrogenated diamond (H-diamond) surface, we have developed the high-k stack gate dielectrics and AlN heterojuction gate for H-diamond FETs, such as HfO2/HfO2, LaAlO3/Al2O3 Ta2O5/Al2O3, and ZrO2/Al2O3, AlN/Al2O3 prepared by a combination of sputter-deposition (SD) and atomic layer deposition (ALD) techniques [1,2]. We also demonstrated the artificial diamond Fin-FETs with high-current level [3] and the nanolaminate insulator gate metal-oxide-gate FETs (MOSFETs) with k value as high as 100 [4], and the new transistor concept named by metal-insulator-metal-semiconductor field-effect transistor (MIMS-FET) to achieve normally-off operation by combining the advantages of MOSFET and metal-semiconductor FET [5]. In addition, we developed the routine ion-implantation process for preparing the diamond cantilever with a resonant frequency quality factor as high as one million [6,7]. We have also developed thermally stable Schottky barrier photodiode (SPD), metal-semiconductor-metal photodetector (MSMPD), and MSM-type SPD (IDF-SPD) with a large photoconductivity gain in DUV wavelength and a large discrimination ratio between DUV/visible light responsivity [8,9]. In this presentation, we will review the comprehensive our work on the diamond FET, MEMS, and photodetector devices. Acknowledgements: This work was in collaboration with J-W. Liu, M. Imura, M-Y. Liao, J. Alvarez in NIMS and A. Ouchiero and E. Obaldia in University of Taxes, Dallas, and partly supported by JSPS KAKENHI Grant Number 20H00313. References [1] Liu, M-Y. Liao, M. Imura, A. Tanaka, H. Iwai, Y. Koide, “Low on-resistance diamond field effect transistor with high-k ZrO2 as dielectric,” Sci. Reports, vol. 4, 6395-1 (2014). [2] Liu and Y. Koide, “An overview of high-k oxides on hydrogenated-diamond for metal-oxide-semiconductor capacitors and field-effect transistors.” SENSORS, 18, No.6, 813 (2018). [3] Liu, H. Ohsato, Bo Da, Y. Koide, "High Current Output Hydrogenated Diamond Triple-Gate MOSFETs," IEEE J. Electron Devices Society. 7, 561 (2019). [4] Liu, O. Auciello, E. de Obaldia, B. Da, Y. Koide, “Science and Technology of Integrated Super-High Dielectric Constant AlOx/TiOy Nanolaminates / Diamond for MOS Capacitors and MOSFETs,” Carbon. 172 112 (2021). [5] Liao, L. Sang, T. Shimaoka, M. Imura, S. Koizumi, Y. Koide, "Energy‐Efficient Metal–Insulator–Metal‐Semiconductor Field‐Effect Transistors Based on 2D Carrier Gases," Advanced Electronic Materials. 5 [5] (2019). [6] Liao, S. Hishita, E. Watanabe, S. Koizumi, Y. Koide, "Suspended single-crystal diamond nanowires for high-performance nanoelectro- mechanical switches." Adv. Mater. 22, 5393 (2010). [7] Wu, L. Sang, T. Teraji, T. Li, K. Wu, M. Imura, J. You, Y. Koide, M. Liao, "Reducing energy dissipation and surface effect of diamond nanoelectromechanical resonators by annealing in oxygen ambient," Carbon. 124, 281 (2017). [8] M. Liao, Y. Koide, and J. Alvarez, “Thermally Stable visible-blind Diamond Photodiode Using WC Schottky Contact,” Appl. Phys. Lett., 87, p. 0221051 (2005). [9] Liao and Y. Koide, "High-performance metal-semiconductor-metal deep-ultraviolet photodetectors based on homoepitaxial diamond thin film." Appl. Phys. Lett. 89, 113509 (2006).
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Kashem, Md Tashfiq Bin, i Samia Subrina. "Computational Analysis of Joule Heating Effect in Triple Material Gate AlGaN/GaN High Electron Mobility Transistor". ECS Transactions 102, nr 3 (7.05.2021): 43–52. http://dx.doi.org/10.1149/10203.0043ecst.

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Chawla, Tulika, Mamta Khosla i Balwinder Raj. "Design and simulation of triple metal double-gate germanium on insulator vertical tunnel field effect transistor". Microelectronics Journal 114 (sierpień 2021): 105125. http://dx.doi.org/10.1016/j.mejo.2021.105125.

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Kashem, Md Tashfiq Bin, i Samia Subrina. "Computational Analysis of Joule Heating Effect in Triple Material Gate AlGaN/GaN High Electron Mobility Transistor". ECS Meeting Abstracts MA2021-01, nr 33 (30.05.2021): 1074. http://dx.doi.org/10.1149/ma2021-01331074mtgabs.

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Mahdia, Marjana, i Quazi Deen Mohd Khosru. "Analytical modeling of transport phenomena in heterojunction triple metal gate all around tunneling field effect transistor". AIP Advances 10, nr 9 (1.09.2020): 095125. http://dx.doi.org/10.1063/5.0024864.

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Jeon, Jin-Hyeok, i Won-Ju Cho. "Triple Gate Polycrystalline-Silicon-Based Ion-Sensitive Field-Effect Transistor for High-Performance Aqueous Chemical Application". IEEE Electron Device Letters 40, nr 2 (luty 2019): 318–20. http://dx.doi.org/10.1109/led.2018.2890741.

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Mushtaq, Umar, Leo Raj Solay, S. Intekhab Amin i Sunny Anand. "Design and Analog Performance Analysis of Triple Material Gate Based Doping-Less Tunnel Field Effect Transistor". Journal of Nanoelectronics and Optoelectronics 14, nr 8 (1.08.2019): 1177–82. http://dx.doi.org/10.1166/jno.2019.2662.

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Boukortt, Nour El Islam, Baghdad Hadri, Alina Caddemi, Giovanni Crupi i Salvatore Patane. "Temperature Dependence of Electrical Parameters of Silicon-on-Insulator Triple Gate n-Channel Fin Field Effect Transistor". Transactions on Electrical and Electronic Materials 17, nr 6 (25.12.2016): 329–34. http://dx.doi.org/10.4313/teem.2016.17.6.329.

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Shringi, Shivangi, Ashish Raman, Sarabdeep Singh i Naveen Kumar. "Design and Analysis of Source Engineered with High Electron Mobility Material Triple Gate Junctionless Field Effect Transistor". Journal of Nanoelectronics and Optoelectronics 14, nr 6 (1.06.2019): 825–32. http://dx.doi.org/10.1166/jno.2019.2558.

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Saha, Priyanka, Rudra Sankar Dhar, Swagat Nanda, Kuleen Kumar i Moath Alathbah. "The Optimization and Analysis of a Triple-Fin Heterostructure-on-Insulator Fin Field-Effect Transistor with a Stacked High-k Configuration and 10 nm Channel Length". Nanomaterials 13, nr 23 (23.11.2023): 3008. http://dx.doi.org/10.3390/nano13233008.

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The recent developments in the replacement of bulk MOSFETs with high-performance semiconductor devices create new opportunities in attaining the best device configuration with drive current, leakage current, subthreshold swing, Drain-Induced Barrier Lowering (DIBL), and other short-channel effect (SCE) parameters. Now, multigate FETs (FinFET and tri-gate (TG)) are advanced methodologies to continue the scaling of devices. Also, strain technology is used to gain a higher current drive, which raises the device performance, and high-k dielectric material is used to minimize the subthreshold current. In this work, we used stacked high-k dielectric materials in a TG n-FinFET with three fins and a 10 nm channel length, incorporating a three-layered strained silicon channel to determine the short-channel effects. Here, we replaced the gate oxide (SiO2) with a stacked gate oxide of 0.5 nm of SiO2 with a 0.5 nm effective oxide thickness of different high-k dielectric materials like Si3N4, Al2O3, ZrO2, and HfO2. It was found that the use of strained silicon and replacing only the SiO2 device with the stacked SiO2 and HfO2 device was more beneficial to obtain an optimized device with the least leakage and improved drive currents.
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Baral, Biswajit, Aloke Kumar Das, Debashis De i Angsuman Sarkar. "An analytical model of triple-material double-gate metal-oxide-semiconductor field-effect transistor to suppress short-channel effects". International Journal of Numerical Modelling: Electronic Networks, Devices and Fields 29, nr 1 (9.01.2015): 47–62. http://dx.doi.org/10.1002/jnm.2044.

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Choudhury, Sagarika, Krishna Lal Baishnab, Koushik Guha, Zoran Jakšić, Olga Jakšić i Jacopo Iannacci. "Modeling and Simulation of a TFET-Based Label-Free Biosensor with Enhanced Sensitivity". Chemosensors 11, nr 5 (22.05.2023): 312. http://dx.doi.org/10.3390/chemosensors11050312.

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This study discusses the use of a triple material gate (TMG) junctionless tunnel field-effect transistor (JLTFET) as a biosensor to identify different protein molecules. Among the plethora of existing types of biosensors, FET/TFET-based devices are fully compatible with conventional integrated circuits. JLTFETs are preferred over TFETs and JLFETs because of their ease of fabrication and superior biosensing performance. Biomolecules are trapped by cavities etched across the gates. An analytical mathematical model of a TMG asymmetrical hetero-dielectric JLTFET biosensor is derived here for the first time. The TCAD simulator is used to examine the performance of a dielectrically modulated label-free biosensor. The voltage and current sensitivity of the device and the effects of the cavity size, bioanalyte electric charge, fill factor, and location on the performance of the biosensor are also investigated. The relative current sensitivity of the biosensor is found to be about 1013. Besides showing an enhanced sensitivity compared with other FET- and TFET-based biosensors, the device proves itself convenient for low-power applications, thus opening up numerous directions for future research and applications.
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Sharma, Dheeraj, Bhagwan Ram Raad, Dharmendra Singh Yadav, Pravin Kondekar i Kaushal Nigam. "Two‐dimensional potential, electric field and drain current model of source pocket hetero gate dielectric triple work function tunnel field‐effect transistor". Micro & Nano Letters 12, nr 1 (styczeń 2017): 11–16. http://dx.doi.org/10.1049/mnl.2016.0351.

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Venkatesh, M., M. Suguna i N. B. Balamurugan. "Subthreshold Performance Analysis of Germanium Source Dual Halo Dual Dielectric Triple Material Surrounding Gate Tunnel Field Effect Transistor for Ultra Low Power Applications". Journal of Electronic Materials 48, nr 10 (6.08.2019): 6724–34. http://dx.doi.org/10.1007/s11664-019-07492-0.

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Popov, Vladimir P., Valentin A. Antonov, Andrey V. Miakonkikh i Konstantin V. Rudenko. "Ion Drift and Polarization in Thin SiO2 and HfO2 Layers Inserted in Silicon on Sapphire". Nanomaterials 12, nr 19 (28.09.2022): 3394. http://dx.doi.org/10.3390/nano12193394.

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To reduce the built-in positive charge value at the silicon-on-sapphire (SOS) phase border obtained by bonding and a hydrogen transfer, thermal silicon oxide (SiO2) layers with a thickness of 50–310 nm and HfO2 layers with a thickness of 20 nm were inserted between silicon and sapphire by plasma-enhanced atomic layer deposition (PEALD). After high-temperature annealing at 1100 °C, these layers led to a hysteresis in the drain current–gate voltage curves and a field-induced switching of threshold voltage in the SOS pseudo-MOSFET. For the inserted SiO2 with a thickness of 310 nm, the transfer transistor characteristics measured in the temperature ranging from 25 to 300 °C demonstrated a triple increase in the hysteresis window with the increasing temperature. It was associated with the ion drift and the formation of electric dipoles at the silicon dioxide boundaries. A much slower increase in the window with temperature for the inserted HfO2 layer was explained by the dominant ferroelectric polarization switching in the inserted HfO2 layer. Thus, the experiments allowed for a separation of the effects of mobile ions and ferroelectric polarization on the observed transfer characteristics of hysteresis in structures of Si/HfO2/sapphire and Si/SiO2/sapphire.
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Borghei, Moein, i Mona Ghassemi. "Characterization of Partial Discharge Activities in WBG Power Converters under Low-Pressure Condition". Energies 14, nr 17 (30.08.2021): 5394. http://dx.doi.org/10.3390/en14175394.

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Many sectors, such as transportation systems, are undergoing rapid electrification due to the need for the mitigation of CO2 emissions. To ensure safe and reliable operation, the electrical equipment must be able to work under various environmental conditions. At high altitudes, the low pressure can adversely affect the health of insulating materials of electrical systems in electric aircraft. A well-known, primary aging mechanism in dielectrics is partial discharge (PD). This study targets internal PD evaluation in an insulated-gate bipolar transistor (IGBT) module under low-pressure conditions. The estimation of electric field distribution is conducted through 3D finite element analysis (FEA) using COMSOL Multiphysics®. The procedure of PD detection and transient modeling is performed in MATLAB for two pressure levels (atmospheric and half-atmospheric). The case study is the IGBT module with a void or two voids in the proximity of triple joints. The single-void case demonstrates that at half-atmospheric pressure, the intensity of discharges per voltage cycle increases by more than 40% compared to atmospheric pressure. The double-void case further shows that a void that is harmless at sea level can turn into an additional source of aging and couple with the other voids to escalate PD intensity by a factor of two or more.
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Choi, Sung-Hwan, Hee-Sun Shin i Min-Koo Han. "Novel F-Shaped Triple-Gate Structure for Suppression of Kink Effect and Improvement of Hot Carrier Reliability in Low-Temperature Polycrystalline Silicon Thin-Film Transistor". Japanese Journal of Applied Physics 48, nr 4 (20.04.2009): 04C155. http://dx.doi.org/10.1143/jjap.48.04c155.

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Tsutsumi, Toshiyuki. "Very low and broad threshold voltage fluctuation caused by ion implantation to silicon-on-insulator triple-gate fin-type field effect transistor using three-dimensional process and device simulations". Japanese Journal of Applied Physics 56, nr 6S1 (16.05.2017): 06GF12. http://dx.doi.org/10.7567/jjap.56.06gf12.

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NA, KYOUNG-IL, JUNG-HEE LEE, SORIN CRISTOLOVEANU, YOUNG-HO BAE, PAUL PATRUNO i WADE XIONG. "SHORT CHANNEL, FLOATING BODY, AND 3D COUPLING EFFECTS IN TRIPLE-GATE MOSFET". International Journal of High Speed Electronics and Systems 18, nr 04 (grudzień 2008): 773–82. http://dx.doi.org/10.1142/s0129156408005758.

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We have investigated the short-channel effect (SCE), floating-body effect, and three-dimensional coupling effect in triple-gate MOSFET with various fin widths, gate lengths and number of fins. It is found that the SCE of these devices is alleviated as the fin width shrinks and does not depend on the number of fins. The gate-induced floating-body effect (GIFBE) is visible even in fully depleted (FD) triple-gate transistors when the film-buried oxide (BOX) interface is swept from depletion to accumulation by the back-gate bias. The 3-D coupling effect in vertical, lateral, and longitudinal directions was investigated for different channel geometries. The biasing condition which enables the simultaneous activation of all channels and gives rise to volume inversion is discussed.
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Yang, J. W., i J. G. Fossum. "On the Feasibility of Nanoscale Triple-Gate CMOS Transistors". IEEE Transactions on Electron Devices 52, nr 6 (czerwiec 2005): 1159–64. http://dx.doi.org/10.1109/ted.2005.848109.

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CRISTOLOVEANU, SORIN, ROMAIN RITZENTHALER, AKIKO OHATA i OLIVIER FAYNOT. "3D Size Effects in Advanced SOI Devices". International Journal of High Speed Electronics and Systems 16, nr 01 (marzec 2006): 9–30. http://dx.doi.org/10.1142/s0129156406003515.

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Recent results on state-of-the-art SOI MOS transistors reveal the impact of the device miniaturization. The role of each dimension (length, width, thickness) is examined sequentially, by emphasizing the link with the other MOSFET dimensions. Ultra-thin gate oxide and silicon film enable, respectively, Gate-Induced Floating Body Effects (GIFBE) and super-coupling. In ultra-thin SOI films, the interface coupling effects are amplified leading to interesting consequences for carrier transport and multiple-gate operation. The self-heating problem in SOI MOSFETs can be alleviated by replacing the buried oxide with a different dielectric that offers improved thermal conductivity, without degrading the electrostatic behavior of the device. We describe the operation and scaling principles of transistors with double, triple or quadruple gates, which are governed by strong 3-D coupling effects.
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Teixeira, Fernando F., Caio C. M. Bordallo, Marcilei A. Guazzelli, Paula Ghedini Der Agopian, João Antonio Martino, Eddy Simoen i Cor Clayes. "Parasitic Conduction Response to X-ray Radiation in Unstrained and Strained Triple-Gate SOI MuGFETs". Journal of Integrated Circuits and Systems 9, nr 2 (28.12.2014): 97–102. http://dx.doi.org/10.29292/jics.v9i2.394.

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In this work, the X-ray irradiation impact on the back gate conduction and drain current for Triple-Gate SOI FinFETs is investigated for strained and unstrained devices. Both types (P and N) of transistors were analyzed. Since X-rays promote trapped positive charges in the buried oxide, the second interface threshold voltage shifts to lower gate voltage. The performance of n-channel devices presented a strong degradation when submitted to X-rays, while for p-channel devices the opposite trend was observed. Two different dose rates were analyzed.
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49

Doria, Rodrigo T., Renan D. Trevisoli, Michelly De Souza i Marcelo Antonio Pavanello. "Impact of the Series Resistance in the I-V Characteristics of Junctionless Nanowire Transistors and its dependence on the Temperature". Journal of Integrated Circuits and Systems 7, nr 2 (27.12.2012): 121–29. http://dx.doi.org/10.29292/jics.v7i2.364.

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The effect of the source/drain parasitic resistance (RS) on the I-V characteristics of Junctionless Nanowire Transistors (JNTs) has been evaluated through experimental and simulated data. The impact of several parameters such as the temperature, the fin width, the total doping concentration, the source/drain length and the source/drain doping concentration on RS has been addressed. The source/drain parasitic resistance presented by JNTs was compared to the one presented by classical inversion mode (IM) triple gate devices, showing opposite behavior with the temperature variation in IM triple transistors and JNTs. In the latter, a reduction on RS is noted with the temperature increase, which is related to the incomplete ionization. This effect inhibits the presence of a Zero Temperature Coefficient (ZTC) operation bias in the Junctionless devices.
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50

Park, Taeho, Kyoungah Cho i Sangsig Kim. "Temperature-Dependent Feedback Operations of Triple-Gate Field-Effect Transistors". Nanomaterials 14, nr 6 (9.03.2024): 493. http://dx.doi.org/10.3390/nano14060493.

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In this study, we examine the electrical characteristics of triple-gate feedback field-effect transistors (TG FBFETs) over a temperature range of −200 °C to 280 °C. With increasing temperature from 25 °C to 280 °C, the thermally generated charge carriers increase in the channel regions such that a positive feedback loop forms rapidly. Thus, the latch-up voltage shifts from −1.01 V (1.34 V) to −11.01 V (10.45 V) in the n-channel (p-channel) mode. In contrast, with decreasing temperature from 25 °C to −200 °C, the thermally generated charge carriers decrease, causing a shift in the latch-up voltage in the opposite direction to that of the increasing temperature case. Despite the shift in the latch-up voltage, the TG FBFETs exhibit ideal switching characteristics, with subthreshold swings of 6.6 mV/dec and 7.2 mV/dec for the n-channel and p-channel modes, respectively. Moreover, the memory window widens with increasing temperature. Specifically, at temperatures above 85 °C, the memory windows are wider than 3.05 V and 1.42 V for the n-channel and p-channel modes, respectively.
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