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Artykuły w czasopismach na temat „Trigger Processor”

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Data publikacji: 11 lutego 2024

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1

Asner, M., V. Papadimitriou, H. Sanders, J. Ting, Y. W. Wah i E. Weatherhead. "A cluster-finding trigger processor". Nuclear Instruments and Methods in Physics Research Section A: Accelerators, Spectrometers, Detectors and Associated Equipment 291, nr 3 (czerwiec 1990): 577–86. http://dx.doi.org/10.1016/0168-9002(90)90007-s.

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Lee, C., G. Miller, D. M. Kaplan, J. Sa, Y. B. Hsiung, T. Carey i R. Jeppesen. "A parallel pipelined dataflow trigger processor". IEEE Transactions on Nuclear Science 38, nr 2 (kwiecień 1991): 461–70. http://dx.doi.org/10.1109/23.289340.

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3

Baird, S. A., N. Bains, D. Campbell, M. Cawthraw, D. Charlton, J. Coughlan, E. Eisenhandler i in. "The new UA1 calorimeter trigger processor". IEEE Transactions on Nuclear Science 36, nr 1 (1989): 364–69. http://dx.doi.org/10.1109/23.34465.

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4

Sheaff, Marleigh. "A specialized second level trigger processor". Nuclear Instruments and Methods in Physics Research Section A: Accelerators, Spectrometers, Detectors and Associated Equipment 263, nr 1 (styczeń 1988): 196–98. http://dx.doi.org/10.1016/0168-9002(88)91034-0.

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5

Bains, N., S. A. Baird, P. Biddulph, D. Campbell, M. Cawthraw, D. Charlton, J. Coughlan i in. "The UA1 upgrade calorimeter trigger processor". Nuclear Instruments and Methods in Physics Research Section A: Accelerators, Spectrometers, Detectors and Associated Equipment 292, nr 2 (lipiec 1990): 401–23. http://dx.doi.org/10.1016/0168-9002(90)90396-n.

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6

Amaral, P. B., N. Ellis, P. Farthouat, P. Gallno, H. P. Lima, T. Maeno, I. R. Arcas i in. "The ATLAS local trigger processor (LTP)". IEEE Transactions on Nuclear Science 52, nr 4 (sierpień 2005): 1202–6. http://dx.doi.org/10.1109/tns.2005.852647.

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7

Perrella, S., Y. Afik, A. Armbruster, P. Czodrowski, N. Ellis, S. Haas, A. Koulouris i in. "Integration and commissioning of the ATLAS Muon-to-Central-Trigger-Processor Interface for Run-3". Journal of Instrumentation 17, nr 04 (1.04.2022): C04006. http://dx.doi.org/10.1088/1748-0221/17/04/c04006.

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Abstract The Muon-to-Central Trigger Processor Interface was completely redesigned as part of the ATLAS Level-1 trigger upgrade for Run 3 of the Large Hadron Collider. The new system is implemented as a single AdvancedTCA module, using three large state-of-the-art FPGAs and high-density fiber-optic modules. Trigger information from the muon trigger detectors are received through 208 high speed links, while 60 links are used to send processed trigger information to the L1 Topological Trigger Processor and the Central Trigger Processor. Extensive integration tests with all input and output systems have shown that the data transfer is stable and reliable. We present results from integration tests with connected sub-systems as well as commissioning of the Muon-to-Central Trigger Processor Interface in the ATLAS experiment.

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8

Koulouris, A., Y. Afik, A. Armbruster, P. Czodrowski, N. Ellis, S. Haas, A. Kulinska i in. "Commissioning of the new muon-to-central-trigger-processor interface at ATLAS". Journal of Instrumentation 18, nr 03 (1.03.2023): C03020. http://dx.doi.org/10.1088/1748-0221/18/03/c03020.

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Abstract The ATLAS trigger system includes a Level-1 (L1) trigger based on custom electronics and firmware, and a high-level software trigger running on off-the-shelf hardware. The L1 trigger system uses information from the forward detectors, the calorimeters and the muon trigger detectors. Once information from all muon trigger sectors has been received, trigger candidate multiplicities are calculated by the Muon-to-Central-Trigger-Processor Interface (MUCTPI). Muon multiplicity information is sent to the Central-Trigger-Processor (CTP) and trigger objects are sent to the L1 Topological Trigger Processor (L1Topo). The CTP combines the information received from the MUCTPI with the trigger information from the forward detectors, the calorimeters and the L1Topo, and takes the L1 trigger decision. As part of the ATLAS L1 trigger system upgrade for Run-3 of the Large Hadron Collider (LHC) a new MUCTPI has been designed and commissioned. We discuss the commissioning and operation of the new MUCTPI used in ATLAS from the beginning of Run-3. In particular, we describe the integration tests which have been carried out for the commissioning and operation of the new MUCTPI.

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9

Krivda, M., D. Alexandre, L. S. Barnby, D. Evans, P. G. Jones, A. Jusko, R. Lietava, J. Pospíšil i O. Villalobos Baillie. "The ALICE Central Trigger Processor (CTP) upgrade". Journal of Instrumentation 11, nr 03 (23.03.2016): C03051. http://dx.doi.org/10.1088/1748-0221/11/03/c03051.

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10

Bains, N., S. A. Baird, D. Campbell, M. Cawthraw, D. Charlton, J. Coughlan, E. Eisenhandler i in. "UA1 upgrade first-level calorimeter trigger processor". Nuclear Instruments and Methods in Physics Research Section A: Accelerators, Spectrometers, Detectors and Associated Equipment 279, nr 1-2 (lipiec 1989): 297–304. http://dx.doi.org/10.1016/0168-9002(89)91097-8.

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11

Soldi, D., i S. Chiozzi. "Level Zero Trigger Processor for the NA62 experiment". Journal of Instrumentation 13, nr 05 (2.05.2018): P05004. http://dx.doi.org/10.1088/1748-0221/13/05/p05004.

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12

Dawson, J. W., R. L. Talaga, G. W. Burr, R. J. Laird, W. Smith i J. Lackey. "First-level trigger processor for the ZEUS calorimeter". IEEE Transactions on Nuclear Science 37, nr 6 (1990): 2198–202. http://dx.doi.org/10.1109/23.101256.

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13

Zhang, S. N., R. Van Berg, T. Trojak, B. Cox, S. Conetti, A. Blankman, S. Borodin, L. Kaplan, W. Kononenko i W. Selove. "A high P/sub T/ muon trigger processor". IEEE Transactions on Nuclear Science 39, nr 4 (1992): 814–20. http://dx.doi.org/10.1109/23.159713.

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14

Korhonen, T., H. Sakamoto i Y. Watase. "Parallel processor trigger with distributed real-time kernel". IEEE Transactions on Nuclear Science 38, nr 2 (kwiecień 1991): 486–90. http://dx.doi.org/10.1109/23.289344.

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15

Frenkel, A., G. Martellotti, E. Petrolo, A. Tusi, F. Cesaroni, M. De Vincenzi, A. Sciubba i R. Roosen. "A hardware processor for a missing energy trigger". Nuclear Instruments and Methods in Physics Research Section A: Accelerators, Spectrometers, Detectors and Associated Equipment 245, nr 1 (kwiecień 1986): 45–50. http://dx.doi.org/10.1016/0168-9002(86)90256-1.

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16

Dawson, J. W., R. L. Talaga, G. W. Burr, R. J. Laird, W. Smith i J. Lackey. "First-level Trigger Processor For The Zeus Calorimeter". IEEE Transactions on Nuclear Science 37, nr 6 (grudzień 1990): 2198–202. http://dx.doi.org/10.1109/tns.1990.574214.

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17

Wolanski, M., S. J. Freedman, J. W. Dawson, W. N. Haberichter, K. C. Chan, A. A. Chishti, N. I. Kaloskamis i C. J. Lister. "Trigger processor for the APEX positron-electron spectrometer". Nuclear Instruments and Methods in Physics Research Section A: Accelerators, Spectrometers, Detectors and Associated Equipment 361, nr 1-2 (lipiec 1995): 326–37. http://dx.doi.org/10.1016/0168-9002(95)00139-5.

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18

Cavestro, A., D. Gibin, A. Guglielmi, M. Laveder, M. Mezzetto, G. Puglierin i M. Vascon. "A fast trigger processor for limited streamer tubes". Nuclear Instruments and Methods in Physics Research Section A: Accelerators, Spectrometers, Detectors and Associated Equipment 364, nr 2 (październik 1995): 328–32. http://dx.doi.org/10.1016/0168-9002(95)00435-1.

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19

Spiwoks, Ralf, Aaron Armbruster, German Carrillo-Montoya, Magda Chelstowska, Patrick Czodrowski, Pier-Olivier Deviveiros, Till Eifert i in. "Run Control Software For The Upgrade Of The Atlas Muon To Central Trigger Processor Interface (MUCTPI)". EPJ Web of Conferences 214 (2019): 01034. http://dx.doi.org/10.1051/epjconf/201921401034.

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The Muon to Central Trigger Processor Interface (MUCTPI) of the ATLAS experiment at the Large Hadron Collider(LHC) at CERN is being upgraded for the next run of the LHC in order to use optical inputs and to provide full-precision information for muon candidates to the topological trigger processor (L1TOPO) of the Level-1 trigger system. The new MUCTPI is implemented as a single ATCA blade with high-end processing FPGAs which eliminate doublecounting of muon candidates in overlapping regions, send muon candidates to L1TOPO, and muon multiplicities tothe Central Trigger Processor (CTP), as well as readout data to the data acquisition system of the experiment. A Xilinx Zynq System-on-Chip (SoC) with a programmable logic part and a processor part is used for the communication to the processing FPGAs and the run control system. The processor part, based on ARM processor cores, is running embedded Linux prepared using the framework of the Linux Foundation's Yocto project. The ATLAS run control software was ported to the processor part and a run control application was developed which receives, at configuration, all data necessary for the overlap handling and candidate counting of the processing FPGAs. During running, the application provides ample monitoring of the physics data and of the operation of the hardware. *

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20

Linnemann, James T. "The D0 Level 2 Trigger". International Journal of Modern Physics A 16, supp01c (wrzesień 2001): 1166–68. http://dx.doi.org/10.1142/s0217751x01009211.

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The D0 Level 2 trigger (L2), a subsystem of the three-stage D0 trigger, reduces event rates from 10 KHz to 1 KHz. The system is organized as a global processor and preprocessors for the calorimeter, muon, tracker, and preshower subsystems. Preprocessors digest information from a single detector system and produce a list of the objects. The global processor receives the object lists, matches across detectors, and applies selection criteria to the objects. The system can buffer 16 events. The L2 design has been guided by extensive queuing simulations. The system is presently being commissioned, with all components available as either pre-production or production boards.

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21

Hallsall, R., S. Jaroslawski, S. Madani, G. P. Heath, H. H. Wills, M. A. Lancaster, P. Shield i I. M. Silvester. "The ZEUS central tracking detector first level trigger processor". IEEE Transactions on Nuclear Science 37, nr 3 (czerwiec 1990): 1203–7. http://dx.doi.org/10.1109/23.57367.

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22

Chiozzi, S., E. Gamberini, A. Gianoli, G. Mila, I. Neri, F. Petrucci i D. Soldi. "The Level 0 Trigger Processor for the NA62 experiment". Nuclear Instruments and Methods in Physics Research Section A: Accelerators, Spectrometers, Detectors and Associated Equipment 824 (lipiec 2016): 324–25. http://dx.doi.org/10.1016/j.nima.2015.09.118.

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23

Appelquist, G., B. Hovander, B. Selldén i C. Bohm. "A programmable systolic trigger processor for FERA bus data". Nuclear Instruments and Methods in Physics Research Section A: Accelerators, Spectrometers, Detectors and Associated Equipment 327, nr 2-3 (kwiecień 1993): 489–99. http://dx.doi.org/10.1016/0168-9002(93)90715-t.

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24

Dzhelyadin, R., S. Erhan, E. P. Hartouni, M. Medinnis, J. G. Zweizig, R. Dzhelyadin, S. Erhan i in. "RD21: test of a silicon data-driven trigger processor". Nuclear Instruments and Methods in Physics Research Section A: Accelerators, Spectrometers, Detectors and Associated Equipment 351, nr 1 (listopad 1994): 228–35. http://dx.doi.org/10.1016/0168-9002(94)91085-5.

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25

Martínez, Carlos Moreno. "The ATLAS Level-1 topological processor: Experience and upgrade plans". International Journal of Modern Physics A 35, nr 34n35 (18.12.2020): 2044008. http://dx.doi.org/10.1142/s0217751x2044008x.

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During Run 2 (2015–2018) the Large Hadron Collider has provided, at the World’s highest energy frontier, proton–proton collisions to the ATLAS experiment with high instantaneous luminosity (up to [Formula: see text]), placing stringent operational and physics requirements on the ATLAS trigger system in order to reduce the 40 MHz collision rate to a manageable event storage rate of 1 kHz, while not rejecting interesting collisions. The Level-1 trigger is the first rate-reducing step in the ATLAS trigger system with an output rate of up to 100 kHz and decision latency of less than 2.5 [Formula: see text]s. In Run 2, an important role was played by the Level-1 Topological Processor (L1Topo). This innovative system consists of two blades designed in AdvancedTCA form factor, mounting four individual state-of-the-art processors, and providing high input bandwidth and low latency data processing. Up to 128 topological trigger algorithms can be implemented to select interesting events by applying kinematic and angular requirements on electromagnetic clusters, hadronic jets, muons and total energy reconstructed in the ATLAS apparatus. This resulted in a significantly improved background rejection and enhanced acceptance of physics signal events, despite the increasing luminosity. The L1Topo system has become more and more important for physics analyses making use of low energy objects, commonly present in the Heavy Flavor or Higgs physics events, for example. An overview of the L1Topo architecture, simulation and performance results during Run 2 is presented alongside with upgrade plans for the L1Topo system to be installed for the future Run 3 data taking period.

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26

Anders, G., D. Berge, H. Bertelsen, M. Dam, E. Dobson, N. Ellis, P. Farthouat i in. "The upgrade of the ATLAS Level-1 Central Trigger Processor". Journal of Instrumentation 8, nr 01 (30.01.2013): C01049. http://dx.doi.org/10.1088/1748-0221/8/01/c01049.

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27

Ammendola, Roberto, Andrea Biagioni, Andrea Ciardiello, Paolo Cretaro, Ottorino Frezza, Gianluca Lamanna, Francesca Lo Cicero i in. "L0TP+: the Upgrade of the NA62 Level-0 Trigger Processor". EPJ Web of Conferences 245 (2020): 01017. http://dx.doi.org/10.1051/epjconf/202024501017.

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The L0TP+ initiative is aimed at the upgrade of the FPGA-based Level-0 Trigger Processor (L0TP) of the NA62 experiment at CERN for the post-LS2 data taking, which is expected to happen at 100% of design beam intensity, corresponding to about 3.3 × 1012 protons per pulse on the beryllium target used to produce the kaons beam. Although tests performed at the end of 2018 showed a substantial robustness of the L0TP system also at full beam intensity, there are several reasons to motivate such an upgrade: i) avoid FPGA platform obsolescence, ii) make room for improvements in the firmware design leveraging a more capable FPGA device, iii) add new functionalities, iv) support the 4 beam intensity increase foreseen in future experiment upgrades. We singled out the Xilinx Virtex UltraScale+ VCU118 development board as the ideal platform for the project. L0TP+ seamless integration into the current NA62 TDAQ system and exact matching of L0TP functionalities represent the main requirements and focus of the project; nevertheless, the final design will include additional features, such as a PCIe RDMA engine to enable processing on CPU and GPU accelerators, and the partial reconfiguration of trigger firmware starting from a high level language description (C/C++). The latter capability is enabled by modern High Level Synthesis (HLS) tools, but to what extent this methodology can be applied to perform complex tasks in the L0 trigger, with its stringent latency requirements and the limits imposed by single FPGA resources, is currently being investigated. As a test case for this scenario we considered the online reconstruction of the RICH detector rings on an HLS generated module, using a dedicated primitives data stream with PM hits IDs. Besides, the chosen platform supports the Virtex Ultrascale+ FPGA wide I/O capabilities, allowing for straightforward integration of primitive streams from additional sub-detectors in order to improve the performance of the trigger.

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28

Zioulas, G., M. Arenton, T. Y. Chen, S. Conetti, B. Cox, S. Delchamps, B. Etemadi i in. "An on-line trigger processor for large transverse energy events". IEEE Transactions on Nuclear Science 36, nr 1 (1989): 375–79. http://dx.doi.org/10.1109/23.34467.

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29

Zweizig, J. G., J. B. Cheze, J. Ellett, S. Erhan, R. Jackson, M. Medinnis, P. E. Schlein i J. Zsembery. "Test of a data-driven trigger processor for experiment UA8". Nuclear Instruments and Methods in Physics Research Section A: Accelerators, Spectrometers, Detectors and Associated Equipment 263, nr 1 (styczeń 1988): 188–95. http://dx.doi.org/10.1016/0168-9002(88)91033-9.

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Zhongqiang, Yu, Sheng Junpeng, Guo Yanan, Ding Huiliang, Yang Xirong i Dong Aiping. "A fast track finding trigger processor for the BES detector". Nuclear Instruments and Methods in Physics Research Section A: Accelerators, Spectrometers, Detectors and Associated Equipment 265, nr 1-2 (marzec 1988): 336–41. http://dx.doi.org/10.1016/0168-9002(88)91088-1.

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31

Geralis, T., S. Kyriazopoulou, C. Markou, I. Michailakis i K. Zachariadou. "The global trigger processor emulator system for the CMS experiment". IEEE Transactions on Nuclear Science 52, nr 5 (październik 2005): 1679–84. http://dx.doi.org/10.1109/tns.2005.852650.

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Han, Yong Qi, Li Ma i Hong Liang Guo. "Design of Monitoring Alarm System Based on GPRS MMS". Advanced Materials Research 1049-1050 (październik 2014): 2149–52. http://dx.doi.org/10.4028/www.scientific.net/amr.1049-1050.2149.

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This system based on embedded technology, MMS wireless communication, etc. Various kinds of modern technology, design a kind of based on GPRS MMS remote monitoring alarm system, this system chooses LPC2132 chip as embedded processor, serial ports, camera, GPRS and infrared pyroelectric sensor module and other hardware. Main funtions as follows: when someone illegally broken into specific space abnormal happens, infrared pyroelectric sensor embedded processor immediately trigger caused disruption, the camera automatically shooting scene image, and transferred to the embedded processor module, embedded processor calls AT instructions through GPRS networks will the collected pictures sent to specify users mobile phone. Users can call or send messages to the system for pictures, but also through the mobile terminal control the system protection and removal. System software embedded in part using development platform ADS development, the key technology was embedded processor interrupt trigger, user instruction processing, control the acquisition and sending MMS etc. This paper analyses the working principle, AT GPRS directive system structure of use, embedded in space, thus realize user of real-time monitoring and alarm.

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33

Kluge, A., i T. Wildschek. "Feasibility of the hardware muon trigger track finder processor in CMS". IEEE Transactions on Nuclear Science 46, nr 2 (kwiecień 1999): 78–91. http://dx.doi.org/10.1109/23.757193.

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Gustafsson, L., i E. Hagberg. "A fast trigger processor, for a scattering experiment, implemented in fastbus". Nuclear Instruments and Methods in Physics Research Section A: Accelerators, Spectrometers, Detectors and Associated Equipment 265, nr 3 (marzec 1988): 521–32. http://dx.doi.org/10.1016/s0168-9002(98)90023-7.

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Medcalf, T., M. R. Saich i J. A. Strong. "A dedicated TPC track processor for the Aleph second level trigger". Nuclear Instruments and Methods in Physics Research Section A: Accelerators, Spectrometers, Detectors and Associated Equipment 277, nr 2-3 (maj 1989): 358–67. http://dx.doi.org/10.1016/0168-9002(89)90764-x.

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Carter, A. A., J. R. Carter, R. D. Heuer, S. Jaroslawski, A. Wagner i D. R. Ward. "A fast track trigger processor for the opal detector at LEP". Nuclear Instruments and Methods in Physics Research Section A: Accelerators, Spectrometers, Detectors and Associated Equipment 250, nr 3 (wrzesień 1986): 503–13. http://dx.doi.org/10.1016/0168-9002(86)91101-0.

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Curatolo, M., B. Esposito, G. Franchi i A. Teodoli. "The design of a level 1 tracking trigger processor for LHC". Nuclear Physics B - Proceedings Supplements 32 (maj 1993): 321–26. http://dx.doi.org/10.1016/0920-5632(93)90041-4.

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Bachtis, M., D. Campos, J. Jones i M. Tepper. "The Octopus processor for the CMS L1 muon trigger for High Luminosity LHC". Journal of Instrumentation 17, nr 03 (1.03.2022): C03025. http://dx.doi.org/10.1088/1748-0221/17/03/c03025.

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Abstract The upgraded L1 muon trigger system of the CMS experiment in the High Luminosity Large Hadron Collider is based on custom processors featuring large Field Programmable Gate Arrays (FPGAs) connected by large numbers of optical links. These provide the I/O bandwidth and power necessary to process the complex algorithms used during the collection of physics data. The design and performance requirements of these processors creates significant challenges in signal integrity, power delivery, and thermal management. In this paper we describe the Octopus processor, featuring a large Xilinx Virtex Ultrascale+ FPGA and up to 128 links interfaced to optics through high quality twin-ax copper cables. Results on signal integrity at 25 Gb/s and the first demonstration of 50+ Gb/s links with pluggable optics in CMS are also shown, demonstrating bit error rates below 10−15 at a 95% confidence level. The thermal performance is measured inside an Advanced-TCA crate with acceptable thermal margins up to 200 W of chip power. Future improvements are mentioned, potentially allowing operation at up to 300 W.

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39

Sundararajan, P., i K. Ntekas. "New developments in the MDT trigger processor for the ATLAS Level-0 muon trigger at High Luminosity LHC". Journal of Instrumentation 18, nr 02 (1.02.2023): C02030. http://dx.doi.org/10.1088/1748-0221/18/02/c02030.

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Abstract The High Luminosity LHC (HL-LHC) will have an instantaneous luminosity 5–7 times higher than LHC. The ATLAS detector, trigger and data acquisition systems will undergo a significant upgrade to cope with the increased particle rate. The upgrade of the ATLAS first-level muon trigger for High-Luminosity LHC foresees incorporating the high-resolution tracking capability of the Monitored Drift Tubes (MDT) in the current system based on Resistive Plate Chambers and Thin Gap Chambers. The MDT Trigger Processor (MDTTP) processes muon trigger candidates along with MDT hits to improve the accuracy of the transverse momentum calculation at the first-level (level-0) of the muon trigger. One of the major challenges is the capability to process all candidates in a bunch crossing within a tight latency constraint. The MDTTP hardware is based on the Apollo ATCA platform [6]. A complete hardware demonstrator is available and an updated prototype has been recently developed. Recent updates in the firmware development, integration and testing are presented.

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40

Ammendola, R., D. Battista, G. Paoluzzi, A. Salamon, R. Aliberti, M. Barbanera, V. Bonaiuto i in. "The NA62 level 0 calorimetric trigger fast readout implementation, commissioning and data taking performances". Journal of Instrumentation 18, nr 02 (1.02.2023): C02049. http://dx.doi.org/10.1088/1748-0221/18/02/c02049.

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Abstract The NA62 experiment at the CERN SPS aims to measure the branching ratio of the very rare kaon decay K + → π + ν ν ¯ . The Calorimetric Level 0 Trigger identifies clusters in the electromagnetic and hadronic calorimeters. Along with the trigger data sent to the L0 Trigger Processor, readout data is collected to be sent to the L1 software trigger. In this work we present the novel implementation of the readout data collection and forwarding system in the multiple layers of the calorimetric trigger structure. We will also present the commissioning of the system and the performance evaluation on current data taking.

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Bestintzanos, I., K. Adamidis, I. Euaggelou, C. Fernandez Bedoya, C. Foudas, A. Lymperakis, N. Manthos i in. "An ATCA processor for Level-1 trigger primitive generation and readout of the CMS barrel muon detectors". Journal of Instrumentation 18, nr 02 (1.02.2023): C02039. http://dx.doi.org/10.1088/1748-0221/18/02/c02039.

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Abstract An ATCA processor was designed to instrument the first layer of the CMS Barrel Muon Trigger. The processor receives and processes DT and RPC data and produces muon track segments. Furthermore, it provides readout for the DT detector. The ATCA processor is based on a Xilinx XCVU13P FPGA, receives data via 10 Gbps optical links and transmits track segments via 25 Gbps optical links. The processor is instrumented with a Zynq Ultrascale+ SoM connected with an SSD which provides the necessary resources for enhanced monitoring and control information. The design of the board as well as results on its performance are presented.

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Chiozzi, S., E. Gamberini, A. Gianoli, G. Mila, I. Neri, F. Petrucci i D. Soldi. "Level Zero Trigger processor for the ultra rare kaon decay experiment—NA62". Journal of Instrumentation 11, nr 02 (12.02.2016): C02037. http://dx.doi.org/10.1088/1748-0221/11/02/c02037.

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Bonaiuto, V., L. Federici, A. Fucci, G. Paoluzzi, A. Salamon, G. Salina, E. Santovetti, F. Sargeni i S. Venditti. "Status of the NA62 liquid krypton electromagnetic calorimeter Level 0 trigger processor". Journal of Instrumentation 8, nr 02 (27.02.2013): C02054. http://dx.doi.org/10.1088/1748-0221/8/02/c02054.

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Bramhall, M., S. Jaroslawski, A. Penton, R. Hammarstrom, D. Joos i C. Weber. "A fast track trigger processor for the OPAL experiment at LEP, CERN". IEEE Transactions on Nuclear Science 36, nr 1 (1989): 380–83. http://dx.doi.org/10.1109/23.34468.

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Köbis, S., P. Achenbach, R. Geiges, K. Grimm, D. v. Harrach, H. Hofmann, J. Hoffmann i in. "The analog trigger processor for the new parity violation experiment at mami". Nuclear Physics B - Proceedings Supplements 61, nr 3 (luty 1998): 625–29. http://dx.doi.org/10.1016/s0920-5632(97)00629-4.

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Soldi, Dario, S. Chiozzi, E. Gamberini, A. Gianoli, G. Mila, I. Neri i F. Petrucci. "Level Zero Trigger Processor for the ultra rare kaon decay experiment: NA62". Nuclear Instruments and Methods in Physics Research Section A: Accelerators, Spectrometers, Detectors and Associated Equipment 845 (luty 2017): 623–27. http://dx.doi.org/10.1016/j.nima.2016.06.090.

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Johnson, M. "Trigger processor algorithm for a tracking detector in a solenoidal magnetic field". IEEE Transactions on Nuclear Science 51, nr 5 (październik 2004): 2373–78. http://dx.doi.org/10.1109/tns.2004.836066.

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Loukas, N., S. Goadhouse, T. Anderson, A. Belloni, T. Gorski, T. Grassi, J. Hakala i in. "The CMS Barrel Calorimeter Processor demonstrator (BCPv1) board evaluation". Journal of Instrumentation 17, nr 08 (1.08.2022): C08005. http://dx.doi.org/10.1088/1748-0221/17/08/c08005.

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Abstract For the CERN LHC phase 2, the barrel region of the CMS electromagnetic (ECAL EB) and hadronic calorimeters (HCAL HB) require new back-end electronics for their readout. To this purpose, a first version of the ATCA-based blade, the Barrel Calorimeter Processor (BCPv1), has been developed. The performance of the optical links as well as clock distribution are also presented here. The BCPv1 has been tested together with front-end and trigger boards, as well as with the new DAQ and TCDS Hub (DTH) [1], to demonstrate that the BCPv1 meets the required specifications.

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Ammendola, R., A. Biagioni, A. Ciardiello, P. Cretaro, O. Frezza, G. Lamanna, F. Lo Cicero i in. "Progress report on the online processing upgrade at the NA62 experiment". Journal of Instrumentation 17, nr 04 (1.04.2022): C04002. http://dx.doi.org/10.1088/1748-0221/17/04/c04002.

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Abstract A new FPGA-based low-level trigger processor has been installed at the NA62 experiment. It is intended to extend the features of its predecessor due to a faster interconnection technology and additional logic resources available on the new platform. With the aim of improving trigger selectivity and exploring new architectures for complex trigger computation, a GPU system has been developed and a neural network on FPGA is in progress. They both process data streams from the ring imaging Cherenkov detector of the experiment to extract in real time high level features for the trigger logic. Description of the systems, latest developments and design flows are reported in this paper.

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WANG, S. M., D. ACOSTA, A. MADORSKY, B. SCURLOCK, A. ATAMANCHUK, V. GOLOVTSOV i B. RAZMYSLOVICH. "A PROTOTYPE TRACK-FINDING PROCESSOR FOR THE LEVEL-1 TRIGGER OF THE CMS ENDCAP MUON SYSTEM". International Journal of Modern Physics A 16, supp01c (wrzesień 2001): 1178–80. http://dx.doi.org/10.1142/s0217751x01009259.

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We report on the development and performance of a novel track-finding processor for the Level-1 trigger of the CMS endcap muon system. The processor links track segments identified in the cathode-strip chambers of the endcap muon system into complete three-dimensional tracks. It then measures the momentum of the best track candidates from the sagitta measured between three muon chambers in the endcap fringe field. The processor is pipelined at 40 MHz, and has an overall latency of 400 ns. The logic for the prototype is implemented in high-density FPGAs and SRAM memory. It receives approximately 3 gigabytes of data every second from a custom backplane operating at 280 MHz. Test results of the prototype are consistent with expectation.

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