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Gotowe bibliografie tematyczne / Translation Lookaside Buffers

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Gotowa bibliografia na temat „Translation Lookaside Buffers”

Autor: Grafiati

Data publikacji: 6 września 2023

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Artykuły w czasopismach na temat "Translation Lookaside Buffers"

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SAGAHYROON, ASSIM, i AHMED H. MOHAMED. "RESIZABLE TRANSLATION STORAGE BUFFERS". Journal of Circuits, Systems and Computers 15, nr 02 (kwiecień 2006): 169–81. http://dx.doi.org/10.1142/s0218126606003027.

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A translation lookaside buffer (TLB) is a high-speed associative cache of recently used virtual-to-physical address translations. The operating system can deal with a TLB miss through software trap handling. A possible technique for such software trap handling uses translation storage buffers (TSBs). A TSB is an operating system data structure that caches the most recent address translations. On a TLB miss, the TLB trap handler searches the TSB for the missing address translation. If the search generates a hit, the address mapping is added to the TLB. In current implementations, TSBs are organized in a variety of ways: a global TSB for all CPUs within the system, a per-processor TSB, or a per-process TSB. All of the aforementioned techniques have various limitations that will be addressed in this paper. In this work, we propose a new framework for TSBs generation and allocation. In the proposed approach, a policy of resizing and dynamically allocating TSBs for the different processes is used. This dynamic policy allows the system to adopt to different workloads while achieving a low TSB context invalidation overhead. In addition, with the ability to assign a separate TSB to each process, thrashing is practically eliminated. Implementation and experimental results of the proposed scheme are reported. Comparisons against existing implementations confirmed the expected performance enhancement.

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Li, Yang, Rami Melhem i Alex K. Jones. "Leveraging Sharing in Second Level Translation-Lookaside Buffers for Chip Multiprocessors". IEEE Computer Architecture Letters 11, nr 2 (lipiec 2012): 49–52. http://dx.doi.org/10.1109/l-ca.2011.35.

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Haigh, Jonathan R., i Lawrence T. Clark. "High performance set associative translation lookaside buffers for low power microprocessors". Integration 41, nr 4 (lipiec 2008): 509–23. http://dx.doi.org/10.1016/j.vlsi.2007.11.003.

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Chang, Xiaotao, Hubertus Franke, Yi Ge, Tao Liu, Kun Wang, Jimi Xenidis, Fei Chen i Yu Zhang. "Improving virtualization in the presence of software managed translation lookaside buffers". ACM SIGARCH Computer Architecture News 41, nr 3 (26.06.2013): 120–29. http://dx.doi.org/10.1145/2508148.2485933.

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Jaleel, A., i B. Jacob. "In-line interrupt handling and lock-up free translation lookaside buffers (TLBs)". IEEE Transactions on Computers 55, nr 5 (maj 2006): 559–74. http://dx.doi.org/10.1109/tc.2006.77.

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Klimiankou, Y. I. "Translation lookaside buffer management". «System analysis and applied information science», nr 4 (30.12.2019): 20–24. http://dx.doi.org/10.21122/2309-4923-2019-4-20-24.

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This paper focuses on the Translation Lookaside Buffer (TLB) management as part of memory management. TLB is an associative cache of the advanced processors, which reduces the overhead of the virtual to physical address translations. We consider challenges related to the design of the TLB management subsystem of the OS kernel on the example of the IA-32 platform and propose a simple model of complete and consistent policy of TLB management. This model can be used as a foundation for memory management subsystems design and verification.

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Teller, P. J. "Translation-lookaside buffer consistency". Computer 23, nr 6 (czerwiec 1990): 26–36. http://dx.doi.org/10.1109/2.55498.

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Tamura, L. R., T. S. Yang, D. E. Wingard, M. A. Horowitz i B. A. Wolley. "A 4-ns BiCMOS translation-lookaside buffer". IEEE Journal of Solid-State Circuits 25, nr 5 (1990): 1093–101. http://dx.doi.org/10.1109/4.62129.

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Lee, Jung-Hoon, Seh-Woong Jeong, Shin-Dug Kim i Charles Weems. "A banked-promotion translation lookaside buffer system". Journal of Systems Architecture 47, nr 14-15 (sierpień 2002): 1065–78. http://dx.doi.org/10.1016/s1383-7621(02)00057-7.

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Black, D. L., R. F. Rashid, D. B. Golub i C. R. Hill. "Translation lookaside buffer consistency: a software approach". ACM SIGARCH Computer Architecture News 17, nr 2 (kwiecień 1989): 113–22. http://dx.doi.org/10.1145/68182.68193.

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Rozprawy doktorskie na temat "Translation Lookaside Buffers"

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Bala, Kavita. "Software management techniques for translation lookaside buffers". Thesis, Massachusetts Institute of Technology, 1995. http://hdl.handle.net/1721.1/36539.

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Chandran, Varadharajan. "Robust Method to Deduce Cache and TLB Characteristics". The Ohio State University, 2011. http://rave.ohiolink.edu/etdc/view?acc_num=osu1308256764.

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Kaeslin, Alain E. "Performance Optimisation of Discrete-Event Simulation Software on Multi-Core Computers". Thesis, KTH, Skolan för datavetenskap och kommunikation (CSC), 2016. http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-191132.

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SIMLOX is a discrete-event simulation software developed by Systecon AB for analysing logistic support solution scenarios. To cope with ever larger problems, SIMLOX's simulation engine was recently enhanced with a parallel execution mechanism in order to take advantage of multi-core processors. However, this extension did not result in the desired reduction in runtime for all simulation scenarios even though the parallelisation strategy applied had promised linear speedup. Therefore, an in-depth analysis of the limiting scalability bottlenecks became necessary and has been carried out in this project. Through the use of a low-overhead profiler and microarchitecture analysis, the root causes were identified: atomic operations causing a high communication overhead, poor locality leading to translation lookaside buffer thrashing, and hot spots that consume significant amounts of CPU time. Subsequently, appropriate optimisations to overcome the limiting factors were implemented: eliminating the expensive operations, more efficient handling of heap memory through the use of a scalable memory allocator, and data structures that make better use of caches. Experimental evaluation using real world test cases demonstrated a speedup of at least 6.75x on an eight-core processor. Most cases even achieve a speedup of more than 7.2x. The various optimisations implemented further helped to lower run times for sequential execution by 1.5x or more. It can be concluded that achieving nearly linear speedup on a multi-core processor is possible in practice for discrete-event simulation.
SIMLOX är en kommersiell mjukvara utvecklad av Systecon AB, vars huvudsakliga funktion är en händelsestyrd simuleringskärna för analys av underhållslösningar för komplexa tekniska system. För hantering av stora problem så används parallellexekvering för simuleringen, vilket i teorin borde ge en nästan linjär skalning med antal trådar. Prestandaförbättringen som observerats i praktiken var dock ytterst begränsad, varför en ordentlig analys av skalbarheten har gjorts i detta projekt. Genom användandet av ett profileringsverktyg med liten overhead och mikroarkitektur-analys, så kunde orsakerna hittas: atomiska operationer som skapar mycket overhead för kommunikation, dålig lokalitet ger fragmentering vid översättning till fysiska adresser och dåligt utnyttjande av TLB-cachen, och vissa flaskhalsar som kräver mycket CPU-kraft. Därefter implementerades och testade optimeringar för att undvika de identifierade problem. Testade lösningar inkluderar eliminering av dyra operationer, ökad effektivitet i minneshantering genom skalbara minneshanteringsalgoritmer och implementation av datastrukturer som ger bättre lokalitet och därmed bättre användande av cache-strukturen. Verifiering på verkliga testfall visade på uppsnabbningar på åtminstone 6.75 gånger på en processor med 8 kärnor. De flesta fall visade på en uppsnabbning med en faktor större än 7.2. Optimeringarna gav även en uppsnabbning med en faktor på åtminstone 1.5 vid sekventiell exekvering i en tråd. Slutsatsen är därmed att det är möjligt att uppnå nästan linjär skalning med antalet kärnor för denna typ av händelsestyrd simulering.

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孫維宗. "Shared translation lookaside buffers on shared-memory multiporcessor systems". Thesis, 1992. http://ndltd.ncl.edu.tw/handle/35206736315855409599.

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Nayak, Ajay Ashok. "Design, Implementation, and Analysis of a TLB-based Covert Channel on GPUs". Thesis, 2021. https://etd.iisc.ac.in/handle/2005/6181.

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GPUs are now commonly available in most modern computing platforms. They are increasingly being adopted in cloud platforms and data centers due to their immense computing capability. In response to this growth in usage, manufacturers are continuously trying to improve GPU hardware by adding new features. However, this increase in usage and the addition of utility-improving features can create new, unexpected attack channels. In this thesis, we show that two such features—unified virtual memory (UVM) and multi-process service (MPS)—primarily introduced to improve the programmability and efficiency of GPU kernels have an unexpected consequence—that of creating a novel covert timing channel via the GPU’s translation lookaside buffer (TLB) hierarchy. To enable this covert channel, we first perform experiments to understand the characteristics of TLBs present on a GPU. The use of UVM allows fine-grained management of translations, and helps us discover several idiosyncrasies of the TLB hierarchy, such as three-levels of TLB, coalesced entries. We use this newly-acquired understanding to demonstrate a novel covert channel via the shared TLB. We then leverage MPS to increase the bandwidth of this channel by 40×. Finally, we demonstrate the channel’s utility by leaking data from a GPU-accelerated database application

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Panwar, Ashish. "Operating System Support for Efficient Virtual Memory". Thesis, 2022. https://etd.iisc.ac.in/handle/2005/5788.

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Computers rely on the virtual memory abstraction to simplify programming, portability, physical memory management and ensure isolation among co-running applications. However, it creates a layer of indirection in the critical path of execution wherein the processor needs to translate an application-generated virtual address into the corresponding physical address before performing the computation. To accelerate the virtual-to-physical address translation, processors cache recently used addresses in Translation Lookaside Buffers (TLBs). Unfortunately, modern data-centric applications executing on large memory servers experience frequent TLB misses. The processor services TLB misses by walking the in-memory page tables that often involves accessing physical memory. Consequently, the processor spends 30-50% of total cycles in servicing TLB misses alone for many big-data applications. Virtualization and non-uniform memory access (NUMA) architectures in multi-socket servers further exacerbate this overhead. Virtualization adds an additional level of address translation while NUMA can increase the latency of accessing page tables residing on a remote socket. The address translation overhead will increase further with deeper page tables and multi-tiered memory systems in newer and upcoming systems. In short, virtual memory is showing its age in the era of data-centric computing. In this thesis, we propose ways to moderate the overhead of virtual-to-physical address translation. The majority of this thesis focuses on huge pages. Processor designers have invested significant hardware in supporting huge pages to reduce the number and cost of TLB misses e.g., x86 architecture supports 2MB and 1GB huge pages. However, we find that operating systems often fail to harness the full potential of huge pages. This thesis highlights the pitfalls associated with the current huge page management strategies and proposes various operating system enhancements to maximize the benefits of huge pages. We also address the effect of non-uniform memory accesses on address translation with NUMA-aware page table management. A key objective of this thesis is to avoid modifying the applications or adding new features to the hardware. Therefore, all the solutions discussed in this thesis apply to current hardware and remain transparent to the applications. All of our contributions are open-sourced.

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Chang, Wei-Keng, i 張維耿. "Low Power Pre-comparison Content Addressable Memory and Translation Lookaside Buffer Design". Thesis, 2005. http://ndltd.ncl.edu.tw/handle/g5h3gt.

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"A Structured Design Methodology for High Performance VLSI Arrays". Doctoral diss., 2012. http://hdl.handle.net/2286/R.I.14726.

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abstract: The geometric growth in the integrated circuit technology due to transistor scaling also with system-on-chip design strategy, the complexity of the integrated circuit has increased manifold. Short time to market with high reliability and performance is one of the most competitive challenges. Both custom and ASIC design methodologies have evolved over the time to cope with this but the high manual labor in custom and statistic design in ASIC are still causes of concern. This work proposes a new circuit design strategy that focuses mostly on arrayed structures like TLB, RF, Cache, IPCAM etc. that reduces the manual effort to a great extent and also makes the design regular, repetitive still achieving high performance. The method proposes making the complete design custom schematic but using the standard cells. This requires adding some custom cells to the already exhaustive library to optimize the design for performance. Once schematic is finalized, the designer places these standard cells in a spreadsheet, placing closely the cells in the critical paths. A Perl script then generates Cadence Encounter compatible placement file. The design is then routed in Encounter. Since designer is the best judge of the circuit architecture, placement by the designer will allow achieve most optimal design. Several designs like IPCAM, issue logic, TLB, RF and Cache designs were carried out and the performance were compared against the fully custom and ASIC flow. The TLB, RF and Cache were the part of the HEMES microprocessor.
Dissertation/Thesis
Ph.D. Electrical Engineering 2012

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Części książek na temat "Translation Lookaside Buffers"

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Agarwal, Manisha, i Manisha Jailia. "Concurrency Control Algorithms for Translation Lookaside Buffer". W Information and Communication Technology for Competitive Strategies, 187–96. Singapore: Springer Singapore, 2018. http://dx.doi.org/10.1007/978-981-13-0586-3_19.

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"Translation Lookaside Buffer (TLB)". W Encyclopedia of Database Systems, 3172. Boston, MA: Springer US, 2009. http://dx.doi.org/10.1007/978-0-387-39940-9_3880.

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Streszczenia konferencji na temat "Translation Lookaside Buffers"

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Chang, Xiaotao, Hubertus Franke, Yi Ge, Tao Liu, Kun Wang, Jimi Xenidis, Fei Chen i Yu Zhang. "Improving virtualization in the presence of software managed translation lookaside buffers". W the 40th Annual International Symposium. New York, New York, USA: ACM Press, 2013. http://dx.doi.org/10.1145/2485922.2485933.

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Clark, Lawrence T., i Vikas Chaudhary. "Fast low power translation lookaside buffers using hierarchical NAND match lines". W 2010 IEEE International Symposium on Circuits and Systems - ISCAS 2010. IEEE, 2010. http://dx.doi.org/10.1109/iscas.2010.5537832.

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Venkatasubramanian, Girish, Renato J. Figueiredo i Ramesh Illikkal. "On the Performance of Tagged Translation Lookaside Buffers: A Simulation-Driven Analysis". W Simulation of Computer and Telecommunication Systems (MASCOTS). IEEE, 2011. http://dx.doi.org/10.1109/mascots.2011.26.

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Antonyuk, Artem V., i Pavel V. Stepanov. "Comparison of the matching circuits for the 65-nm CMOS translation lookaside buffers". W 2018 Moscow Workshop on Electronic and Networking Technologies (MWENT). IEEE, 2018. http://dx.doi.org/10.1109/mwent.2018.8337194.

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Agarwal, Manisha, i Manisha Jailia. "Inconsistency in translation lookaside buffer". W 2016 International Conference on ICT in Business Industry & Government (ICTBIG). IEEE, 2016. http://dx.doi.org/10.1109/ictbig.2016.7892705.

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Clark, Lawrence T., Byungwoo Choi i Michael Wilkerson. "Reducing translation lookaside buffer active power". W the 2003 international symposium. New York, New York, USA: ACM Press, 2003. http://dx.doi.org/10.1145/871506.871512.

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Tamura, L., T. S. Yang, D. Wingard, M. Horowitz i B. Wooley. "A 4 ns BiCMOS translation-lookaside buffer". W 1990 37th IEEE International Conference on Solid-State Circuits. IEEE, 1990. http://dx.doi.org/10.1109/isscc.1990.110132.

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Black, D. L., R. F. Rashid, D. B. Golub i C. R. Hill. "Translation lookaside buffer consistency: a software approach". W the third international conference. New York, New York, USA: ACM Press, 1989. http://dx.doi.org/10.1145/70082.68193.

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Liu, Hao, Quentin L. Meunier i Alain Greiner. "Decoupling Translation Lookaside Buffer Coherence from Cache Coherence". W 2017 IEEE Computer Society Annual Symposium on VLSI (ISVLSI). IEEE, 2017. http://dx.doi.org/10.1109/isvlsi.2017.25.

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Farrens, Matthew, Arvin Park, Rob Fanfelle, Pius Ng i Gary Tyson. "A partitioned translation lookaside buffer approach to reducing address bandwith (abstract)". W the 19th annual international symposium. New York, New York, USA: ACM Press, 1992. http://dx.doi.org/10.1145/139669.140546.

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