Rozprawy doktorskie na temat „Transistor scaling”

La r eduction (\scaling") continue des dimensions des transistors MOS- FET nous a conduits a l' ere de la nano electronique. Le transistor a ef- fet de champ multi-grilles (MultiGate FET, MuGFET) avec l'architecture \nano l canal" est consid er e comme un candidat possible pour le scaling des MOSFET jusqu' a la n de la roadmap. Parall element au scaling des CMOS classiques ou scaling suivant la loi de Moore, de nombreuses propo- sitions de nouveaux dispositifs, exploitant des ph enom enes nanom etriques, ont et e faites. Ainsi, le transistor mono electronique (SET), utilisant le ph enom ene de \blocage de Coulomb", et le transistor a atome unique (SAT), en tant que transistors de dimensions ultimes, sont les premiers disposi- tifs nano electroniques visant de nouvelles applications comme la logique a valeurs multiples ou l'informatique quantique. Bien que le SET a et e ini- tialement propos e comme un substitut au CMOS (\Au-del a du dispositif CMOS"), il est maintenant largement consid er e comme un compl ement a la technologie CMOS permettant de nouveaux circuits fonctionnels. Toutefois, la faible temp erature de fonctionnement et la fabrication incompatible avec le proc ed e CMOS ont et e des contraintes majeures pour l'int egration SET avec la technologie FET industrielle. Cette th ese r epond a ce probl eme en combinant les technologies CMOS de dimensions r eduites, SET et SAT par le biais d'un sch ema d'int egration unique a n de fabriquer des transistors \Trigate" nano l. Dans ce travail, pour la premi ere fois, un SET fonction- nant a temp erature ambiante et fabriqu es a partir de technologies CMOS SOI a l' etat de l'art (incluant high-k/grille m etallique) est d emontr e. Le fonctionnement a temp erature ambiante du SET n ecessite une le (ou canal) de dimensions inf erieures a 5 nm. Ce r esultat est obtenu grce a la r eduction du canal nano l "trigate" a environ 5 nm de largeur. Une etude plus ap- profondie des m ecanismes de transport mis en jeu dans le dispositif est r ealis ee au moyen de mesures cryog eniques de conductance. Des simula- tions NEGF tridimensionnelles sont egalement utilis ees pour optimiser la conception du SET. De plus, la coint egration sur la m^eme puce de MOS- FET FDSOI et SET est r ealis ee. Des circuits hybrides SET-FET fonction- nant a temp erature ambiante et permettant l'ampli cation du courant SET jusque dans la gamme des milliamp eres (appel e \dispositif SETMOS" dans la litt erature) sont d emontr es de m^eme que de la r esistance di erentielle n egative (NDR) et de la logique a valeurs multiples. Parall element, sur la m^eme technologie, un transistor a atome unique fonc- tionnant a temp erature cryog enique est egalement d emontr e. Ceci est obtenu par la r eduction de la longueur de canal MOSFET a environ 10 nm, si bien qu'il ne comporte plus qu'un seul atome de dopant dans le canal (dif- fus ee a partir de la source ou de drain). A basse temp erature, le trans- port d' electrons a travers l' etat d' energie de ce dopant unique est etudi e. Ces dispositifs fonctionnent egalement comme MOSFET a temp erature am- biante. Par cons equent, une nouvelle m ethode d'analyse est d evelopp ee en corr elation avec des caract eristiques a 300K et des mesures cryog eniques pour comprendre l'impact du dopant unique sur les caracteristiques du MOSFET a temp erature ambiante.

The objective of the proposed work is to study the behavior of SiGe HBTs at cryogenic temperatures and its relation to device scaling and optimization. Not only is cryogenic operation of these devices required by space missions, but characterizing their cryogenic behavior also helps to investigate the performance limits of SiGe HBTs and provides essential information for further device scaling. Technology computer aided design (TCAD) and sophisticated on-wafer DC and RF measurements are essential in this research. Drift-diffusion (DD) theory is used to investigate a novel negative differential resistance (NDR) effect and a collector current kink effect in first-generation SiGe HBTs at deep cryogenic temperatures. A theory of positive feedback due to the enhanced heterojunction barrier effect at deep cryogenic temperatures is proposed to explain such effects. Intricate design of the germanium and base doping profiles can greatly suppress both carrier freezeout and the heterojunction barrier effect, leading to a significant improvement in the DC and RF performance for NASA lunar missions. Furthermore, cooling is used as a tuning knob to better understand the performance limits of SiGe HBTs. The consequences of cooling SiGe HBTs are in many ways similar to those of combined vertical and lateral device scaling. A case study of low-temperature DC and RF performance of prototype fourth-generation SiGe HBTs is presented. This study summarizes the performance of all three prototypes of these fourth-generation SiGe HBTs within the temperature range of 4.5 to 300 K. Temperature dependence of a fourth-generation SiGe CML gate delay is also examined, leading to record performance of Si-based IC. This work helps to analyze the key optimization issues associated with device scaling to terahertz speeds at room temperature. As an alternative method, an fT -doubler technique is presented as an attempt to reach half-terahertz speeds. In addition, a roadmap for terahertz device scaling is given, and the potential relevant physics associated with future device scaling are examined. Subsequently, a novel superjunction collector design is proposed for higher breakdown voltages. Hydrodynamic models are used for the TCAD studies that complete this part of the work. Finally, Monte Carlo simulations are explored in the analysis of aggressively-scaled SiGe HBTs.

This thesis investigates the effects of low temperatures on Silicon Germanium (SiGe) Hterojunction Bipolar Transistors (HBT) BiCMOS technology. A comprehensive set of dc measurements were taken on first, second, third and fourth generation IBM SiGe technology over a range of temperatures (room temperature to 43K for first generation, and room temperature to 15K for the rest). This work is unique in the sense that this sort of comprehensive study of dc characteristics on four SiGe HBT technology generations over a wide range of temperatures has never been done before to the best of the authors knowledge.

O objetivo principal deste trabalho é o estudo de transistores UTBOX SOI não auto-alinhados operando como célula de memória de apenas um transistor aproveitando-se do efeito de corpo flutuante (1T-FBRAM single Transistor Floating Body Random Access Memory). A caracterização elétrica dos dispositivos se deu a partir de medidas experimentais estáticas e dinâmicas e ainda, simulações numéricas bidimensionais foram implementadas para confirmar os resultados obtidos. Diferentes métodos de escrita e leitura do dado 1 que também são chamados de métodos de programação do dado 1 são encontrados na literatura, mas com intuito de se melhorar os parâmetros dinâmicos das memórias como o tempo de retenção e a margem de sensibilidade e ainda, permitir um maior escalamento dos dispositivos totalmente depletados, o método de programação utilizado neste trabalho será o BJT (Bipolar Junction Transistor). Uma das maiores preocupações para a aplicação de células 1T-DRAMs nas gerações tecnológicas futuras é o tempo de retenção que diminui juntamente com a redução do comprimento de canal do transistor. Com o intuito de solucionar este problema ou ao menos retardá-lo, é apresentando pela primeira vez um estudo sobre a dependência do tempo de retenção e da margem de sensibilidade em função do comprimento de canal, onde se observou que esses parâmetros dinâmicos podem ser otimizados através da polarização do substrato e mantidos constantes para comprimentos de canal maiores que 50 no caso dos dispositivos não auto-alinhados e 80 nos dispositivos de referência. Entretanto, observou-se também que existe um comprimento de canal mínimo que é dependente do tipo de junção (30 no caso dos dispositivos não auto-alinhados e 50 nos dispositivos de referência) de modo que para comprimentos de canal abaixo desses valores críticos não há mais espaço para otimização dos parâmetros, degradando assim o desempenho da célula de memória. O mecanismo de degradação dos parâmetros dinâmicos de memória foi identificado e atribuído à amplificação da corrente de GIDL (Gate Induced Drain Leakage) pelo transistor bipolar parasitário de base estreita durante a leitura e o tempo de repouso do dado 0. A presença desse efeito foi confirmada através de simulações numéricas bidimensionais dos transistores quando uma alta taxa de geração de portadores surgiu bem próxima das junções de fonte e dreno somente quando o modelo de tunelamento banda-a-banda (bbt.kane) foi considerado. Comparando o comportamento dos dispositivos não auto-alinhados com os dispositivos de referência tanto nos principais parâmetros elétricos (tensão de limiar, inclinação de sublimiar, ganho intrínseco de tensão) como em aplicações de memória (tempo de retenção, margem de sensibilidade, janela de leitura), constatou-se que a estrutura não auto-alinhada apresenta melhor desempenho, uma vez que alcança maior velocidade de chaveamento devido a menor inclinação de sublimiar; menor influência das linhas de campo elétrico nas cargas do canal, menor variação da tensão de limiar, até mesmo com a variação da temperatura. Além disso, constatou-se que os dispositivos não auto-alinhados são mais escaláveis do que os dispositivos de referência, pois são menos susceptíveis à corrente de GIDL, apresentando menor campo elétrico e taxa de geração próximos das junções de fonte e dreno que os dispositivos de referência, alcançando então um tempo de retenção de aproximadamente 6 e margem de sensibilidade de aproximadamente 71 A/m. Segundo as especificações da International Technology Roadmap for Semicondutor de 2011, o valor do tempo de retenção para as memórias DRAM convencionais existentes no mercado de semicondutores é de aproximadamente 64. Com o intuito de aumentar o tempo de retenção das 1T-DRAMs a valores próximos à 64 recomenda-se então o uso da tecnologia não auto-alinhada e também a substituição do silício por materiais com maior banda proibida (band-gap), como exemplo o arseneto de gálio e o silício-carbono, dificultando assim o tunelamento dos elétrons e, consequentemente, diminuindo o GIDL.
The main topic of this work is the study of extensionless UTBOX SOI transistors, also called underlapped devices, applied as a single transistor floating body RAM (1T-FBRAM single transistor floating body access memory). The electrical characterization of the devices was performed through static and dynamic experimental data and two dimensional simulations were implemented to confirm the obtained results. In the literature, different methods to write and read the data 1 can be found but in order to improve the dynamic parameters of the memories, as retention time and sense margin and still allows the scaling of fully depleted devices, the BJT (Bipolar Junction Transistor) method is used in this work. One of the biggest issues to meet the specifications for future generations of 1T-DRAM cells is the retention time that scales together with the channel length. In order to overcome this issue or at least slow it down, in this work, we present for the first time, a study about the retention time and sense margin dependence of the channel length where it was possible to observe that these dynamic parameters can be optimized through the back gate bias and kept constant for channel lengths higher than 50 nm for extensionless devices and 80 nm for standard ones. However, it was also observed that there is a minimal channel length which depends of the source/drain junctions, i.e. 30 nm for extensionless and 50 nm for standard devices in the sense that for shorter channel lengths than these ones, there is no room for optimization degrading the performance of the memory cell. The mechanism behind the dynamic parameters degradation was identified and attributed to the GIDL current amplification by the lateral bipolar transistor with narrow base. Simulations confirmed this effect where higher generation rates near the junctions were presented only when the band-toband- tunneling adjustment was considered (bbt.kane model). Comparing the performance of standard and extensionless devices in both digital and analog electrical parameters and also in memory applications, it was found that extensionless devices present better performance since they reach faster switching which means lower subthreshold slope; less influence of the electrical field in the channel charges; less variation of the threshold voltage even increasing the temperature. Furthermore, it was seen that the gate length can be further scaled using underlap junctions since these devices are less susceptible to the GIDL current, presenting less electric field and generation rate near the source/drain junctions and reach a retention time of around 4 ms and sense margin of 71A/m. According to the International Technology Roadmap for Semiconductor of 2011, the retention time for the existing DRAM is around 64 ms. In order to increase the retention time of the 1T-DRAMs to values close to 64 ms it is recommended the use of extensionless devices and also the substitution of silicon by materials with higher band gap, i.e., gallium arsenide and siliconcarbon, which makes difficult the electron tunneling therefore, decreasing the GIDL.

Thesis (Ph. D.)--Electrical and Computer Engineering, Georgia Institute of Technology, 2004.
Hess, Dennis, Committee Member; Meindl, James, Committee Chair; Allen, Phillip, Committee Member; Cressler, John, Committee Member; Davis, Jeffrey, Committee Member. Vita. Includes bibliographical references (leaves 108-119).

Thesis (Ph. D.)--Electrical and Computer Engineering, Georgia Institute of Technology, 2007.
Philip First, Committee Member ; Ian F. Akyildiz, Committee Member ; Russell Dupuis, Committee Member ; James D. Meindl, Committee Chair ; Willianm R. Callen, Committee Member.

L’escalat dels transistors MOSFET convencionals ha portat a aquests dispositius a la nanoescala per incrementar tant les seves prestacions com el nombre de components per xip. En aquest process d’escalat, els coneguts “Short Channel Effects” representen una forta limitació. La forma més efectiva de suprimir aquests efectes i aixi estendre l’ús del MOSFET convencional, és la reducció del gruix de l’òxid de porta i l’augment de la concentració de dopants al canal. Quan el gruix d’òxid de porta es redueix a unes quantes capes atòmiques, apareix l’efecte túnel mecano-quàntic d’electrons, produint un gran augment en els corrents de fuita, perjudicant la normal operació dels MOSFETs. Això ha fet obligatori l’ús de materials d’alta permitivitat o materials high-κ en els dielèctrics de porta. Tot i les solucions proposades, la reducció de les dimensiones físiques del MOSFET convencional no pot ser mantinguda de forma indefinida i per mantenir la tendència tecnològica s’han suggerit noves estructures com ara MOSFETs multi-porta de cos ultra-prim. En particular, el MOSFET de doble porta és considerat com una estructura multi-porta prometedora per les seves diverses qualitats i avantatges en l’escalat. Aquesta tesi s’enfoca en la modelització de dispositius MOSFET de doble porta i, en particular, en la modelització del corrent túnel de porta que afecta críticamente al consum de potència del transistor. Primerament desenvolupem un model quàntic compacte tant per al potencial electrostàtic com per a la càrrega elèctrica en el transistor de doble-porta simètric amb cos no dopat. Després, aquest model quàntic s’utilitza per proposar un model analític compacte per al corrent túnel directe amb SiO2 com dielèctric de porta, primerament, i després amb una doble capa composta de SiO2 com a capa interfacial i un material “high-κ”. Finalment se desenvolupa un mètode precís per calcular el corrent túnel de porta. El mètode es basa en l’aplicació de condicions de frontera absorbents i, més especificament, en el mètode PML. Aquesta tesi està motivada per les recomanacions fetes pel “International Technology Roadmap of Semiconductors” (ITRS) sobre la necessitat existent de modelatge i simulació d’estructures semiconductores multi-porta.
The scaling of the conventional MOSFETs has led these devices to the nanoscale to increase both the performance and the number of components per chip. In this process, the so-called “Short Channel Effects” have arisen as a limiting factor. To extend the use of the bulk MOSFETs, the most effective ways of suppressing such effects are the reduction of the gate oxide thickness and increasing of the channel doping concentration. When the gate oxide thickness is reduced to a few atomic layers, quantum mechanical tunneling is responsible of a huge increase in the gate leakage current impairing the normal operation of MOSFETs. This has made mandatory the use of high permittivity materials or high-κ as gate dielectrics. Despite the proposed solutions, reduction of the physical dimensions of the conventional MOSFETs cannot be maintained. To keep the technological trend, new MOSFET structures have been suggested such as ultra-thin body Multi-Gate MOSFETs. In particular, the Double-Gate MOSFETs is considered as a promising MG structure for its several qualities and advantages in scaling. This thesis focuses on the modeling of Double-Gate MOSFET and, in particular, on the modeling of the gate leakage current critically affecting the power consumption. First we develop a compact quantum model for both the electrostatic potential and the electric charge in symmetric double-gate MOSFET with undoped thin body. Then, this quantum model is used to propose an analytical compact model for the direct tunnelling current with SiO2 as gate dielectric, firstly, and later assuming a dual layer consisting of a SiO2 interfacial layer and a high-κ material. Finally, an accurate method for the calculation of the gate tunnelling current is developed. It is based on Absorbing Boundary Conditions techniques and, more specifically, on the Perfectly Mached Layer (PML) method. This thesis is motivated by the recommendations given by the “International Technology Roadmap of Semiconductors” (ITRS) about the need for the modeling and simulation of multi-gate semiconductor structures.

Two-dimensional numerical simulation was used to study the scaling properties of SOI p-MOSFETs. Based on the design criteria for the threshold voltage and DIBL, a set of design curves for different designs was developed. Data for subthreshold slope, SCE and threshold voltage sensitivity to silicon film thickness are also given. Results show that short-channel effects can be controlled by increasing the doping level or by thinning the silicon film thickness. The first approach is more effective for p+ gate design with high body doping, while the second approach is much more effective for n+ gate design with low body doping. Then+ gate design is more suited for the design of fully depleted (FD) devices since we need to keep the doping low to minimize the threshold adjustment implant dose and to use thin silicon films to control the SCE. The design of both p-MOSFET and Si 1-xGex p-MOSFET requires the implantation for the threshold voltage adjustment. The p+ gate design is more suited for the partially depleted (PD) or near-fully depleted device design since we need to use high doping for the threshold voltage adjustment and this results in large threshold voltage sensitivity to silicon film thickness for FD devices. The design of Si SOI p-MOSFET is done by properly adjusting the body doping. For the Si1-xGex SOI p-MOSFET large reduction in VTH requires large body doping. This increases the parasitic capacitances and slows down the device.

Mit dem Erreichen der Grenzen der konventionellen MOSFET-Skalierung werden neue Techniken untersucht, um die Leistungsfähigkeit der CMOS-Technologie dem bisherigen Trend folgend weiter zu steigern. Einer dieser Ansätze ist die Verwendung mechanischer Verspannungen im Transistorkanal. Mechanische Verspannungen führen zu Kristalldeformationen und ändern die elektronische Bandstruktur von Silizium, so dass n- und p-MOSFETs mit verspannten Kanälen erhöhte Ladungsträgerbeweglichkeiten und demzufolge eine gesteigerte Leistungsfähigkeit aufweisen. Die vorliegende Arbeit beschäftigt sich mit den Auswirkungen mechanischer Verspannungen auf die elektronischen Eigenschaften planarer Silicon-On-Insulator-MOSFETs für Höchstleistungsanwendungen sowie mit deren Optimierung und technologischen Begrenzungen. Der Effekt der Verspannung auf die Bandstruktur von Silizium und die Ladungsträgerbeweglichkeit wird zunächst systematisch mit Hilfe der empirischen Pseudopotenzialmethode und der Deformationspotenzialtheorie untersucht. Verringerte Streuraten und kleinere effektive Massen als Folge der Aufspaltung der Energiebänder sowie von Bandverformungen sind der Hauptgrund für eine erhöhte Löcher- bzw. Elektronenbeweglichkeit. Die unterschiedlichen Konzepte zur Erzeugung der Verspannung werden kurz rekapituliert. Der Schwerpunkt der Untersuchungen liegt auf den verspannten Deckschichten, den Si1-xGex- bzw. Si1-yCy- Source/Drain-Gebieten, den verspannungsspeichernden Prozessen und den verspannten Substraten. Die starke Abhängigkeit dieser Verspannungstechniken von der Transistorstruktur macht die Nutzung numerischer Simulationen unabdingbar. So werden die Auswirkungen von Variationen der Transistorgeometrie sowie von Prozessparametern im Hinblick auf die Verspannung und die Drainstromänderungen der Transistoren neben den Messungen am gefertigten Transistor auch anhand numerischer Simulationen dargestellt und verglichen. Wesentliche Parameter für eine erhöhte Verspannung werden bestimmt und technologische Herausforderungen bei der Prozessintegration diskutiert. Die durchgeführten Simulationen und das erlangte Verständnis der Wirkungsweise der Verspannungstechniken ermöglichen es, das Potenzial dieser Verspannungstechniken für weitere Leistungssteigerungen in zukünftigen Technologiegenerationen abzuschätzen. Dadurch ist es möglich, die Prozessbedingungen und die Eigenschaften der fertigen Bauelemente im Hinblick auf eine gesteigerte Leistungsfähigkeit hin zu optimieren. Mit der weiteren Verkleinerung der Strukturgrößen der Bauelemente wird der zunehmende Einfluss der parasitären Source/Drain-Widerstände als Begrenzung der Effektivität der Verspannungstechniken identifiziert. Anschließend werden die Wechselwirkungen zwischen den einzelnen Verspannungstechniken hervorgehoben bzw. die gegebenenfalls auftretenden Einschränkungen angesprochen. Abschließend wird das Transportverhalten sowohl im linearen ohmschen Bereich als auch unter dem Einfluss hoher elektrischer Feldstärken analysiert und die deutlichen Unterschiede für die Leistungssteigerungen der verspannten n- und p-MOSFETs begründet
As conventional MOSFET scaling is reaching its limits, several novel techniques are investigated to extend the CMOS roadmap. One of these techniques is the introduction of mechanical strain in the silicon transistor channel. Because strain changes the inter-atomic distances and thus the electronic band structure of silicon, ntype and p-type transistors with strained channels can show enhanced carrier mobility and performance. The purpose of this thesis is to analyze and understand the effects of strain on the electronic properties of planar silicon-on-insulator MOSFETs for high-performance applications as well as the optimization of various stress techniques and their technological limitations. First, the effect of strain on the electronic band structure of silicon and the carrier mobility is studied systematically using the empirical pseudopotential method and the deformation potential theory. Strain-induced energy band splitting and band deformations alter the electron and hole mobility through modulated effective masses and modified scattering rates. The various concepts for strain generation inside the transistor channel are reviewed. The focus of this work is on strained overlayer films, strained Si1-xGex and Si1-yCy in the source/drain regions, stress memorization techniques and strained substrates. It is shown, that strained silicon based improvements are highly sensitive to the device layout and geometry. For that reason, numerical simulations are indispensable to analyze the efficiency of the strain techniques to transfer strain into the channel. In close relation with experimental work the results from detailed simulation studies including parameter variations and material analyses are presented, as well as a thorough investigation of critical parameters to increase the strain in the transistor channel. Thus, the process conditions and the properties of the fabricated devices can be optimized with respect to higher performance. In addition, technological limitations are discussed and the potential of the different strain techniques for further performance enhancements in future technology generations is evaluated. With the continuing reduction in device dimensions the detrimental impact of the parasitic source/drain resistance on device performance is quantified and projected to be the bottleneck for strain-induced performance improvements. Next, the effects from a combination of individual strain techniques are studied and their interactions or possible restrictions are highlighted. Finally, the transport properties in the low-field transport regime as well as under high electrical fields are analyzed and the notable differences between strained n-type and p-type transistors are discussed

Este trabalho propõe uma estratégia para projeto de circuitos VLSI operando em amplo ajuste de tensão e frequência (VFS), desde o regime em Near-threshold, onde uma tensão de VDD caracteriza-se por permitir o funcionamento do circuito com o mínimo dispêndio de energia por operação (MEP), até tensões nominais, dependendo da carga de trabalho exigida pela aplicação. Nesta dissertação é proposto o dimensionamento de transistores para três bibliotecas de células utilizando MOSFETs com tensões de limiar distintas: Regular-VT (RVT), High-VT (HVT) e Low-VT (LVT). Tais bibliotecas possuem cinco células combinacionais: INV, NAND, NOR, OAI21 e AOI22 em múltiplos strengths. A regra para dimensionamento dos transistores das células lógicas foi adaptada de trabalhos relacionados, e fundamenta-se na equalização dos tempos de subida e descida na saída de cada célula, objetivando à redução dos efeitos de variabilidade em baixas tensões de operação. Dois registradores também foram incluídos na biblioteca RVT e sua caracterização foi realizada considerando os parâmetros de processo CMOS 65 nm typical, fast e slow; nas temperaturas de operação de -40°C, 25°C e 125°C, e para tensões variando de 200 mV até 1,2V, para incluir a região de interesse, próxima ao MEP. Os experimentos foram realizados utilizando dez circuitos VLSI de teste: filtro digital notch, um núcleo compatível com o micro-controlador 8051, quatro circuitos combinacionais e quatro sequenciais do benchmark ISCAS. Em termos de economia de energia, operar no MEP resulta em uma redução média de 54,46% em relação ao regime de sub-limiar e até 99,01% quando comparado com a tensão nominal, para a temperatura de 25°C e processo típico. Em relação ao desempenho, operar em regime de VFS muito amplo propicia frequências máximas que variam de centenas de kHz até a faixa de centenas de MHz a GHz, para as temperaturas de -40°C e 25°C, e de MHz até GHz em 125°C. Os resultados desta dissertação, quando comparados a trabalhos relacionados, demonstraram, em média, redução de energia e ganho de desempenho de 24,1% e 152,68%, respectivamente, considerando os mesmos circuitos de teste, operando no ponto de mínima energia (MEP).
This work proposes a strategy for designing VLSI circuits to operate in a very-wide Voltage-Frequency Scaling (VFS) range , from the supply voltage at which the minimum energy per operation (MEP) is achieved, at the Near-Threshold regime, up to the nominal supply voltage for the processes, if so demanded by applications workload. This master thesis proposes the sizing of transistors for three library cells using MOSFETs with different threshold voltages: Regular-VT (RVT), High-VT (HVT), and Low-VT (LVT). These libraries have five combinational cells: INV, NAND, NOR, OAI21, and AOI22 with multiple strengths. The sizing rule for the transistors of the digital cells was an adapted version from related works and it is directly driven by requiring equal rise and fall times at the output for each cell in order to attenuate variability effects in the low supply voltage regime. Two registers were also included in the RVT library cell. This library cell was characterized for typical, fast, and slow processes conditions of a CMOS 65nm technology; for operation at -40ºC, 25ºC, and 125ºC temperatures, and for supply voltages varying from 200 mV up to 1.2V, to include the region of interest, for VDD near the MEP. Experiments were performed with ten VLSI circuit benchmarks: notch filter, 8051 compatible core, four combinational and four sequential ISCAS benchmark circuits. From the energy savings point of view, to operate in MEP results on average reduction of 54.46% and 99.01% when compared with the sub-threshold and nominal supply voltages, respectively. This analysis was performed for 25⁰C and typical process. When considered the performance, the very-wide VFS regime enables maximum operating frequencies varying from hundreds of kHz up to MHz/GHz at -40ºC and 25ºC, and from MHz up to GHz at 125ºC. This master thesis results, when compared with related works, showed on average an energy reduction and performance gain of 24.1% and 152.68%, respectively, for the same circuit benchmarks operating with VDD at the minimum energy point (MEP).

La sensibilité accrue aux variations des procedés de fabrication, de tension, de température et de vieillissement (PVTA) dans les nœuds technologiques avancés d'integration est responsable d'une dégradation significative des spécifications des circuits integrés lors de la fabrication à grand volume. Celle-ci est devenue une préoccupation croissante dans la conception de circuits numériques, qui doit faire face aux exigences de plus en plus strictes des applications modernes en termes d'efficacité énergétique, de fiabilité et de sécurité. Dans ce travail de thèse, les techniques de surveillance de timing intégrée et de compensation sont explorées pour répondre efficacement à ces exigences contradictoires. Dans ce travail de thèse, les techniques proposées ont été étudiés séparément puis combinées dans 3 démonstrateurs SoC numériques fabriqués en technologie 28nm FD-SOI CMOS, dont l'un a été mesuré au moment de la rédaction de ce manuscrit.La surveillance de timing intégrée est proposée comme solution de conception pour permettre la compensation des variations PVTA, la surveillance de la sécurité en operation et la protection contre les attaques hardware en timing. Les moniteurs de timing de l'état de l'art ont été évalués dans la perspective d'une intégration dans des produits industriels, ce qui privilégie des caractéristiques telles que la reusabilité et les faibles coûts d'intégration. Les avantages identifiés de la surveillance de timing de registre à registre ont conduit à la mise en œuvre d'un circuit témoin reconfigurable (Tunable Replica Circuit en langue anglaise) avec une sensibilité de 3 mV/bit en 28nm FD-SOI CMOS, qui démontre un suivi rapide et précis des variations PVTA d'un SoC basé sur un ARM Cortex-R4F à travers des corners lent / typique / rapide, une plage de tension 0.5/1.2 V, une gamme de temperature -40/150°C, et de vieillissement jusqu'a fin de vie. Enfin, ce travail propose un nouveau moniteur de timing qui permet de surmonter les faiblesses des solutions existantes, en obtenant simultanément la reutilisabilité élevée et la large plage de surveillance des oscillateurs en anneau et l'acquisition rapide et précise des circuits témoins reconfigurables.L'exploration des techniques d'adaptation et de compensation commence par la détermination de leur champ d'application dans les produits industriels: l'amélioration des pires cas qui définissent les limites de spécifications du produit lors de la fabrication à grand volume. Dans cette perspective, la région d'application optimale des techniques de voltage scaling et de body biasing a été déterminée et leur impact sur les pires cas des SoC numériques a été évalué. Enfin, ces travaux montrent comment la surconsommation induite par l'application séparée de voltage scaling ou body biasing peut être atténuée par la combinaison des deux, en particulier dans les circuits avec une variété de points de performance opérationnelle (OPPs).Les avantages des techniques proposées ont été démontrés dans un SoC numérique qui optimise son énergie à travers d'une largeur de fréquence de 11X en combinant le voltage scaling adaptatif, body biasing adaptatif et le bias-in-memory-array avec un tunable replica circuit pour la sécurité, la régulation de puissance intégrée et la compensation. Grâce à l'application de ces techniques, le circuit proposé permet de surmonter les limites précédemment signalées et démontre une amélioration des performances de 21X, une Vmin inférieure de 120 mV et une durée de vie de 8X, pour les OPP de faible puissance, de moyenne et de haute performance respectivement.Les études présentées ici ont été incluses dans plusieurs chapitres d'un livre scientifique qui sera publié cette année. En outre, elles ont contribué à une nouvelle plateforme de technologie et de conception. Enfin, 3 publications dans des conférences de l'IEEE et 3 demandes de brevet ont résulté de ce travail de thèse
The increased sensitivity to Process, Voltage, Temperature, and Aging (PVTA) variations in scaled integrated circuits' technology nodes is responsible for a significant degradation in the products' specifications during high volume manufacturing. This has become a growing concern in digital circuit design, which has to cope with the increasingly stringent requirements of modern applications in terms of energy efficiency, reliability, and safety. In this thesis work, embedded timing monitoring and compensation techniques are explored to efficiently address these conflicting requirements. The proposed techniques are studied separately and then combined in 3 digital SoC demonstrators manufactured in 28nm FD-SOI CMOS technology, one of which has been measured at the time of this manuscript's writing.Embedded timing monitoring is proposed as a design solution to enable PVTA compensation, in-field safety monitoring and security protection against hardware timing attacks. The state-of-the-art timing monitors are evaluated from the perspective of an integration into industrial products, emphasizing features such as high reusability and low integration costs. The identified advantages of register-to-register timing monitoring have led to the implementation of a 3mV/bit tunable replica circuit in 28nm FD-SOI CMOS, which demonstrates a fast and accurate PVTA tracking of an ARM Cortex-R4F based SoC across slow/typical/fast process, 0.5/1.2V, -40/150ºC, and End Of Life (EOL) aging. Finally, this work proposes a novel timing monitor that overcomes the weaknesses of existing solutions, simultaneously achieving the high reusability and wide monitoring range of ring oscillators and the fast and accurate timing acquisition of tunable replica circuits.The exploration of adaptive and compensation techniques begins with the determination of their application scope in industrial designs: the improvement of the worst-case limiting corners that set the product's specifications during high volume manufacturing. Following this perspective, the optimal region of application of voltage scaling and body biasing techniques has been determined and their impact on the worst-case specifications of digital SoCs has been assessed. Finally, this work demonstrates how the power overhead induced by the separate application of voltage scaling or body biasing can be mitigated through the combination of both, specially in circuits with a variety of Operational Performance Points (OPPs).The benefits of the proposed techniques have been demonstrated in a digital SoC that optimizes its energy across 11X frequency-wide OPPs by combining adaptive voltage scaling, adaptive body biasing, and bias-in-memory-array with a tunable replica circuit for safety, embedded power regulation and compensation. Through the application of these techniques the proposed design overcomes previously reported limitations and demonstrates an improvement by 21X performance, 120mV lower Vmin, and 8X lifetime, the low-power, mid-, and high-performance OPPs respectively.The studies reported here have been included in several chapters of a scientific book to be published this year. Furthermore, they have contributed to a new technology and design platform. Finally, 3 IEEE conference publications and 3 patent applications have resulted from this thesis' work

Au-delà du nœud technologique CMOS BULK 28nm, certaines limites ont été atteintes dans l'amélioration des performances en raison notamment d'une consommation énergétique devenant trop importante. C'est une des raisons pour lesquelles de nouvelles technologies ont été développées, notamment celles basées sur Silicium sur Isolant (SOI). Par ailleurs, la généralisation des architectures complexes de type multi-cœurs, accentue le problème de gestion de la consommation à grain-fin. Les technologies CMOS FD-SOI offrent de nouvelles opportunités pour la gestion de la consommation en permettant d'ajuster, outre les paramètres usuels que sont la tension d'alimentation et la fréquence d'horloge, la tension de body bias. C'est dans ce contexte que ce travail étudie les nouvelles possibilités offertes et explore des solutions innovantes de gestion dynamique de la tension d'alimentation, fréquence d'horloge et tension de body bias afin d'optimiser la consommation énergétique des systèmes sur puce. L'ensemble des paramètres tensions/fréquence permettent une multitude de points de fonctionnement, qui doivent satisfaire des contraintes de fonctionnalité et de performance. Ce travail s'intéresse donc dans un premier temps à une problématique de conception, en proposant une méthode d'optimisation du placement de ces points de fonctionnement. Une solution analytique permettant de maximiser le gain en consommation apporté par l'utilisation de plusieurs points de fonctionnement est proposée. La deuxième contribution importante de cette thèse concerne la gestion dynamique de la tension d'alimentation, de la fréquence et de la tension de body bias, permettant d'optimiser l'efficacité énergétique en se basant sur le concept de convexité. La validation expérimentale des méthodes proposées s'appuie sur des échantillons de circuits réels, et montre des gains en consommation moyens allant jusqu'à 35%
Beyond 28nm CMOS BULK technology node, some limits have been reached in terms of performance improvements. This is mainly due to the increasing power consumption. This is one of the reasons why new technologies have been developed, including those based on Silicon-On-Insulator (SOI). Moreover, the standardization of complex architectures such as multi-core architectures emphasizes the problem of power management at fine-grain. FD-SOI technologies offer new power management opportunities by adjusting, in addition to the usual parameters such as supply voltage and clock frequency, the body bias voltage. In this context, this work explores new opportunities and searches novel solutions for dynamically manage supply voltage, clock frequency and body bias voltage in order to optimize the power consumption of System on Chip.Adjusting supply voltage, frequency and body bias parameters allows multiple operating points, which must satisfy the constraints of functionality and performance. This work focuses initially at design time, proposing a method to optimize the placement of these operating points. An analytical solution to maximize power savings achieved through the use of several operating points is provided. The second important contribution of this work is a method based on convexity concept to dynamically manage the supply voltage, the frequency and the body bias voltage so as to optimize the energy efficiency. The experimental results based on real circuits show average power savings reaching 35%

The prospect of producing nanometer channel-length thin film transistors (TFTs) for active matrix addressed pixelated arrays opens up new high-performance applications in which the most amenable device topology is the vertical thin film transistor (VTFT) in view of its small area. The previous attempts at fabricating VTFTs have yielded devices with a high drain leakage current, a low ON/OFF current ratio, and no saturation behaviour in the output current at high drain voltages, all induced by short channel effects. To overcome these adversities, particularly dominant as the channel length approaches the nano-scale regime, the reduction of the gate dielectric thickness is essential. However, the problems with scaling the gate dielectric thickness are the high gate leakage current and early dielectric breakdown of the insulator, deteriorating the device performance and reliability. A novel ultra-thin SiNx film suitable for the application as the gate dielectric of short channel TFTs and VTFTs is developed. The deposition is performed in a standard 13.56MHz PECVD system with silane and ammonia precursor gasses diluted in nitrogen. The deposited 50nm SiNx films demonstrate excellent electrical characteristics in terms of a leakage current of 0.1 nA/cm?? and a breakdown electric field of 5.6MV/cm. Subsequently, the state of the art performances of 0.5??m channel length VTFTs with 50 and 30nm thick SiNx gate dielectrics are presented in this thesis. The transistors exhibit ON/OFF current ratios over 10^9, the subthreshold slopes as sharp as 0.23 V/dec, and leakage currents in the fA range. More significantly, a high associated yield is obtained for the fabrication of these devices on 3-inch rigid substrates. Finally, to illustrate the tremendous potential of the VTFT for the large area electronics, a 2.2-inch QVGA AMOLD display with in-pixel VTFT-based driver circuits is designed and fabricated. An outstanding value of 56% compared to the 30% produced by conventional technology is achieved as the aperture ratio of the display. Moreover, the initial measurement results reveal an excellent uniformity of the circuit elements.

The scaling down of Complementary Metal Oxide Semiconductor (CMOS) transistors requires replacement of conventional silicon dioxide layer with higher dielectric constant (K) material for gate dielectric. In order to reduce the gate leakage current, and also to maximize gate capacitance, ‘high K’ gate oxide materials such as Al2O3, ZrO2, HfO2, Ta2O5, TiO2, Er2O3, La2O3, Pr2O3, Gd2O3, Y2O3, CeO2 etc. and some of their silicates such as ZrxSi1–xOy, HfxSi1–xOy, AlxZr1–xO2 etc. are under investigation. A systematic consideration of the required properties of gate dielectrics indicates that the key guidelines for selecting an alternate gate dielectric are (a) permittivity, band gap and band alignment to silicon, (b) thermodynamic stability, (c) film morphology, (d) interface quality, (e) compatibility with the materials/process used in CMOS devices and (f) reliability. In this study titanium dioxide (TiO2) is chosen as an alternate to silicon dioxide (SiO2). This thesis work is aimed at the study of the influence of process parameters like deposition rate, substrate temperature and annealing temperature on the electrical properties like maximum capacitance, dielectric constant, fixed charge, interface trapped charge and leakage current. For making this analysis we have used p–type single crystal silicon (<100>) as substrates and employed direct current (DC) reactive magnetron sputtering method with Titanium metal as target and Oxygen as reactive gas. TiO2 thin films have been deposited with an expected thickness of 50 nm with different deposition rates starting from 0.8 nm/minute to 2 nm/minute with different substrate temperatures (ambient temperature to 500ºC). Some of the samples are annealed at 750ºC in oxygen atmosphere for 30 minutes. SENTECH make Spectroscopic Ellipsometer is used for analyzing the optical properties such as thickness, refractive index etc. The thicknesses of all the samples that are extracted from the Ellipsometry are varying from 35 ± 2 nm to 50 ± 5 nm. Agilent make 4284A model L−C−R meter along with KarlSUSS wafer probe station is used for the C − V measurements and Keithley make 6487 model Pico ammeter/Voltage source is used for the I−V measurements. MOS capacitors have been fabricated with Aluminium as top electrode to perform the bi directional Capacitance−Voltage and also Current−Voltage analysis. The X–ray diffraction studies on the samples deposited at 500ºC showed that the films are amorphous. Dielectric constant (K) and effective substrate doping concentration (Na), flat band voltage (VFB), hysteresis, magnitude of fixed charges (Qf) as well as interface states density (Dit') and Equivalent Oxide Thickness (EOT) are obtained from the bi directional C−V analysis. A maximum dielectric constant of 18 is achieved with annealed samples. The best value of fixed charge density we have achieved is 1.2 x1011 per cm2 corresponding to the deposition rate of 2.0 nm/minute and with 500ºC substrate temperature. The ranges of Qf values that we have obtained are varying from 1.2x 1011 − 1.0 x1012 per cm2. It was also found that, the samples deposited at higher substrate temperatures show lower Qf values than the samples deposited at lower temperatures. The same trend is observed in case of interface states density also. The range of Dit' values we have obtained are in the range of 1.0 x 1012 cm–2eV–1 to 9x1012 cm–2eV–1. The best value of Dit' we have obtained is 1.0x1012 cm–2 eV–1 for the sample deposited at 0.8 nm/minute deposition rate and with substrate temperature of 400ºC. From the flat band voltage values of different set of samples, it was found that the flat band voltage is decreasing and in turn trying to approach the analytical value for the films deposited at higher deposition rates. The minimum EOT that we have achieved is 11 nm that corresponds to the film, which is annealed at 750ºC in oxygen atmosphere. From the I−V analysis it was found that the leakage current density is increasing with increase in substrate temperature and the same trend is observed with annealed films also. The minimum leakage current density achieved is 1.72x10–6 A/cm2 at a gate bias of 1V (corresponding field of 0.3 MV/cm). From the time dependent dielectric breakdown analysis it was found that the leakage current is exhibiting a constant value during the entire voltage stress time of 23 minutes. From the I–V characteristics it was found that the leakage current is following the Schottky emission characteristics at lower electric fields (< 1MV/cm) and is following the Fowler–Nordheim tunneling mechanism at higher electric fields. Since our aim is to study the electrical properties of titanium dioxide thin films for the application as high K gate dielectric in microelectronic applications more emphasis is given on the electrical properties. The maximum dielectric constant we have achieved is in the comparable range of the values for this parameter. The leakage current density values obtained are higher than the required for the microelectronic devices, where as the interface state density values and fixed charge density values are in the same range of values that are reported with this particular oxide and more care has to be taken to minimize these parameters. The EOT values we have achieved are also falling into the range of values that it actually takes as it was reported in the literature.

碩士
國立宜蘭大學
電子工程學系碩士班
97
The thesis mainly focuses on the scaling capability of the nanowire transistors, and the impact of quantum effect is investigated via physical 3D numerical simulation. We analyze the channel scalability and discuss how to control the short channel effects of nanowire, FinFET and Tri-Gate transistors characteristics. Several emerging patterning processes have been proposed in recent years. Due to device size scaling, quantum mechanical effects become significant. The physical quantum mechanical model is one of key figures for 3D numerical device simulation. The quantum mechanical model is analytically studied and compared with classical model. The characteristics of electron distributions on different surface orientations subject to film thickness and manufacturability of the nanowire device are investigated via 3D numerical simulation. We comprehensively examine the three types of multiple-gate structures including nanowire, FinFET and Tri-Gate devices. In order to evaluate the device performance when considering speed for logic application, the thesis also focuses on CV/Ion for CMOS inverter with advanced multiple-gate devices.

碩士
國立臺灣大學
光電工程學研究所
100
This thesis analyzes the scalability of nitride-based nanowire high electron mobility transistors (HEMTs). The positive polarization charge between the AlGaN and GaN interface induces high density of electron which also known as the two dimensional electron gate (2DEG). With the 2DEG, the device does not need high n-type doping to increase the electron density in the channel. Therefore, the mobility can reach a high value due to less impurity scattering in the device. We use a fully three dimensional(3D) self-consistent nite element model to solves drift-di usion and Poisson equations and obtains the electrical properties in the device with 3D structure. In the scaling issue of Si-based transistors, the structure of silicon on insulator(SOI) and the FINFET are two common ways to suppress the short channel e ect (SCE). In the GaN-based transistor, AlGaN and AlInN back barrier, similar to the structure of SOI, can suppress the SCE. How- ever, the negative polarization charge at the interface of the GaN channel and the back barrier reduces the saturation current. In this thesis, we discuss the GaN-HEMT in a 3D tri-gate struc- ture, which is similar to the structure of FINFET. The I-V curve, vtransconductance (gm), sub-threshold swing, and drain induce barrier lowering, fT are discussed. The tri-gate structure can well suppress the SCE when the wire width is reduced. However, the fT decreases at the same time due to the e ect of the lateral gate. To optimize this tri-gate structure, we replace the AlGaN top insulator with AlInN to increase the 2DEG in the channel. Furthermore, we reduce the distance between drain and source to reduce the channel resistance. With a smaller channel resistance in the channel, a higher fT can be obtained. In sum, the optimize structure can suppress the SCE without sacri cing the fT .

碩士
國立交通大學
電子物理系所
106
For the demands and developments of semiconductor industry, the device dimension is scaled down continuously. In this dissertation, we investigate the pros and cons of the multi-gate poly-Si junctionless transistors in the various scaling routes. The routes are conventionally physical scaling, novel electrical scaling, and ultimate scaling, respectively. In the conventional physical scaling route, thinning down the channel of junctionless transistor is able to enhance the switching ability, but its series resistance arise to cause the current declines as the channel dimension scaling down. In the electrical scaling route, the inverse doped poly-Si body is inserted under the channel. The P/N junction supports the volume depletion to scale the channel down, but there is dopant diffusion after the subsequent thermal process. Therefore, we also investigate the impacts of the insertion of a nano-scale dielectric for suppressing diffusion. Consequently, the switching characteristic and current level actually are improved by electrical scaling, but the channel and body concentration is a critical factor to the electrical characteristic. However, too heavy doping concentration leading serious leakage and VT roll-off as channel length increases are still unsolved issues, which make the devices hard to apply on the real circuits. Body bias can adjust the electrical characteristic efficiently (ϒ=0.306) and extend the device application. In the ultimate scaling route, the device combined with the GAA architecture and nano-scale channels shows the superior S.S (≈66mV/dec). and current level (ION ≈79 µA/µm). As a result, the GAA architecture is still the best choice in the various scaling routes.

碩士
國立交通大學
光電系統研究所
108
In recent years, with the flourish of smart phones, Internet of Things (IoT) and other related applications, low-power consumption electronic devices are in urgent need. Tunneling FETs (TFETs) and Negative Capacitances (NCFETs) are been investigated to be different from traditional Si-based FETs to break through the thermophysical limitation of less than 60mV/decade subthershold (SS), allowing the transistors to turn on the devices with less biasing. Since the TFET has a shortage that Ion is hard to improve and a tradeoff effect with Ioff, the NC-FETs with negative capacitance effect have the potential to develop a low-power consumption transistor device. The new ferroelectric materials retain the advantages, strong polarization performances, of traditional ferroelectric materials (SBT, PZT...) and overcome the problems that traditional ferroelectric materials cannot be shrunk. However, new challenges have been emerged due to the influence of miniaturization. The thinner the overall buffer is, the thinner the buffer layer and the ferroelectric layer are, resulting in a stronger ferroelectric material polarization, and a leakage current is increased at the interface. In this master thesis, we investigate ferroelectric HfZrO material which is the most mature HfO2-based ferroelectric application so far. First, we investigate the influences on ferroelectricity of different Zr dopant content. The high dopant content induces stronger ferroelectricity. However, when Zr dopant content too high, it will result in zirconium diffusion and further induce high leakage current. Therefore, the appropriate Zr dopant content not only can keep the strong ferroelectricity but also avoid high leakage current issue. Next, we try to scale the HfZrO thin films, finding that the thickness at 7nm can remain ferroelectricity due to the grain size effect. Last, in order to study relationship with the Zr diffusion and the interfacial layer, we fabricate different thickness of interlayer. Although thin interlayer is prone to Zr diffusion and lead higher leakage current, it exhibits good performance on gate controllability. When thicken the interlayer, the obvious depolarization will degrade the gate controllability on ferroelectric gate-stack and further induce increasing Ioff in MOSFET apparently. As a result, the investigation on Zr dopant content in HfZrO NC-FET, ferroelectric gate-stack scaling and the thickness of interlayer effect, we can sum up the optimization of HfZrO NC-FET. With the success of bipolar N-type and P-type NC-FET, the investigation will help the future integration of low-power CMOS circuit technology.