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Artykuły w czasopismach na temat „TIQ COMPARATOR”

Autor: Grafiati
Data publikacji: 11 września 2023

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1

Palsodkar, Prachi, Pravin Dakhole i Prasanna Palsodkar. "Reduced Complexity Linearity Improved Threshold Quantized Comparator Based Flash ADC". Journal of Circuits, Systems and Computers 26, nr 03 (21.11.2016): 1750046. http://dx.doi.org/10.1142/s0218126617500463.

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This paper describes a standard cell-based new approach of comparator design for flash ADC. Conventional flash ADC comparator consumes up to 60% of the power due to resistive ladder network and analog comparators. Threshold inverter quantized (TIQ) comparators reported earlier have improved speed and provide low-power, low-voltage operation. But they need feature size variation and have non-linearity issues. Here, a new standard cell comparator is proposed which retains all advantages of TIQ comparator and provides improved linearity with reduced hardware complexity. A 4-bit ADC designed using the proposed comparator requires 206 minimum-sized transistors and provides large area saving compared to previously proposed designs. Thermometer code is partitioned using algebraic division theorem. This conversion is used for mathematical modeling and complexity reduction of decoder circuit using semi-parallel organization of comparators. Circuit is designed using 90 nm technology which exhibits satisfactory performance even in process variation.
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2

Thai, Hong-Hai, Cong-Kha Pham i Duc-Hung Le. "Design of a Low-Power and Low-Area 8-Bit Flash ADC Using a Double-Tail Comparator on 180 nm CMOS Process". Sensors 23, nr 1 (21.12.2022): 76. http://dx.doi.org/10.3390/s23010076.

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This paper presents a low-area 8-bit flash ADC that consumes low power. The flash ADC includes four main blocks—an analog multiplexer (MUX), a comparator, an encoder, and an SPI (Serial Peripheral Interface) block. The MUX allows the selection between eight analog inputs. The comparator block contains a TIQ (Threshold Inverter Quantization) comparator, a control circuit, and a proposed architecture of a Double-Tail (DT) comparator. The advantage of using the DT comparator is to reduce the number of comparators by half, which helps reduce the design area. The SPI block can provide a simple way for the ADC to interface with microcontrollers. This mixed-signal circuitry is designed and simulated using 180 nm CMOS technology. The 8-bit flash ADC only employs 128 comparators. The applied input clock is 80 MHz, with the input voltage ranging from 0.6 V to 1.8 V. The comparator block outputs 127 bits of thermometer code and sends them to the encoder, which exports the seven least significant bits (LSB) of the binary code. The most significant bit (MSB) is decided by only one DT comparator. The design consumes 2.81 mW of power on average. The total area of the layout is 0.088 mm2. The figure of merit (FOM) is about 877 fJ/step. The research ends up with a fabricated chip with the design inserted into it.
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3

KIM, I., J. YOO, J. KIM i K. CHOI. "Highly Efficient Comparator Design Automation for TIQ Flash A/D Converter". IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences E91-A, nr 12 (1.12.2008): 3415–22. http://dx.doi.org/10.1093/ietfec/e91-a.12.3415.

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Sankar, P. A. Gowri, i G. Sathiyabama. "A Novel CNFET Technology Based 3 Bit Flash ADC for Low-Voltage High Speed SoC Application". International Journal of Engineering Research in Africa 19 (październik 2015): 19–36. http://dx.doi.org/10.4028/www.scientific.net/jera.19.19.

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The continuous scaling down of metal-oxide-semiconductor field effect transistors (MOSFETs) led to the considerable impact in the analog-digital mixed signal integrated circuit design for system-on-chips (SoCs) application. SoCs trends force ADCs to be integrated on the chip with other digital circuits. These trends present new challenges in ADC circuit design based on existing CMOS technology. In this paper, we have designed and analyzed a 3-bit high speed, low-voltage and low-power flash ADC at 32nm CNFET technology for SoC applications. The proposed ADC utilizes the Threshold Inverter Quantization (TIQ) technique that uses two cascaded carbon nanotube field effect transistor (CNFET) inverters as a comparator. The TIQ technique proposed has been developed for better implementation in SoC applications. The performance of the proposed ADC is studied using two different types of encoders such as ROM and Fat tree encoders. The proposed ADCs circuits are simulated using Synopsys HSPICE with standard 32nm CNFET model at 0.9 input supply voltage. The simulation results show that the proposed 3 bit TIQ technique based flash ADC with fat tree encoder operates up to 8 giga samples per second (GSPS) with 35.88µW power consumption. From the simulation results, we observed that the proposed TIQ flash ADC achieves high speed, small size, low power consumption, and low voltage operation compared to other low power CMOS technology based flash ADCs. The proposed method is sensitive to process, temperature and power supply voltage variations and their impact on the ADC performance is also investigated.
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5

Kumar Nagar, Rajesh, i UBS Chandrawat. "Design of a 3.0 MSPS, 2.5V, 0.25 µm, 4-Bit Flash ADC Based on TIQ Comparator". International Journal of Engineering Trends and Technology 12, nr 3 (25.06.2014): 123–26. http://dx.doi.org/10.14445/22315381/ijett-v12p222.

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6

Senthil Sivakumar, M., i S. P. Joy Vasantha Rani. "Efficient Design of ADC BIST with an Analog Ramp Signal Generation and Digital Error Estimation". Journal of Circuits, Systems and Computers 28, nr 03 (24.02.2019): 1950042. http://dx.doi.org/10.1142/s0218126619500427.

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This paper presents the design of linear ramp generator and digital BIST for an on-chip ADC testing. It replaces the costly and time-consuming traditional mixed signal test methods like DSP-based testing, ATE, etc. The proposed on-chip analog ramp generator uses only a few transistors to generate linear ramp signal. A TIQ comparator based 8-bit flash ADC is taken under test. The output response of the ADC is analyzed in the digital BIST to measure the primary nonidealities affecting the linearity and accuracy of the data conversion. In testing, ADC generates the digital data sequence as a test pattern in response to the ramp input while digital BIST estimates the conversion error. This method does not require DAC and any additional components which increase the area overhead of ADC test. The complete design of ramp generator is integrated with TIQ flash ADC and verified in 0.18[Formula: see text][Formula: see text]m CMOS technology with 1.8[Formula: see text]V of the power supply and 100[Formula: see text]kHz of the input frequency. Measurement of nonidealities shows that the design of an 8-bit flash ADC has good accuracy in data conversion with the differential nonlinearity of [Formula: see text]0.24/[Formula: see text]0.17[Formula: see text]LSB and integral nonlinearity of [Formula: see text]0.44/[Formula: see text]0.04[Formula: see text]LSB.
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7

Saman, B., R. H. Gudlavalleti, R. Mays, J. Chandy, Evan Heller i F. Jain. "3-Bit Analog-to-Digital Converter Using Multi-State Spatial Wave-Function Switched FETs". International Journal of High Speed Electronics and Systems 29, nr 01n04 (marzec 2020): 2040014. http://dx.doi.org/10.1142/s0129156420400145.

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Multi-valued logic using multi-state spatial wavefunction switched (SWS)-FETs offers overall reduction in size and power as compared to conventional FET based circuits. This paper presents the design of compact 3-bit Analog-to-Digital Converters (ADC) implemented with SWS-FETs. A novel multi-valued Threshold Inverter Quantization (TIQ) based voltage comparator using SWS FET transistors has been proposed. Unlike conventional FETs, SWS-FETs are comprised of two or more vertically stacked coupled quantum well or quantum dot channels, and the spatial location of carriers within these channels is used to encode the logic states (00), (01), (10) and (11). The SWS-FET logic and circuit models for complementary (n- and p-channel) using 20 nm technology are presented. The digital logic circuit in the ADC is developed using SWS-FET based quaternary logic circuits. The accuracy of the SWS-FET circuits is verified by SWS-FET models in Cadence. The simulations for the SWS FET are based on integration of the Berkeley Short-channel IGFET Model (BSIM4.6) and the Analog Behavioral Model (ABM). The ADC circuit design using SWS-FETs reduce the number of transistors by 55% compared with CMOS counterpart.
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8

Tangel, Ali, i Oktay Aytar. "MOS mismatch effects on TIQ comparators". International Journal of Electronics 96, nr 6 (czerwiec 2009): 561–70. http://dx.doi.org/10.1080/00207210902792783.

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9

Shao, Haiming, Kaifeng Qu, Feipeng Lin, Bo Liang, Kai Jia, Qiang Ren, Yanqiang Li i Wenfeng Li. "Magnetic Shielding Effectiveness of Current Comparator". IEEE Transactions on Instrumentation and Measurement 62, nr 6 (czerwiec 2013): 1486–90. http://dx.doi.org/10.1109/tim.2012.2228751.

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10

Coffield, Frederick E. "A high-performance digital phase comparator". IEEE Transactions on Instrumentation and Measurement IM-36, nr 3 (wrzesień 1987): 717–20. http://dx.doi.org/10.1109/tim.1987.6312777.

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11

So, E., i B. Djokic. "A Hybrid Electronically Coupled Current Comparator". IEEE Transactions on Instrumentation and Measurement 54, nr 2 (kwiecień 2005): 580–83. http://dx.doi.org/10.1109/tim.2004.843071.

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12

Tan, Xin, Yu Qing Li, Xue Jie Liu i Yan Hui Xie. "Structural and Mechanical Properties of Ti1-XAlxN Studied by Ab Initio". Advanced Materials Research 383-390 (listopad 2011): 3331–37. http://dx.doi.org/10.4028/www.scientific.net/amr.383-390.3331.

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Ti1-xAlxN films have been shown to exhibit superior mechanical and thermal properties and are thus widely used for industrial applications. We have studied the structural and mechanical properties of fcc-TiN and fcc-Ti1-xAlxN solid solution (x=0.25 and x=0.5), using first principles calculations based on the density functional theory. These calculations provide the lattice parameter, total energy, cohesive energy, elastic constants, etc, of the TiN lattice and when Al atoms replace Ti atoms in the TiN lattice. With regard to the cohesive energy of TiN and fcc-Ti1-xAlxN, we can obtain that the fcc-Ti1-xAlxN is metastable. Via comparation and analysis, it’s shown that the lattice parameter, cohesive energy and elastic constants decrease with increasing the content of Al. However, ductile behavior is promoted by Al addition.
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13

Zhao, Xiumin. "New comparator-type calibrator for instrument transformers". IEEE Transactions on Instrumentation and Measurement IM-36, nr 3 (wrzesień 1987): 755–58. http://dx.doi.org/10.1109/tim.1987.6312784.

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14

Avramov, S., i I. Zapunski. "An AC comparator for audio frequency waveforms". IEEE Transactions on Instrumentation and Measurement 40, nr 2 (kwiecień 1991): 373–76. http://dx.doi.org/10.1109/tim.1990.1032963.

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15

Abumurad, Abdulrahman, i Kyusun Choi. "Design Procedure and Selection of TIQ Comparators for Flash ADCs". Circuits, Systems, and Signal Processing 37, nr 2 (25.05.2017): 500–531. http://dx.doi.org/10.1007/s00034-017-0574-x.

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16

Met, Andrzej, Krzysztof Musiol i Tadeusz Skubis. "Vector Voltmeter for High-Precision Unbalanced Comparator Bridge". IEEE Transactions on Instrumentation and Measurement 60, nr 2 (luty 2011): 577–83. http://dx.doi.org/10.1109/tim.2010.2058555.

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17

Nakazoe, Jun, Kazuyuki Seki i Minoru Abe. "A cascade comparator ADC using a magnetic modulator". IEEE Transactions on Instrumentation and Measurement IM-36, nr 2 (czerwiec 1987): 440–42. http://dx.doi.org/10.1109/tim.1987.6312716.

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18

Williams, J. M., i A. Hartland. "An automated cryogenic current comparator resistance ratio bridge". IEEE Transactions on Instrumentation and Measurement 40, nr 2 (kwiecień 1991): 267–70. http://dx.doi.org/10.1109/tim.1990.1032934.

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19

Vasjanov, Aleksandr, i Vaidotas Barzdėnas. "DESIGN OF A 65 NM CMOS COMPARATOR WITH HYSTERESIS / 65 NM KMOP TECHNOLOGIJOS HISTEREZINIO KOMPARATORIAUS PROJEKTAVIMAS". Mokslas – Lietuvos ateitis 6, nr 2 (24.04.2014): 202–5. http://dx.doi.org/10.3846/mla.2014.30.

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The comparator can be described as one of the basic building blocks in electronics. It is implemented both as a discrete device and as a constituent of a complex circuit. In both cases, the circuits usually operate in conditions, where useful and unwanted (noise) signals are present at the same time. In order to maintain the validity of output data, a hysteresis parameter is introduced to the comparator’s circuit. This article presents the results of a CMOS comparator with hysteresis design – the schematic, topology and simulation results are analyzed. The designed comparator is implemented in a zero voltage offset compensation circuit ADC in a multi-standard transceiver IC. Komparatorius yra vienas iš pagrindinių elektronikos įtaisų. Jis yra naudojamas kaip diskretinis elementas arba kaip viena iš sudėtingesnės sistemos sudedamųjų dalių. Šie įtaisai dažnai veikia elektronikos sistemose, kuriose egzistuoja ne tik informaciją nešantys bei apdorojami signalai, bet ir nepageidautini triukšmo signalai. Siekiant tokiomis sąlygomis užtikrinti patikimą ir efektyvią komparatoriaus veiką, imama taikyti histerezė. Šiame straipsnyje pateikiami TSMC 65 nm KMOP histerezinio komparatoriaus projektavimo rezultatai: aptariama principinė elektrinė schema, pateikiama suprojektuota topologija, jos kompiuterinio modeliavimo rezultatai bei išvados. Šis komparatorius bus naudojamas daugiastandarčio, daugiakanalio siųstuvo-imtuvo grandinėje, nulinio potencialo poslinkio įtampą nustatančiame, lygiagrečios architektūros analoginiame skaitmeniniame keitiklyje (ASK).
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20

Santra, Sanchayan, Ranjan Mondal i Bhabatosh Chanda. "Learning a Patch Quality Comparator for Single Image Dehazing". IEEE Transactions on Image Processing 27, nr 9 (wrzesień 2018): 4598–607. http://dx.doi.org/10.1109/tip.2018.2841198.

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21

Bierzychudek, M. E., i R. E. Elmquist. "Uncertainty Evaluation in a Two-Terminal Cryogenic Current Comparator". IEEE Transactions on Instrumentation and Measurement 58, nr 4 (kwiecień 2009): 1170–75. http://dx.doi.org/10.1109/tim.2008.2006967.

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22

Gotz, Martin, Dietmar Drung, Eckart Pesel, Henry-Jobes Barthelmess, Colmar Hinnrichs, Cornelia Assmann, Margret Peters, HansjÖrg Scherer, Bernd Schumacher i Thomas Schurig. "Improved Cryogenic Current Comparator Setup With Digital Current Sources". IEEE Transactions on Instrumentation and Measurement 58, nr 4 (kwiecień 2009): 1176–82. http://dx.doi.org/10.1109/tim.2008.2012379.

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23

Bierzychudek, M. E., R. S. Sanchez-Pena i Alejandra Tonina. "Robust Control of a Two-Terminal Cryogenic Current Comparator". IEEE Transactions on Instrumentation and Measurement 62, nr 6 (czerwiec 2013): 1736–42. http://dx.doi.org/10.1109/tim.2013.2240954.

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So, Eddy. "A microprocessor-controlled current-comparator-based DC voltage calibrator". IEEE Transactions on Instrumentation and Measurement IM-36, nr 2 (czerwiec 1987): 291–95. http://dx.doi.org/10.1109/tim.1987.6312689.

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Hao, L., J. C. Macfarlane, S. Haining i J. C. Gallop. "HTS Superconducting Current Comparator: Dynamic Range and Noise Limits". IEEE Transactions on Instrumentation and Measurement 54, nr 2 (kwiecień 2005): 584–87. http://dx.doi.org/10.1109/tim.2005.843575.

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Bierzychudek, Marcos Eduardo, Martin Gotz, Ricardo S. Sanchez-Pena, Ricardo Iuzzolino i Dietmar Drung. "Application of Robust Control to a Cryogenic Current Comparator". IEEE Transactions on Instrumentation and Measurement 66, nr 6 (czerwiec 2017): 1095–102. http://dx.doi.org/10.1109/tim.2017.2648898.

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Xiaobing, He, Wang Wei, Zhang Xin i Dai Dongxue. "Research on High Accuracy Current Comparator and Self-Calibration Methods". IEEE Transactions on Instrumentation and Measurement 62, nr 6 (czerwiec 2013): 1669–74. http://dx.doi.org/10.1109/tim.2013.2253978.

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So, Eddy. "A Current-Comparator-Based 20-Bit Digital-to-Analog Converter". IEEE Transactions on Instrumentation and Measurement IM-34, nr 2 (czerwiec 1985): 278–82. http://dx.doi.org/10.1109/tim.1985.4315324.

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Williams, Earl S., i Joseph R. Kinard. "A Dual-Channel Automated Comparator for AC-DC Difference Measurements". IEEE Transactions on Instrumentation and Measurement IM-34, nr 2 (czerwiec 1985): 290–94. http://dx.doi.org/10.1109/tim.1985.4315327.

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30

Rietveld, G., E. Bartolome, J. Sese, P. de la Court, J. Flokstra, C. Rillo i A. Camon. "1:30 000 cryogenic current comparator with optimum squid readout". IEEE Transactions on Instrumentation and Measurement 52, nr 2 (kwiecień 2003): 621–25. http://dx.doi.org/10.1109/tim.2003.809916.

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Sese, J., E. Bartolome, A. Camon, J. Flokstra, G. Rietveld i C. Rillo. "Simplified calculus for the design of a cryogenic current comparator". IEEE Transactions on Instrumentation and Measurement 52, nr 2 (kwiecień 2003): 612–16. http://dx.doi.org/10.1109/tim.2003.811579.

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Bergman, D. I., i B. C. Waltrip. "A low-noise latching comparator probe for waveform sampling applications". IEEE Transactions on Instrumentation and Measurement 52, nr 4 (sierpień 2003): 1107–13. http://dx.doi.org/10.1109/tim.2003.815982.

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Trinchera, Bruno, Danilo Serazio i Umberto Pogliano. "Asynchronous Phase Comparator for Characterization of Devices for PMUs Calibrator". IEEE Transactions on Instrumentation and Measurement 66, nr 6 (czerwiec 2017): 1139–45. http://dx.doi.org/10.1109/tim.2017.2648598.

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Trinchera, Bruno, Vincenzo D'Elia i Luca Callegaro. "A Digitally Assisted Current Comparator Bridge for Impedance Scaling at Audio Frequencies". IEEE Transactions on Instrumentation and Measurement 62, nr 6 (czerwiec 2013): 1771–75. http://dx.doi.org/10.1109/tim.2013.2238011.

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Delahaye, Francois, i Dominique Reymann. "Progress in Resistance Ratio Measurements Using a Cryogenic Current Comparator at LCIE". IEEE Transactions on Instrumentation and Measurement IM-34, nr 2 (czerwiec 1985): 316–19. http://dx.doi.org/10.1109/tim.1985.4315334.

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Ling Hao, J. C. Gallop, J. C. Macfarlane i C. Carr. "HTS cryogenic current comparator for non-invasive sensing of charged particle beams". IEEE Transactions on Instrumentation and Measurement 52, nr 2 (kwiecień 2003): 617–20. http://dx.doi.org/10.1109/tim.2003.810456.

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Ren, S., H. Yang i X. Wang. "The Theoretical Analysis of Open-Loop Characteristic for Double Magnetic Detector Comparator". IEEE Transactions on Instrumentation and Measurement 54, nr 2 (kwiecień 2005): 592–94. http://dx.doi.org/10.1109/tim.2004.843350.

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Yu, Haoyu, Xiaolong Chen, Jinsong Zhan i Zhaoxiang Chen. "A Long-Range High Applicability Length Comparator for Linear Displacement Sensor Calibration". IEEE Transactions on Instrumentation and Measurement 70 (2021): 1–10. http://dx.doi.org/10.1109/tim.2020.3011795.

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Bierzychudek, Marcos Eduardo, Ricardo S. Sanchez-Pena i Alejandra Tonina. "Identification and Control of a Cryogenic Current Comparator Using Robust Control Theory". IEEE Transactions on Instrumentation and Measurement 64, nr 12 (grudzień 2015): 3451–57. http://dx.doi.org/10.1109/tim.2015.2459472.

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Djokic, Branislav, i Harold Parks. "A Synchronized Current-Comparator Bridge for the Calibration of Analog Merging Units". IEEE Transactions on Instrumentation and Measurement 68, nr 6 (czerwiec 2019): 1955–60. http://dx.doi.org/10.1109/tim.2018.2882117.

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41

Kinard, J. R., T. E. Lipe i S. Avramov-Zamurovic. "A new binary inductive divider comparator system for measuring high-voltage thermal converters". IEEE Transactions on Instrumentation and Measurement 51, nr 5 (październik 2002): 1045–49. http://dx.doi.org/10.1109/tim.2002.807794.

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Morath, C. P., K. Vaccaro, W. Buchwald i W. R. Clark. "Comparator-Based Measurement Scheme for Dark-Count Rates in Single Photon Avalanche Diodes". IEEE Transactions on Instrumentation and Measurement 54, nr 5 (październik 2005): 2020–26. http://dx.doi.org/10.1109/tim.2005.853347.

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Callegaro, Luca, Vincenzo D'Elia, Massimo Ortolano i Faranak Pourdanesh. "A Three-Arm Current Comparator Bridge for Impedance Comparisons Over the Complex Plane". IEEE Transactions on Instrumentation and Measurement 64, nr 6 (czerwiec 2015): 1466–71. http://dx.doi.org/10.1109/tim.2015.2398953.

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Callegaro, Luca, Vincenzo D'Elia, Jan Kucera, Massimo Ortolano, Faranak Pourdanesh i Bruno Trinchera. "Self-Compensating Networks for Four-Terminal-Pair Impedance Definition in Current Comparator Bridges". IEEE Transactions on Instrumentation and Measurement 65, nr 5 (maj 2016): 1149–55. http://dx.doi.org/10.1109/tim.2015.2490898.

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Gotz, Martin, i Dietmar Drung. "Stability and Performance of the Binary Compensation Unit for Cryogenic Current Comparator Bridges". IEEE Transactions on Instrumentation and Measurement 66, nr 6 (czerwiec 2017): 1467–74. http://dx.doi.org/10.1109/tim.2017.2659998.

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46

Hwu, K. I., i Y. T. Yau. "Applying One-Comparator Counter-Based Sampling to Current Sharing Control of Multichannel LED Strings". IEEE Transactions on Industry Applications 47, nr 6 (listopad 2011): 2413–21. http://dx.doi.org/10.1109/tia.2011.2168596.

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47

Faisal, Agah, Jae Kap Jung i Eddy So. "A Modified Technique for Calibration of Current-Comparator-Based Capacitance Bridge and Its Verification". IEEE Transactions on Instrumentation and Measurement 60, nr 7 (lipiec 2011): 2642–47. http://dx.doi.org/10.1109/tim.2010.2096952.

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Shiyan Ren i Hengchun Ding. "A 300 000- a high precision DC comparator for on-line calibration and measurement". IEEE Transactions on Instrumentation and Measurement 40, nr 2 (kwiecień 1991): 281–83. http://dx.doi.org/10.1109/tim.1990.1032938.

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Elmquist, R. E., E. Hourdakis, D. G. Jarrett i N. M. Zimmerman. "Direct Resistance Comparisons From the QHR to 100 MΩ Using a Cryogenic Current Comparator". IEEE Transactions on Instrumentation and Measurement 54, nr 2 (kwiecień 2005): 525–28. http://dx.doi.org/10.1109/tim.2004.843330.

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Poirier, Wilfrid, Dominique Leprat i Felicien Schopfer. "A Resistance Bridge Based on a Cryogenic Current Comparator Achieving Sub-10⁻⁹ Measurement Uncertainties". IEEE Transactions on Instrumentation and Measurement 70 (2021): 1–14. http://dx.doi.org/10.1109/tim.2020.3010111.

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