Gotowe bibliografie tematyczne / Timed automata

Spis treści

Artykuły w czasopismach
Rozprawy doktorskie
Książki
Części książek
Streszczenia konferencji
Raporty organizacyjne

Gotowa bibliografia na temat „Timed automata”

Autor: Grafiati

Data publikacji: 4 czerwca 2021

Data aktualizacji: 8 czerwca 2024

Utwórz poprawne odniesienie w stylach APA, MLA, Chicago, Harvard i wielu innych

Wybierz rodzaj źródła:

Zobacz listy aktualnych artykułów, książek, rozpraw, streszczeń i innych źródeł naukowych na temat „Timed automata”.

Przycisk „Dodaj do bibliografii” jest dostępny obok każdej pracy w bibliografii. Użyj go – a my automatycznie utworzymy odniesienie bibliograficzne do wybranej pracy w stylu cytowania, którego potrzebujesz: APA, MLA, Harvard, Chicago, Vancouver itp.

Możesz również pobrać pełny tekst publikacji naukowej w formacie „.pdf” i przeczytać adnotację do pracy online, jeśli odpowiednie parametry są dostępne w metadanych.

Artykuły w czasopismach na temat "Timed automata"

Boumaza, Amel, i Ramdane Maamri. "Mapping OWL-S Process Model to Timed Automata". Journal of Information Technology Research 11, nr 1 (styczeń 2018): 29–48. http://dx.doi.org/10.4018/jitr.2018010103.

Pełny tekst źródła

Streszczenie:

The conversion of web services to semantic web comes the opportunity to automate various tasks. OWL-S plays a key role in describing web services behaviour. While ontology-based semantics given to OWL-S is structural rather than behaviourally oriented, we cannot automate an essential task in this field, verification. In this article, the mapping of OWL-S process model to Timed automata is investigated, which is a suitable formalism for real time systems modeling and automatic verification. Hence, this has led to not only enabling automatic verification but also covering problems related to automated verification of temporal quantitative properties as bounded liveness property. As a starting point, the OWL-S and sub entry of time ontologies for describing the timed behaviour of services has been chosen. A defined set of mapping rules is used to automatically encode control constructs defined in OWL-S and temporal information into timed automata. Also, it is shown how a Uppaal checker is used to check required properties formulated in TCTL. Finally, an EClinic case study is used to illustrate the technique.

Style APA, Harvard, Vancouver, ISO itp.

FIGUEIRA, DIEGO, PIOTR HOFMAN i SŁAWOMIR LASOTA. "Relating timed and register automata". Mathematical Structures in Computer Science 26, nr 6 (5.12.2014): 993–1021. http://dx.doi.org/10.1017/s0960129514000322.

Pełny tekst źródła

Streszczenie:

Timed and register automata are well-known models of computation over timed and data words, respectively. The former has clocks that allow to test the lapse of time between two events, whilst the latter includes registers that can store data values for later comparison. Although these two models behave differently in appearance, several decision problems have the same (un)decidability and complexity results for both models. As a prominent example, emptiness is decidable for alternating automata with one clock or register, both with non-primitive recursive complexity. This is not by chance.This work confirms that there is indeed a tight relationship between the two models. We show that a run of a timed automaton can be simulated by a register automaton over ordered data domain, and conversely that a run of a register automaton can be simulated by a timed automaton. These are exponential time reductions hold both in the finite and infinite words settings. Our results allow to transfer decidability results back and forth between these two kinds of models, as well complexity results modulo an exponential time reduction. We justify the usefulness of these reductions by obtaining new results on register automata.

Style APA, Harvard, Vancouver, ISO itp.

Nielsen, Brian, i Arne Skou. "Automated test generation from timed automata". International Journal on Software Tools for Technology Transfer 5, nr 1 (17.06.2003): 59–77. http://dx.doi.org/10.1007/s10009-002-0094-1.

Pełny tekst źródła

Style APA, Harvard, Vancouver, ISO itp.

Lanotte, Ruggero, Andrea Maggiolo-Schettini i Adriano Peron. "Timed Cooperating Automata". Fundamenta Informaticae 43, nr 1-4 (2000): 153–73. http://dx.doi.org/10.3233/fi-2000-43123408.

Pełny tekst źródła

Style APA, Harvard, Vancouver, ISO itp.

Barbuti, Roberto, Andrea Maggiolo-Schettini, Paolo Milazzo i Luca Tesei. "Timed P Automata". Fundamenta Informaticae 94, nr 1 (2009): 1–19. http://dx.doi.org/10.3233/fi-2009-114.

Pełny tekst źródła

Style APA, Harvard, Vancouver, ISO itp.

Jin Song Dong, Ping Hao, Shengchao Qin, Jun Sun i Wang Yi. "Timed Automata Patterns". IEEE Transactions on Software Engineering 34, nr 6 (listopad 2008): 844–59. http://dx.doi.org/10.1109/tse.2008.52.

Pełny tekst źródła

Style APA, Harvard, Vancouver, ISO itp.

Lasota, Slawomir, i Igor Walukiewicz. "Alternating timed automata". ACM Transactions on Computational Logic 9, nr 2 (marzec 2008): 1–27. http://dx.doi.org/10.1145/1342991.1342994.

Pełny tekst źródła

Style APA, Harvard, Vancouver, ISO itp.

Krishnan, Padmanabhan. "Distributed Timed Automata". Electronic Notes in Theoretical Computer Science 28 (2000): 5–21. http://dx.doi.org/10.1016/s1571-0661(05)80627-9.

Pełny tekst źródła

Style APA, Harvard, Vancouver, ISO itp.

Springintveld, Jan, Frits Vaandrager i Pedro R. D'Argenio. "Testing timed automata". Theoretical Computer Science 254, nr 1-2 (marzec 2001): 225–57. http://dx.doi.org/10.1016/s0304-3975(99)00134-6.

Pełny tekst źródła

Style APA, Harvard, Vancouver, ISO itp.

Bouyer, Patricia, Catherine Dufourd, Emmanuel Fleury i Antoine Petit. "Updatable timed automata". Theoretical Computer Science 321, nr 2-3 (sierpień 2004): 291–345. http://dx.doi.org/10.1016/j.tcs.2004.04.003.

Pełny tekst źródła

Style APA, Harvard, Vancouver, ISO itp.

Więcej źródeł

Rozprawy doktorskie na temat "Timed automata"

Carlier, Pierre. "Verification of Stochastic Timed Automata". Thesis, Université Paris-Saclay (ComUE), 2017. http://www.theses.fr/2017SACLN058/document.

Pełny tekst źródła

Streszczenie:

La vérification est maintenant une branche très connue des sciences informatiques. Elle est cruciale lorsque l'on a affaire à des programmes informatiques dans des systèmes automatiques : on veut vérifier si un système donné est correct et s'il satisfait des propriétés nécessaires à son bon fonctionnement. Une façon d'analyser ces systèmes se fait par la modélisation mathématique. La question est alors : peut-on vérifier si le modèle satisfait les propriétés requises ? C'est ce que l'on appelle le problème du model-checking. Plusieurs modèles ont été étudiés dans la littérature. Nous portons notre intérêt sur des modèles qui peuvent mêler des aspects temporels et des aspects probabilistes. Dans cette thèse, nous étudions donc le modèle des automates temporisés et stochastiques (ATS). Les contributions de ce document sont divisées en deux parties. Tout d'abord, nous étudions les problèmes de model-checking qualitatifs et quantitatifs des ATS. Les ATS sont, en particulier, des systèmes probabilistes généraux et avec de tels modèles, on est intéressé par des questions du type : « Une propriété est-elle satisfaite, au sein d'un modèle donné, avec probabilité 1 ? » (qualitatif) ou bien « Peut-on calculer une approximation de la probabilité que le modèle satisfait une propriété donnée ? » (quantitatif).Nous étudions ces questions dans des systèmes probabilistes généraux en utilisant, entre autres, la notion de decisiveness utilisée dans les chaînes de Markov infinie dans le but d'obtenir d'importants résultats qualitatifs et que nous étendons ici dans notre contexte plus général. Nous prouvons plusieurs résultats pour les problèmes de model-checking qualitatifs et quantitatifs de ces systèmes probabilistes, certains d'entre eux étant des extensions de travaux antérieurs sur les chaînes de Markov, d'autres étant nouveaux, et nous montrons comment l'on peut appliquer ces résultats sur des sous-classes des ATS. Nous étudions ensuite la vérification compositionnelle des ATS. En général, un système est le résultat de plusieurs plus petits systèmes fonctionnant ensemble. La vérification compositionnelle permet alors de réduire l'analyse de gros systèmes aux analyses des plus petits systèmes qui le composent. Il est donc crucial d'avoir une bonne structure compositionnelle au sein des modèles mathématiques, et cela manque aux ATS. Dans cette thèse, nous définissons un opérateur de composition pour les ATS. Nous faisons d'abord l'hypothèse que les ATS composés fonctionnent complètement indépendamment l'un de l'autre, c'est-à-dire les ATS ne communiquent pas entre eux. Nous prouvons que notre définition satisfait bien cette hypothèse d'indépendance. Un tel opérateur de composition n'est pas très intéressant puisque, généralement, les systèmes interagissent entre eux. Mais c'est une première étape nécessaire. Nous introduisons donc le nouveau modèle des ATS interactifs (ATSI) qui vont permettre des interactions entre les systèmes. Nous définissons un opérateur de composition dans les ATSI qui va rendre possible des synchronisations entre les systèmes et qui est construit sur la précédente composition dans les ATS. Nous finissons cette thèse par l'identification d'une sous-classe de ATSI dans laquelle tous les résultats qualitatifs et quantitatifs fournis dans cette thèse peuvent être appliqués, et qui est donc accompagnée d'une bonne structure compositionnelle au sein du modèle
Verification is now a well-known branch in computer science. It is crucial when dealing with computer programs in automatic systems: we want to check if a given system is correct and satisfies some specifications that should be met. One way to analyse those systems is to model them mathematically. The question is then: can we check if the model satisfies the required specifications ? This is called the model-checking problem. Several models have been studied in the literature. We have an interest for models that can mix both timing and randomized aspects. In this thesis we thus study the stochastic timed automaton model (STA). The contributions of this document are twofold. First, we study the qualitative and quantitative model-checking problems of STA. STA are, in particular, general probabilistic systems and with such model, one is thus interested in questions like « Is a property satisfied, within a given model, with probability 1 ? » (qualitative) or « Can we compute an approximation of the probability that the model satisfies a given property ? » (quantitative).We study those questions for general stochastic systems using, amongst other, the notion of decisiveness used in infinite Markov chains in order to get strong qualitative and quantitative results, and that we extend here in or more general context. We prove several results for the qualitative and quantitative model-checking problems of those probabilistic systems, some of them being extensions of previous work on Markov chains, others being new, and we show how it can be applied to subclasses of STA. Then we study the compositional verification in STA. In general, a system is the result of several smaller systems working together. Compositional verification allows then one to reduce the analysis of a big system to the analyses of the smaller systems which compose it. It is then crucial to have a good compositional framework in mathematical models, and this lacks in STA. In this thesis, we define an operator of composition for STA. We first make the assumption that the STA composed run completely independently from each other, i.e. they do not communicate between them. We prove that our definition satisfies indeed this independence assumption. Such an operator of composition is not very interesting as in general, systems do communicate. But it is a necessary first step. We then introduce the new model of interactive STA (ISTA) that will allow for interactions between the systems. We define an operator of composition in ISTA that will make synchronisations possible between the systems and that is built on the previous composition in STA. We end this thesis with the identification of a subclass of ISTA in which all the qualitative and quantitative results provided in this thesis can be applied, and which thus comes with the nice compositional framework defined in the model

Style APA, Harvard, Vancouver, ISO itp.

Park, Young-Saeng. "Automatic schedule computation for distributed real-time systems using timed automata". Thesis, Northumbria University, 2008. http://nrl.northumbria.ac.uk/745/.

Pełny tekst źródła

Streszczenie:

The time-triggered architecture is becoming accepted as a means of implementing scalable, safer and more reliable solutions for distributed real-time systems. In such systems, the execution of distributed software components and the communication of messages between them take place in a fixed pattern and are scheduled in advance within a given scheduling round by a global scheduling policy. The principal obstacle in the design of time-triggered systems is the difficulty of finding the static schedule for all resources which satisfies constraints on the activities within the scheduling round, such as the meeting of deadlines. The scheduler has to consider not only the requirements on each processor but also the global requirements of system-wide behaviour including messages transmitted on networks. Finding an efficient way of building an appropriate global schedule for a given system is a major research challenge. This thesis proposes a novel approach to designing time-triggered schedules which is radically different from existing mathematical methods or algorithms for schedule generation. It entails the construction of timed automata to model the arrival and execution of software tasks and inter-task message communication for a system; the behaviour of an entire distributed system is thus a parallel composition of these timed automata models. A job comprises a sequence of tasks and messages; this expresses a system-wide transaction which may be distributed over a system of processors and networks. The job is formalized by a timed automata based on the principle that a task or message can be modelled by finite states and a clock variable. Temporal logic properties are formed to express constraints on the behaviour of the system components such as precedence relationships between tasks and messages and adherence to deadlines. Schedules are computed by formally verifying that these properties hold for an evolution of the system; a successful schedule is simply a trace generated by the verifier, in this case the UPPAAL model-checking tool has been employed to perform the behaviour verification. This approach guarantees to generate a practical schedule if one exists and will fail to construct any schedule if none exists. A prototype toolset has been developed to automate the proposed approach to create of timed automata models, undertake the analysis, extract schedules from traces and visualize the generated schedules. Two case studies, one of a cruise control system, the other a manufacturing cell system, are presented to demonstrate the applicability and usability of the approach and the application of the toolset. Finally, further constraints are considered in order to yield schedules with limited jitter, increased efficiency and system-wide properties.

Style APA, Harvard, Vancouver, ISO itp.

Amnell, Tobias. "Code synthesis for timed automata". Licentiate thesis, Uppsala universitet, Avdelningen för datorteknik, 2003. http://urn.kb.se/resolve?urn=urn:nbn:se:uu:diva-86154.

Pełny tekst źródła

Streszczenie:

In this thesis, we study executable behaviours of timed models. The focus is on synthesis of executable code with predictable behaviours from high level abstract models. We assume that a timed system consists of two parts: the control software and the plant (i.e. the environment to be controlled). Both are modelled as timed automata extended with real time tasks. We consider the extended timed automata as design models. We present a compilation procedure to transform design models to executable code including a run-time scheduler (run time system) preserving the correctness and schedulability of the models. The compilation procedure has been implemented in a prototype C-code generator for the brickOS operating system included in the Times tool. We also present an animator, based on hybrid automata, to be used to describe a simulated environment (i.e. the plant) for timed systems. The tasks of the hybrid automata define differential equations and the animator uses a differential equations solver to calculate step-wise approximations of real valued variables. The animated objects, described as hybrid automata, are compiled by the Times tool into executable code using a similar procedure as for controller software. To demonstrate the applicability of timed automata with tasks as a design language we have developed the control software for a production cell. The production cell is built in LEGO and is controlled by a Hitachi H8 based LEGO-Mindstorms control brick. The control software has been analysed (using the Times tool) for schedulability and other safety properties. Using results from the analysis we were able to avoid generating code for parts of the design that could never be reached, and could also limit the amount of memory allocated for the task queue.

Style APA, Harvard, Vancouver, ISO itp.

Trivedi, Ashutosh. "Competative optimisation on timed automata". Thesis, University of Warwick, 2009. http://wrap.warwick.ac.uk/2243/.

Pełny tekst źródła

Streszczenie:

Timed automata are finite automata accompanied by a finite set of real-valued variables called clocks. Optimisation problems on timed automata are fundamental to the verification of properties of real-time systems modelled as timed automata, while the control-program synthesis problem of such systems can be modelled as a two-player game. This thesis presents a study of optimisation problems and two-player games on timed automata under a general heading of competitive optimisation on timed automata. This thesis views competitive optimisation on timed automata as a multi-stage decision process, where one or two players are confronted with the problem of choosing a sequence of timed moves—a time delay and an action—in order to optimise their objectives. A solution of such problems consists of the “optimal” value of the objective and an “optimal” strategy for each player. This thesis introduces a novel class of strategies, called boundary strategies, that suggest to a player a symbolic timed move of the form (b, c, a)— “wait until the value of the clock c is in very close proximity of the integer b, and then execute a transition labelled with the action a”. A distinctive feature of the competitive optimisation problems discussed in this thesis is the existence of optimal boundary strategies. Surprisingly perhaps, many competitive optimisation problems on timed automata of practical interest admit optimal boundary strategies. For example, optimisation problems with reachability price, discounted price, and average-price objectives, and two-player turn-based games with reachability time and average time objectives. The existence of optimal boundary strategies allows one to work with a novel abstraction of timed automata, called a boundary region graph, where players can use only boundary strategies. An interesting property of a boundary region graph is that, for every state, the set of reachable states is finite. Hence, the existence of optimal boundary strategies permits us to reduce competitive optimisation problem on a timed automaton to the corresponding competitive optimisation problem on a finite graph.

Style APA, Harvard, Vancouver, ISO itp.

Sankur, Ocan. "Robustness in timed automata : analysis, synthesis, implementation". Phd thesis, École normale supérieure de Cachan - ENS Cachan, 2013. http://tel.archives-ouvertes.fr/tel-00910333.

Pełny tekst źródła

Streszczenie:

Timed automata are a formalism to model, verify, and synthesize real-time systems. They have the advantage of having an abstract mathematical semantics, which allow formalizing and solving several verification and synthesis problems. However, timed automata are intended to design models, rather than completely describe real systems. Therefore, once the design phase is over, it remains to check whether the behavior of an actual implementation corresponds to that of the timed automaton model. An important step before implementing a system design is ensuring its robustness. This thesis considers a notion of robustness that asks whether the behavior of a given timed automaton is preserved, or can be made so, when it is subject to small perturbations. Several approaches are considered: Robustness analysis seeks to decide whether a given timed automaton tolerates perturbations, and in that case to compute the (maximum) amount of tolerated perturbations. In robust synthesis, a given system needs to be controlled by a law (or strategy) which tolerates perturbations upto some computable amount. In robust implementation, one seeks to automatically transform a given timed automaton model so that it tolerates perturbations by construction. Several perturbation models are considered, ranging from introducing error in time measures (guard enlargement), forbidding behaviors that are too close to boundaries (guard shrinking), and restricting the time domain to a discrete sampling. We also formalize robust synthesis problems as games, where the control law plays against the environment which can systematically perturb the chosen moves, by some bounded amount. These problems are studied on timed automata and their variants, namely, timed games, and weighted timed automata and games. Algorithms for the parameterized robustness analysis against guard enlargements, and guard shrinkings are presented. The robust synthesis problem is studied for two variants of the game semantics, for timed automata, games, and their weighted extensions. A software tool for robustness analysis against guard shrinkings is presented, and experimental results are discussed. The robust implementation problem is also studied in two different settings. In all algorithms, an upper bound on perturbations that the given timed automaton tolerates can be computed.

Style APA, Harvard, Vancouver, ISO itp.

Ericsson, Ann-Marie. "Deriving ECA-rules from timed-automata specifications". Thesis, University of Skövde, Department of Computer Science, 2002. http://urn.kb.se/resolve?urn=urn:nbn:se:his:diva-655.

Pełny tekst źródła

Streszczenie:

Real-time systems are required to answer to external stimuli within a specified time-period. For this to be possible, the systems behaviour must be predictable. The use of active databases in real-time systems introduces unpredictability in the system, e.g. due to their use of active rules. The behaviour in active databases is usually specified in ECA-rules. Sets of ECA-rules are hard to analyse, which implies that the behaviour of the ECA-rule set is hard to predict.

The purpose of this project is to evaluate the ability to support the development of a predictable ECA-rule set. Using a formal method for the specification task is desirable, since a formal specification is analysable and can be proven correct. In this project, timed-automata are used for specifying the systems behaviour. A method for deriving predictable ECA-rules from a timed-automaton specification is developed, and successfully applied on a case-study specification. For this case-study specification, a set of ECA-rules preserving the analysed behaviour of the timed-automata specification is derived.

Style APA, Harvard, Vancouver, ISO itp.

Nehme, Carl 1981. "The VAT tool : automatic transformation of VHDL to timed automata". Thesis, Massachusetts Institute of Technology, 2004. http://hdl.handle.net/1721.1/17790.

Pełny tekst źródła

Streszczenie:

Thesis (S.M.)--Massachusetts Institute of Technology, Dept. of Aeronautics and Astronautics, 2004.
Includes bibliographical references (leaves 61-66).
Embedded systems have become an integral part of the systems we use today. These types of systems are constrained by both stringent time requirements and limited resource availability. Traditionally, high-integrity embedded systems operated on well understood hardware platforms. The emergence of inexpensive FPGAs (Field Programmable Gate Arrays) and ASICs (Application Specific Integrated Circuits) as operational platforms for embedded software, has resulted in the system developer having to verify both the hardware and the software components. The stringent processes used over the system development lifecycle have to be augmented to account for this paradigm shift. One possible approach is to create a homogenous formal model that accounts for both the hardware and the software components of the system. This thesis focuses on making a contribution to the extraction of formal models from the VHDL specification of the operational platform. The research underlying this thesis was driven by the goals of: a) augmenting the system developer's verification and validation toolbox with a powerful yet easy-to-use tool; b) developing a tool that is modular, extensible, and adaptable to changing customer requirements; c) providing a transparent transformation process, which can be leveraged by both academia and industry. The thesis discusses in detail, the design and development of the VAT tool, that transforms VHDL specifications into finite state machines. It discusses the use of model checking on the extracted formal model and presents a visualization technique that enables manual inspection of the formal model.
by Carl Nehme.
S.M.

Style APA, Harvard, Vancouver, ISO itp.

Hagman, Mikael. "Instrumentation of timed automata for formal verification of timed properties". Thesis, Linköping University, Department of Computer and Information Science, 2007. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-9861.

Pełny tekst źródła

Streszczenie:

Embedded systems are used in many technical products of today. The tendency also points to the fact that they are in many ways becoming more and more complex as technology advances. Systems like advanced avionics, air bags, ABS brakes or any real-time embedded system requires reliability, correctness and timeliness. This puts hard pressure on designers, analyzers and developers. The need for high performance and non failing systems has therefore led to a growing interest in modeling and verification of component-based embedded systems in order to reduce costs and simplify design and development. The solution proposed by the Embedded Systems Lab at Linköping University is the modeling language PRES+, Petri Net based Representation for Embedded Systems.

PRES+ models are then translated into timed automata, TA, which is used by the UPPAAL verification tool. To be able to verify timing properties the translated TA model must be instrumented with certain timers, called clocks. These clocks must be reset in a manner reflected by the property to be verified.

This thesis will provide a solution to the problem and also give the reader necessary information in order to understand the theoretical background needed. The thesis will also show the reader the importance of modeling and time verification in the development of embedded systems. A simple example is used to describe and visualize the benefit regarding real-time embedded systems as well as the importance of the ability to verify these systems.

The conclusion drawn stresses the fact that high development costs, possible gain of human lives and the problems in developing complex systems only emphasize the need for easy to handle and intuitive verification methods.

Style APA, Harvard, Vancouver, ISO itp.

Mavrommatis, Panayiotis P. "Simulation of timed input/output automata". Thesis, Massachusetts Institute of Technology, 2006. http://hdl.handle.net/1721.1/36395.

Pełny tekst źródła

Streszczenie:

Thesis (M. Eng.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2006.
This electronic version was submitted by the student author. The certified thesis is available in the Institute Archives and Special Collections.
Includes bibliographical references (p. 73-74).
This Master of Engineering Thesis describes the design, implementation, and usage of the TIOA Simulator. The TIOA Simulator, along with the other components of the TIOA Toolset aims to provide a framework for developing dependable distributed systems. The project is based on the Timed Input/Output Automaton framework, and supports TIOA, a formal language for specifying timed I/O automata. Simulation of TIOA programs is useful in the process of testing the proposed system over a specific set of executions. During the execution the Simulator is able to test proposed invariants and validate a proposed simulation relation between the system's implementation and its specification. A step correspondence between the steps of the implementation and the specification drives the validation of the simulation relation. The identification and validation of the invariants and the simulation relation constitutes the first step towards a formal verification of the system's correctness. The proposed step correspondence can be used in a formal proof to show that the proposed relation is indeed a simulation relation.
by Panayiotis P. Mavrommatis.
M.Eng.

Style APA, Harvard, Vancouver, ISO itp.

Widerberg, Ernst. "A Modeling Language for Timed Automata". Thesis, KTH, Skolan för elektroteknik och datavetenskap (EECS), 2021. http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-291554.

Pełny tekst źródła

Streszczenie:

This work details the design and implementation of a modeling language for timed automata. The primary intended use of the language TML is as an interface to controller synthesis system m2mc, which is being developed in a current KTH/Chalmers research project. TML is evaluated by a qualitative comparison with the modeling languages of two well-known model checking tools: Uppaal and Kronos. Two example systems (Fischer’s mutual exclusion protocol and CSMA/CD) are implemented in all three languages, to discover the relative merits of each language. Although not as feature rich as Uppaal, TML brings some new language features which are found to be potentially useful for modeling timed automata systems. These features are largely adopted from the general graph description language Dot, used by programs in the Graphviz software package. As m2mc is still in early development and liable to change, an intermediate JSON representation for timed automata is defined. A compiler targeting this intermediate representation is implemented using Miking, a new compiler tool under development in a separate KTH project. Further compilation from JSON to Uppaal is implemented as a proof of concept.
Detta arbete behandlar utformning och implementering av ett modelleringsspråk för tidsautomater. Språket TML:s huvudsakliga tänkta tillämpning är att fungera som ett användargränssnitt för kontrollsyntessystemet m2mc, vilket utvecklas i ett pågående forskningsprojekt på KTH och Chalmers. TML utvärderas genom en kvalitativ jämförelse med modelleringsspråken för två välkända model checking-verktyg: Uppaal och Kronos. Två exempelsystem (Fischers protokoll för mutual exclusion och CSMA/CD) implementeras i vardera modelleringsspråk för att undersöka de olika språkens relativa fördelar och nackdelar. Fastän TML inte är lika omfattande i funktionalitet som Uppaal så bidrar språket med en del nya funktioner, vilka baserat på utvärderingen anses kunna vara användbara för modellering av tidsautomatsystem. Dessa funktioner hämtas till stor del från språket Dot, vilket används i mjukvarupaketet Graphviz för att modellera generella grafer. Eftersom m2mc är i tidig utveckling vore direkt integration med TML inte praktiskt användbart. Därför definieras istället ett mellanformat för tidsautomater i JSON. En kompilator för TML som producerar detta mellanformat implementeras med användning av Miking, ett nytt kompilatorverktyg under utveckling i ett separat KTH-projekt. Som ett koncepttest implementeras vidare kompilering från JSON till Uppaal.

Style APA, Harvard, Vancouver, ISO itp.

Więcej źródeł

Książki na temat "Timed automata"

Kaynar, Dilsun K., Nancy Lynch, Roberto Segala i Frits Vaandrager. The Theory of Timed I/O Automata. Cham: Springer International Publishing, 2011. http://dx.doi.org/10.1007/978-3-031-02003-2.

Pełny tekst źródła

Style APA, Harvard, Vancouver, ISO itp.

Kaynar, Dilsun K., Nancy Lynch, Roberto Segala i Frits Vaandrager. The Theory of Timed I/O Automata. Cham: Springer International Publishing, 2006. http://dx.doi.org/10.1007/978-3-031-01794-0.

Pełny tekst źródła

Style APA, Harvard, Vancouver, ISO itp.

The theory of timed I/O automata. Wyd. 2. San Rafael, Calif. (1537 Fourth Street, San Rafael, CA 94901 USA): Morgan & Claypool, 2011.

Znajdź pełny tekst źródła

Style APA, Harvard, Vancouver, ISO itp.

Penczek, Wojciech, i Agata Pólrola. Advances in Verification of Time Petri Nets and Timed Automata. Berlin, Heidelberg: Springer Berlin Heidelberg, 2006. http://dx.doi.org/10.1007/978-3-540-32870-4.

Pełny tekst źródła

Style APA, Harvard, Vancouver, ISO itp.

Jansen, Nils, Mariëlle Stoelinga i Petra van den Bos, red. A Journey from Process Algebra via Timed Automata to Model Learning. Cham: Springer Nature Switzerland, 2022. http://dx.doi.org/10.1007/978-3-031-15629-8.

Pełny tekst źródła

Style APA, Harvard, Vancouver, ISO itp.

Rodolfo, Gomez, red. Concurrency theory: Calculi and automata for modelling untimed and timed concurrent systems. London: Springer, 2006.

Znajdź pełny tekst źródła

Style APA, Harvard, Vancouver, ISO itp.

1957-, Larsen K. G., i Niebert Peter, red. Formal modeling and analysis of timed systems: First international workshop, FORMATS 2003, Marseille, France, September 6-7, 2003 : revised papers. Berlin: Springer, 2004.

Znajdź pełny tekst źródła

Style APA, Harvard, Vancouver, ISO itp.

FORMATS, 2010 (2010 Klosterneuburg Austria). Formal modeling and analysis of timed systems: 8th international conference, FORMATS 2010, Klosterneuburg, Austria, September 8-10, 2010 : proceedings. Berlin: Springer, 2010.

Znajdź pełny tekst źródła

Style APA, Harvard, Vancouver, ISO itp.

Y, Lakhnech, Yovine Sergio, LINK (Online service) i FTRTFT 2004 (2004 : Grenoble, France), red. Formal techniques, modelling and analysis of timed and fault-tolerant systems: Joint international conferences on formal modeling and analysis of timed systems, FORMATS 2004, and formal techniques in real-time and fault -tolerant systems, FTRTFT 2004, Grenoble, France, September 22-24, 2004 : proceedings. Berlin: Springer, 2004.

Znajdź pełny tekst źródła

Style APA, Harvard, Vancouver, ISO itp.

FORMATS 2004 (2004 Grenoble, France). Formal techniques, modelling and analysis of timed and fault-tolerant systems: Joint international conferences on Formal Modelling and Analysis of Timed Systems, FORMATS 2004 and Formal Techniques in Real-Time and Fault-Tolerant Systems, FTRTFT 2004, Grenoble, France, September 22-24, 2004 : proceedings. Berlin: Springer, 2004.

Znajdź pełny tekst źródła

Style APA, Harvard, Vancouver, ISO itp.

Więcej źródeł

Części książek na temat "Timed automata"

Bouyer, Patricia. "Timed automata". W Handbook of Automata Theory, 1261–94. Zuerich, Switzerland: European Mathematical Society Publishing House, 2021. http://dx.doi.org/10.4171/automata-1/34.

Pełny tekst źródła

Style APA, Harvard, Vancouver, ISO itp.

Alur, Rajeev. "Timed Automata". W Verification of Digital and Hybrid Systems, 233–64. Berlin, Heidelberg: Springer Berlin Heidelberg, 2000. http://dx.doi.org/10.1007/978-3-642-59615-5_12.

Pełny tekst źródła

Style APA, Harvard, Vancouver, ISO itp.

Kaynar, Dilsun K., Nancy Lynch, Roberto Segala i Frits Vaandrager. "Timed Automata". W The Theory of Timed I/O Automata, 19–51. Cham: Springer International Publishing, 2006. http://dx.doi.org/10.1007/978-3-031-01794-0_4.

Pełny tekst źródła

Style APA, Harvard, Vancouver, ISO itp.

Bérard, Béatrice, Michel Bidoit, Alain Finkel, François Laroussinie, Antoine Petit, Laure Petrucci, Philippe Schnoebelen i Pierre Mckenzie. "Timed Automata". W Systems and Software Verification, 59–72. Berlin, Heidelberg: Springer Berlin Heidelberg, 2001. http://dx.doi.org/10.1007/978-3-662-04558-9_5.

Pełny tekst źródła

Style APA, Harvard, Vancouver, ISO itp.

Alur, Rajeev. "Timed Automata". W Computer Aided Verification, 8–22. Berlin, Heidelberg: Springer Berlin Heidelberg, 1999. http://dx.doi.org/10.1007/3-540-48683-6_3.

Pełny tekst źródła

Style APA, Harvard, Vancouver, ISO itp.

Kaynar, Dilsun K., Nancy Lynch, Roberto Segala i Frits Vaandrager. "Timed Automata". W The Theory of Timed I/O Automata, 23–55. Cham: Springer International Publishing, 2011. http://dx.doi.org/10.1007/978-3-031-02003-2_4.

Pełny tekst źródła

Style APA, Harvard, Vancouver, ISO itp.

Sankur, Ocan. "Timed Automata Verification and Synthesis via Finite Automata Learning". W Tools and Algorithms for the Construction and Analysis of Systems, 329–49. Cham: Springer Nature Switzerland, 2023. http://dx.doi.org/10.1007/978-3-031-30820-8_21.

Pełny tekst źródła

Streszczenie:

AbstractWe present algorithms for model checking and controller synthesis of timed automata, seeing a timed automaton model as a parallel composition of a large finite-state machine and a relatively smaller timed automaton, and using compositional reasoning on this composition. We use automata learning algorithms to learn finite automata approximations of the timed automaton component, in order to reduce the problem at hand to finite-state model checking or to finite-state controller synthesis. We present an experimental evaluation of our approach.

Style APA, Harvard, Vancouver, ISO itp.

Bérard, Beatrice, i Serge Haddad. "Interrupt Timed Automata". W Foundations of Software Science and Computational Structures, 197–211. Berlin, Heidelberg: Springer Berlin Heidelberg, 2009. http://dx.doi.org/10.1007/978-3-642-00596-1_15.

Pełny tekst źródła

Style APA, Harvard, Vancouver, ISO itp.

Li, Guoqiang, Xiaojuan Cai, Mizuhito Ogawa i Shoji Yuen. "Nested Timed Automata". W Lecture Notes in Computer Science, 168–82. Berlin, Heidelberg: Springer Berlin Heidelberg, 2013. http://dx.doi.org/10.1007/978-3-642-40229-6_12.

Pełny tekst źródła

Style APA, Harvard, Vancouver, ISO itp.

Trivedi, Ashutosh, i Dominik Wojtczak. "Recursive Timed Automata". W Automated Technology for Verification and Analysis, 306–24. Berlin, Heidelberg: Springer Berlin Heidelberg, 2010. http://dx.doi.org/10.1007/978-3-642-15643-4_23.

Pełny tekst źródła

Style APA, Harvard, Vancouver, ISO itp.

Streszczenia konferencji na temat "Timed automata"

Pastore, Fabrizio, Daniela Micucci i Leonardo Mariani. "Timed k-Tail: Automatic Inference of Timed Automata". W 2017 IEEE International Conference on Software Testing, Verification and Validation (ICST). IEEE, 2017. http://dx.doi.org/10.1109/icst.2017.43.

Pełny tekst źródła

Style APA, Harvard, Vancouver, ISO itp.

Jenkin, Mark, Joël Ouaknine, Alexander Rabinovich i James Worrell. "Alternating Timed Automata over Bounded Time". W 2010 25th Annual IEEE Symposium on Logic in Computer Science (LICS 2010). IEEE, 2010. http://dx.doi.org/10.1109/lics.2010.45.

Pełny tekst źródła

Style APA, Harvard, Vancouver, ISO itp.

Cao, Yizhen, Zhiying Duan i Yongbin Wang. "Uninterrupted Automatic Broadcasting Based on Timed Automata". W 2015 3rd International Conference on Applied Computing and Information Technology/2nd International Conference on Computational Science and Intelligence (ACIT-CSI). IEEE, 2015. http://dx.doi.org/10.1109/acit-csi.2015.93.

Pełny tekst źródła

Style APA, Harvard, Vancouver, ISO itp.

Abdulla, Parosh Aziz, Mohamed Faouzi Atig i Jari Stenman. "Dense-Timed Pushdown Automata". W 2012 27th Annual IEEE Symposium on Logic in Computer Science (LICS 2012). IEEE, 2012. http://dx.doi.org/10.1109/lics.2012.15.

Pełny tekst źródła

Style APA, Harvard, Vancouver, ISO itp.

Clemente, Lorenzo, i Slawomir Lasota. "Timed Pushdown Automata Revisited". W 2015 30th Annual ACM/IEEE Symposium on Logic in Computer Science (LICS). IEEE, 2015. http://dx.doi.org/10.1109/lics.2015.73.

Pełny tekst źródła

Style APA, Harvard, Vancouver, ISO itp.

David, Alexandre, Kim G. Larsen, Axel Legay, Ulrik Nyman i Andrzej Wasowski. "Timed I/O automata". W the 13th ACM international conference. New York, New York, USA: ACM Press, 2010. http://dx.doi.org/10.1145/1755952.1755967.

Pełny tekst źródła

Style APA, Harvard, Vancouver, ISO itp.

Lampka, Kai, Simon Perathoner i Lothar Thiele. "Analytic real-time analysis and timed automata". W the seventh ACM international conference. New York, New York, USA: ACM Press, 2009. http://dx.doi.org/10.1145/1629335.1629351.

Pełny tekst źródła

Style APA, Harvard, Vancouver, ISO itp.

Berard, Beatrice, Serge Haddad i Mathieu Sassolas. "Real Time Properties for Interrupt Timed Automata". W 2010 17th International Symposium on Temporal Representation and Reasoning (TIME 2010). IEEE, 2010. http://dx.doi.org/10.1109/time.2010.11.

Pełny tekst źródła

Style APA, Harvard, Vancouver, ISO itp.

Chen, Taolue, Tingting Han i Joost-Pieter Katoen. "Time-Abstracting Bisimulation for Probabilistic Timed Automata". W 2008 2nd IEEE/IFIP International Symposium on Theoretical Aspects of Software Engineering (TASE). IEEE, 2008. http://dx.doi.org/10.1109/tase.2008.29.

Pełny tekst źródła

Style APA, Harvard, Vancouver, ISO itp.

Priesterjahn, Claudia, Christian Heinzemann i Wilhelm Schafer. "From timed automata to timed failure propagation graphs". W 2013 IEEE 16th International Symposium on Object/Component/Service-Oriented Real-Time Distributed Computing (ISORC). IEEE, 2013. http://dx.doi.org/10.1109/isorc.2013.6913236.

Pełny tekst źródła

Style APA, Harvard, Vancouver, ISO itp.

Raporty organizacyjne na temat "Timed automata"

Archer, Myla, i Constance Heitmeyer. Mechanical Verification of Timed Automata: A Case Study. Fort Belvoir, VA: Defense Technical Information Center, grudzień 1998. http://dx.doi.org/10.21236/ada359891.

Pełny tekst źródła

Style APA, Harvard, Vancouver, ISO itp.

Seshia, Sanjit A., i Randal E. Bryant. A Boolean Approach to Unbounded, Fully Symbolic Model Checking of Timed Automata. Fort Belvoir, VA: Defense Technical Information Center, marzec 2003. http://dx.doi.org/10.21236/ada460035.

Pełny tekst źródła

Style APA, Harvard, Vancouver, ISO itp.

Ouaknine, Joel, i James Worrell. On the Language Inclusion Problem for Timed Automata: Closing a Decidability Gap. Fort Belvoir, VA: Defense Technical Information Center, listopad 2003. http://dx.doi.org/10.21236/ada461167.

Pełny tekst źródła

Style APA, Harvard, Vancouver, ISO itp.

Archer, Myla. Tools for Simplifying Proofs of Properties of Timed Automata: The TAME Template, Theories, and Strategies. Fort Belvoir, VA: Defense Technical Information Center, marzec 1999. http://dx.doi.org/10.21236/ada361638.

Pełny tekst źródła

Style APA, Harvard, Vancouver, ISO itp.

Cleveland, Gary A., Richard L. Piazza i Richard H. Brown. Real Time Automatic Programming. Fort Belvoir, VA: Defense Technical Information Center, luty 1990. http://dx.doi.org/10.21236/ada220162.

Pełny tekst źródła

Style APA, Harvard, Vancouver, ISO itp.

Videa, Aldo, i Yiyi Wang. Inference of Transit Passenger Counts and Waiting Time Using Wi-Fi Signals. Western Transportation Institute, sierpień 2021. http://dx.doi.org/10.15788/1715288737.

Pełny tekst źródła

Streszczenie:

Passenger data such as real-time origin-destination (OD) flows and waiting times are central to planning public transportation services and improving visitor experience. This project explored the use of Internet of Things (IoT) Technology to infer transit ridership and waiting time at bus stops. Specifically, this study explored the use of Raspberry Pi computers, which are small and inexpensive sets of hardware, to scan the Wi-Fi networks of passengers’ smartphones. The process was used to infer passenger counts and obtain information on passenger trajectories based on Global Positioning System (GPS) data. The research was conducted as a case study of the Streamline Bus System in Bozeman, Montana. To evaluate the reliability of the data collected with the Raspberry Pi computers, the study conducted technology-based estimation of ridership, OD flows, wait time, and travel time for a comparison with ground truth data (passenger surveys, manual data counts, and bus travel times). This study introduced the use of a wireless Wi-Fi scanning device for transit data collection, called a Smart Station. It combines an innovative set of hardware and software to create a non-intrusive and passive data collection mechanism. Through the field testing and comparison evaluation with ground truth data, the Smart Station produced accurate estimates of ridership, origin-destination characteristics, wait times, and travel times. Ridership data has traditionally been collected through a combination of manual surveys and Automatic Passenger Counter (APC) systems, which can be time-consuming and expensive, with limited capabilities to produce real-time data. The Smart Station shows promise as an accurate and cost-effective alternative. The advantages of using Smart Station over traditional data collection methods include the following: (1) Wireless, automated data collection and retrieval, (2) Real-time observation of passenger behavior, (3) Negligible maintenance after programming and installing the hardware, (4) Low costs of hardware, software, and installation, and (5) Simple and short programming and installation time. If further validated through additional research and development, the device could help transit systems facilitate data collection for route optimization, trip planning tools, and traveler information systems.

Style APA, Harvard, Vancouver, ISO itp.

Jackson, Richard Henry Frymuth, i Albert Jones. Real-time optimization in automated manufacturing facilities. Gaithersburg, MD: National Bureau of Standards, 1986. http://dx.doi.org/10.6028/nbs.sp.724.

Pełny tekst źródła

Style APA, Harvard, Vancouver, ISO itp.

Kuruganti, Teja, Olufemi Omitaomu, Ozgur Ozmen, Laura Pullum, Hilda Klasky, Mark Martin, Mohammed Olama i in. Real-Time Automated Health Information Technology Hazard Detection. Office of Scientific and Technical Information (OSTI), wrzesień 2019. http://dx.doi.org/10.2172/1615805.

Pełny tekst źródła

Style APA, Harvard, Vancouver, ISO itp.

Chang, Fangzhe, i Vijay Karamcheti. Automatic Configuration and Run-time Adaptation of Distributed Applications. Fort Belvoir, VA: Defense Technical Information Center, styczeń 1999. http://dx.doi.org/10.21236/ada439727.

Pełny tekst źródła

Style APA, Harvard, Vancouver, ISO itp.

Bonakdarpour, Borzoo, i Sandeep S. Kulkarni. Automatic Addition of Fault-Tolerance to Real-Time Programs. Fort Belvoir, VA: Defense Technical Information Center, styczeń 2006. http://dx.doi.org/10.21236/ada455712.

Pełny tekst źródła

Style APA, Harvard, Vancouver, ISO itp.

Oferujemy zniżki na wszystkie plany premium dla autorów, których prace zostały uwzględnione w tematycznych zestawieniach literatury. Skontaktuj się z nami, aby uzyskać unikalny kod promocyjny!