Artykuły w czasopismach na temat „Systems on chip (SoCs)”
Utwórz poprawne odniesienie w stylach APA, MLA, Chicago, Harvard i wielu innych
Sprawdź 50 najlepszych artykułów w czasopismach naukowych na temat „Systems on chip (SoCs)”.
Przycisk „Dodaj do bibliografii” jest dostępny obok każdej pracy w bibliografii. Użyj go – a my automatycznie utworzymy odniesienie bibliograficzne do wybranej pracy w stylu cytowania, którego potrzebujesz: APA, MLA, Harvard, Chicago, Vancouver itp.
Możesz również pobrać pełny tekst publikacji naukowej w formacie „.pdf” i przeczytać adnotację do pracy online, jeśli odpowiednie parametry są dostępne w metadanych.
Przeglądaj artykuły w czasopismach z różnych dziedzin i twórz odpowiednie bibliografie.
Piguet, Christian. "Power consumption reduction in systems on Chip (SoCs)". Annales Des Télécommunications 59, nr 7-8 (lipiec 2004): 884–902. http://dx.doi.org/10.1007/bf03180026.
Pełny tekst źródłaHansson, Andreas, Kees Goossens i Andrei Rădulescu. "Avoiding Message-Dependent Deadlock in Network-Based Systems on Chip". VLSI Design 2007 (30.04.2007): 1–10. http://dx.doi.org/10.1155/2007/95859.
Pełny tekst źródłaBoutekkouk, Fateh, Mohammed Benmohammed, Sebastien Bilavarn i Michel Auguin. "UML2.0 Profiles for Embedded Systems and Systems On a Chip (SOCs)." Journal of Object Technology 8, nr 1 (2009): 135. http://dx.doi.org/10.5381/jot.2009.8.1.a1.
Pełny tekst źródłaMaity, Srijeeta, Anirban Ghose, Soumyajit Dey i Swarnendu Biswas. "Thermal-aware Adaptive Platform Management for Heterogeneous Embedded Systems". ACM Transactions on Embedded Computing Systems 20, nr 5s (31.10.2021): 1–28. http://dx.doi.org/10.1145/3477028.
Pełny tekst źródłaBogdan, Paul, Tudor Dumitraş i Radu Marculescu. "Stochastic Communication: A New Paradigm for Fault-Tolerant Networks-on-Chip". VLSI Design 2007 (22.04.2007): 1–17. http://dx.doi.org/10.1155/2007/95348.
Pełny tekst źródłaSi, Qilin, Santosh Shetty i Benjamin Carrion Schaefer. "Building Complete Heterogeneous Systems-on-Chip in C: From Hardware Accelerators to CPUs". Electronics 10, nr 14 (20.07.2021): 1746. http://dx.doi.org/10.3390/electronics10141746.
Pełny tekst źródłaTouati, Djallel Eddine, Aziz Oukaira, Ahmad Hassan, Mohamed Ali, Ahmed Lakhssassi i Yvon Savaria. "Accurate On-Chip Thermal Peak Detection Based on Heuristic Algorithms and Embedded Temperature Sensors". Electronics 12, nr 13 (6.07.2023): 2978. http://dx.doi.org/10.3390/electronics12132978.
Pełny tekst źródłaTong, Huyan. "An Overview on On-chip Network Routing Optimisation". Applied and Computational Engineering 8, nr 1 (1.08.2023): 191–95. http://dx.doi.org/10.54254/2755-2721/8/20230123.
Pełny tekst źródłaLu, Jian, Hongwei Jia, Andres Arias, Xun Gong i Z. John Shen. "On-Chip Bondwire Magnetics with Ferrite-Epoxy Glob Coating for Power Systems on Chip". International Journal of Power Management Electronics 2008 (16.07.2008): 1–9. http://dx.doi.org/10.1155/2008/678415.
Pełny tekst źródłaNandi, Purab, K. R. Anupama, Himanish Agarwal, Arav Jain i Siddharth Paliwal. "Use of the k-nearest neighbour and its analysis for fall detection on Systems on a Chip for multiple datasets". Acta IMEKO 12, nr 3 (18.09.2023): 1–11. http://dx.doi.org/10.21014/actaimeko.v12i3.1489.
Pełny tekst źródłaGonzalez-Martinez, Guillermo, Remberto Sandoval-Arechiga, Luis Octavio Solis-Sanchez, Laura Garcia-Luciano, Salvador Ibarra-Delgado, Juan Ramon Solis-Escobedo, Jose Ricardo Gomez-Rodriguez i Viktor Ivan Rodriguez-Abdala. "A Survey of MPSoC Management toward Self-Awareness". Micromachines 15, nr 5 (26.04.2024): 577. http://dx.doi.org/10.3390/mi15050577.
Pełny tekst źródłaWegner, Tim, Martin Gag i Dirk Timmermann. "Performance Analysis of Temperature Management Approaches in Networks-on-Chip". International Journal of Embedded and Real-Time Communication Systems 3, nr 4 (październik 2012): 19–41. http://dx.doi.org/10.4018/jertcs.2012100102.
Pełny tekst źródłaR, Anala M., Amit N. Subrahmanya i Allbright D’Souza. "Performance Analysis of Mesh-based NoC’s on Routing Algorithms". International Journal of Electrical and Computer Engineering (IJECE) 8, nr 5 (1.10.2018): 3368. http://dx.doi.org/10.11591/ijece.v8i5.pp3368-3373.
Pełny tekst źródłaGomez-Rodriguez, Jose Ricardo, Remberto Sandoval-Arechiga, Salvador Ibarra-Delgado, Viktor Ivan Rodriguez-Abdala, Jose Luis Vazquez-Avila i Ramon Parra-Michel. "A Survey of Software-Defined Networks-on-Chip: Motivations, Challenges and Opportunities". Micromachines 12, nr 2 (12.02.2021): 183. http://dx.doi.org/10.3390/mi12020183.
Pełny tekst źródłaZhang, Wei, Zihao Jiang, Zhiguang Chen, Nong Xiao i Yang Ou. "NUMA-Aware DGEMM Based on 64-Bit ARMv8 Multicore Processors Architecture". Electronics 10, nr 16 (17.08.2021): 1984. http://dx.doi.org/10.3390/electronics10161984.
Pełny tekst źródłaAmoretti, Michele. "Modeling and Simulation of Network-on-Chip Systems with DEVS and DEUS". Scientific World Journal 2014 (2014): 1–9. http://dx.doi.org/10.1155/2014/982569.
Pełny tekst źródłaELRABAA, MUHAMMAD E. S., i ABDELHAFID BOUHRAOUA. "BUFFER ENGINEERING FOR MODIFIED FAT TREE NoCs FOR MANY-CORE SYSTEMS-ON-CHIP". Journal of Circuits, Systems and Computers 23, nr 07 (2.06.2014): 1450105. http://dx.doi.org/10.1142/s0218126614501059.
Pełny tekst źródłaZhou, Xinbing, Peng Hao i Dake Liu. "PCCNoC: Packet Connected Circuit as Network on Chip for High Throughput and Low Latency SoCs". Micromachines 14, nr 3 (21.02.2023): 501. http://dx.doi.org/10.3390/mi14030501.
Pełny tekst źródłaNesrine, Toubaline, Bennouar Djamel i Mahdoum Ali. "A Classification and Evaluation Framework for NoC Mapping Strategies". Journal of Circuits, Systems and Computers 26, nr 02 (3.11.2016): 1730001. http://dx.doi.org/10.1142/s021812661730001x.
Pełny tekst źródłaSHI, ZAIFENG, TAO LUO, YUANQING LI, YAN XU i SUYING YAO. "AN ON-CHIP BUS MODELING AND PARAMETER SIMULATION METHOD BASED ON UTILIZATION ANALYSIS". Journal of Circuits, Systems and Computers 22, nr 10 (grudzień 2013): 1340031. http://dx.doi.org/10.1142/s0218126613400318.
Pełny tekst źródłaMelo, Douglas R., Cesar A. Zeferino, Luigi Dilillo i Eduardo A. Bezerra. "Maximizing the Inner Resilience of a Network-on-Chip through Router Controllers Design". Sensors 19, nr 24 (9.12.2019): 5416. http://dx.doi.org/10.3390/s19245416.
Pełny tekst źródłaClair, Judicael, Guy Eichler i Luca P. Carloni. "SpikeHard: Efficiency-Driven Neuromorphic Hardware for Heterogeneous Systems-on-Chip". ACM Transactions on Embedded Computing Systems 22, nr 5s (9.09.2023): 1–22. http://dx.doi.org/10.1145/3609101.
Pełny tekst źródłaParmar, Harikrishna, i Usha Mehta. "ILP Based Power-Aware Test Time Reduction Using On-Chip Clocking in NoC Based SoC". Journal of Low Power Electronics and Applications 9, nr 2 (17.06.2019): 19. http://dx.doi.org/10.3390/jlpea9020019.
Pełny tekst źródłaBhat, Ganapati, Sumit K. Mandal, Sai T. Manchukonda, Sai V. Vadlamudi, Ayushi Agarwal, Jun Wang i Umit Y. Ogras. "Per-Core Power Modeling for Heterogenous SoCs". Electronics 10, nr 19 (7.10.2021): 2428. http://dx.doi.org/10.3390/electronics10192428.
Pełny tekst źródłaA., Rahul, i Shripriyadarshini J. "Environmental Impact Assessment of Chiplet-Based VLSI". International Research Journal of Computer Science 11, nr 04 (5.04.2024): 364–70. http://dx.doi.org/10.26562/irjcs.2024.v1104.44.
Pełny tekst źródłaRuaro, Marcelo, Anderson Sant’ana, Axel Jantsch i Fernando Gehm Moraes. "Modular and Distributed Management of Many-Core SoCs". ACM Transactions on Computer Systems 38, nr 1-2 (lipiec 2021): 1–16. http://dx.doi.org/10.1145/3458511.
Pełny tekst źródłaKordzadeh, Atefeh, Dominik Holzmann, Alfred Binder, Thomas Moldaschl, Johannes Sturm i Ali Roshanghias. "Miniaturized On-Chip NFC Antenna versus Screen-Printed Antenna for the Flexible Disposable Sensor Strips". IoT 1, nr 2 (28.10.2020): 309–19. http://dx.doi.org/10.3390/iot1020018.
Pełny tekst źródłaZhang, Zhun, Xiang Wang, Qiang Hao, Dongdong Xu, Jinlei Zhang, Jiakang Liu i Jinhui Ma. "High-Efficiency Parallel Cryptographic Accelerator for Real-Time Guaranteeing Dynamic Data Security in Embedded Systems". Micromachines 12, nr 5 (15.05.2021): 560. http://dx.doi.org/10.3390/mi12050560.
Pełny tekst źródłaMalik, Arsalan Ali, Anees Ullah, Ali Zahir, Affaq Qamar, Shadan Khan Khattak i Pedro Reviriego. "Isolation Design Flow Effectiveness Evaluation Methodology for Zynq SoCs". Electronics 9, nr 5 (15.05.2020): 814. http://dx.doi.org/10.3390/electronics9050814.
Pełny tekst źródłaAyachi, Riadh, Ayoub Mhaouch i Abdessalem Ben Abdelali. "Lightweight Cryptography for Network-on-Chip Data Encryption". Security and Communication Networks 2021 (19.05.2021): 1–10. http://dx.doi.org/10.1155/2021/9943713.
Pełny tekst źródłaBHAGAVAT, MILIND. "Packaging Renaissance with Chiplets". International Symposium on Microelectronics 2019, S1 (1.10.2019): S1—S17. http://dx.doi.org/10.4071/2380-4505-2019.1.keynote000001.
Pełny tekst źródłaCirstea, Marcian, Khaled Benkrid, Andrei Dinu, Romeo Ghiriti i Dorin Petreus. "Digital Electronic System-on-Chip Design: Methodologies, Tools, Evolution, and Trends". Micromachines 15, nr 2 (7.02.2024): 247. http://dx.doi.org/10.3390/mi15020247.
Pełny tekst źródłaShahane, Priti, i Rakhi Kurup. "Design of fault tolerant algorithm for network on chip router using field programmable gate array". International Journal of Reconfigurable and Embedded Systems (IJRES) 13, nr 1 (1.03.2024): 1. http://dx.doi.org/10.11591/ijres.v13.i1.pp1-8.
Pełny tekst źródłaDondo Gazzano, Julio, Fernando Rincon, Carlos Vaderrama, Felix Villanueva, Julian Caba i Juan Carlos Lopez. "Facilitating Preemptive Hardware System Design Using Partial Reconfiguration Techniques". Scientific World Journal 2014 (2014): 1–15. http://dx.doi.org/10.1155/2014/164059.
Pełny tekst źródłaNeuenhahn, M. C., H. Blume i T. G. Noll. "Quantitative design space exploration of routing-switches for Network-on-Chip". Advances in Radio Science 6 (26.05.2008): 145–50. http://dx.doi.org/10.5194/ars-6-145-2008.
Pełny tekst źródłaRamos, Alberto, Honorio Martín, Carmen Cámara i Pedro Peris-Lopez. "Stimulated Microcontroller Dataset for New IoT Device Identification Schemes through On-Chip Sensor Monitoring". Data 9, nr 5 (28.04.2024): 62. http://dx.doi.org/10.3390/data9050062.
Pełny tekst źródłaPitre, Boisy, i Martin Margala. "A Novel Approach to Managing System-on-Chip Sub-Blocks Using a 16-Bit Real-Time Operating System". Electronics 13, nr 10 (18.05.2024): 1978. http://dx.doi.org/10.3390/electronics13101978.
Pełny tekst źródłaCesini, Daniele, Elena Corni, Antonio Falabella, Andrea Ferraro, Lucia Morganti, Enrico Calore, Sebastiano Fabio Schifano i in. "Power-Efficient Computing: Experiences from the COSA Project". Scientific Programming 2017 (2017): 1–14. http://dx.doi.org/10.1155/2017/7206595.
Pełny tekst źródłaPrasad Acharya, Gobinda, Muddapu Asha Rani, Ganjikunta Ganesh Kumar i Lavanya Poluboyina. "Adaptation of of March-SS algorithm to word-oriented memory built-in self-test and repair". Indonesian Journal of Electrical Engineering and Computer Science 26, nr 1 (1.04.2022): 96. http://dx.doi.org/10.11591/ijeecs.v26.i1.pp96-104.
Pełny tekst źródłaLi, Peng, Wei Xi, Xianggen Yin, Hao Yao i Huafeng Chen. "Design of a CMOS Lineal Hall Sensor Front-End Working in Current Mode with Programmable Gain Stage for Power Specific Chip". Journal of Sensors 2021 (1.02.2021): 1–5. http://dx.doi.org/10.1155/2021/6618206.
Pełny tekst źródłaOhmura, Itta, Gentaro Morimoto, Yousuke Ohno, Aki Hasegawa i Makoto Taiji. "MDGRAPE-4: a special-purpose computer system for molecular dynamics simulations". Philosophical Transactions of the Royal Society A: Mathematical, Physical and Engineering Sciences 372, nr 2021 (6.08.2014): 20130387. http://dx.doi.org/10.1098/rsta.2013.0387.
Pełny tekst źródłaAlraho, Senan, Qummar Zaman, Hamam Abd i Andreas König. "Integrated Sensor Electronic Front-Ends with Self-X Capabilities". Chips 1, nr 2 (12.08.2022): 83–120. http://dx.doi.org/10.3390/chips1020008.
Pełny tekst źródłaBernardi, Paolo, Augusto Maria Guerriero, Giorgio Insinga, Giovanni Paganini, Giambattista Carnevale, Matteo Coppetta, Walter Mischo i Rudolf Ullmann. "Built-In Self-Test Architecture Enabling Diagnosis for Massive Embedded Memory Banks in Large SoCs". Electronics 13, nr 2 (10.01.2024): 303. http://dx.doi.org/10.3390/electronics13020303.
Pełny tekst źródłaKrishna, Banoth, Sandeep Singh Gill i Amod Kumar. "Design of Low-Power High-Speed 8 Bit CMOS Current Steering DAC for AI Applications". International Journal of Software Science and Computational Intelligence 14, nr 1 (1.01.2022): 1–18. http://dx.doi.org/10.4018/ijssci.304801.
Pełny tekst źródłaKumar, N. Ashok, G. Shyni, Geno Peter, Albert Alexander Stonier i Vivekananda Ganji. "Architecture of Network-on-Chip (NoC) for Secure Data Routing Using 4-H Function of Improved TACIT Security Algorithm". Wireless Communications and Mobile Computing 2022 (9.03.2022): 1–9. http://dx.doi.org/10.1155/2022/4737569.
Pełny tekst źródłaSharma, Dimple, i Lev Kirischian. "A Decision-Making Method Providing Sustainability to FPGA-Based SoCs by Run-Time Structural Adaptation to Mode of Operation, Power Budget, and Die Temperature Variations". International Journal of Reconfigurable Computing 2021 (1.09.2021): 1–29. http://dx.doi.org/10.1155/2021/5512938.
Pełny tekst źródłaGalatenko, V. A., i K. A. Kostyukhin. "Hardware Debugging: an Overview of Modern Approaches". Programmnaya Ingeneria 13, nr 9 (7.11.2022): 415–24. http://dx.doi.org/10.17587/prin.13.415-424.
Pełny tekst źródłaIyer (Subu), Subramanian S. "Packaging without the Package - A More Holistic Moore's Law". International Symposium on Microelectronics 2017, S1 (1.10.2017): 1–40. http://dx.doi.org/10.4071/isom-2017-slide-2.
Pełny tekst źródłaNawaz, Gareeb, i Chhagan Charan. "The Design of An LDO Regulator". ITM Web of Conferences 54 (2023): 02010. http://dx.doi.org/10.1051/itmconf/20235402010.
Pełny tekst źródłaAhmed, Mohammed Altaf, i Suleman Alnatheer. "Deep Q-Learning with Bit-Swapping-Based Linear Feedback Shift Register fostered Built-In Self-Test and Built-In Self-Repair for SRAM". Micromachines 13, nr 6 (19.06.2022): 971. http://dx.doi.org/10.3390/mi13060971.
Pełny tekst źródła