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Artykuły w czasopismach na temat "Systems on chip (SoCs)"
Piguet, Christian. "Power consumption reduction in systems on Chip (SoCs)". Annales Des Télécommunications 59, nr 7-8 (lipiec 2004): 884–902. http://dx.doi.org/10.1007/bf03180026.
Pełny tekst źródłaHansson, Andreas, Kees Goossens i Andrei Rădulescu. "Avoiding Message-Dependent Deadlock in Network-Based Systems on Chip". VLSI Design 2007 (30.04.2007): 1–10. http://dx.doi.org/10.1155/2007/95859.
Pełny tekst źródłaBoutekkouk, Fateh, Mohammed Benmohammed, Sebastien Bilavarn i Michel Auguin. "UML2.0 Profiles for Embedded Systems and Systems On a Chip (SOCs)." Journal of Object Technology 8, nr 1 (2009): 135. http://dx.doi.org/10.5381/jot.2009.8.1.a1.
Pełny tekst źródłaMaity, Srijeeta, Anirban Ghose, Soumyajit Dey i Swarnendu Biswas. "Thermal-aware Adaptive Platform Management for Heterogeneous Embedded Systems". ACM Transactions on Embedded Computing Systems 20, nr 5s (31.10.2021): 1–28. http://dx.doi.org/10.1145/3477028.
Pełny tekst źródłaBogdan, Paul, Tudor Dumitraş i Radu Marculescu. "Stochastic Communication: A New Paradigm for Fault-Tolerant Networks-on-Chip". VLSI Design 2007 (22.04.2007): 1–17. http://dx.doi.org/10.1155/2007/95348.
Pełny tekst źródłaSi, Qilin, Santosh Shetty i Benjamin Carrion Schaefer. "Building Complete Heterogeneous Systems-on-Chip in C: From Hardware Accelerators to CPUs". Electronics 10, nr 14 (20.07.2021): 1746. http://dx.doi.org/10.3390/electronics10141746.
Pełny tekst źródłaTouati, Djallel Eddine, Aziz Oukaira, Ahmad Hassan, Mohamed Ali, Ahmed Lakhssassi i Yvon Savaria. "Accurate On-Chip Thermal Peak Detection Based on Heuristic Algorithms and Embedded Temperature Sensors". Electronics 12, nr 13 (6.07.2023): 2978. http://dx.doi.org/10.3390/electronics12132978.
Pełny tekst źródłaTong, Huyan. "An Overview on On-chip Network Routing Optimisation". Applied and Computational Engineering 8, nr 1 (1.08.2023): 191–95. http://dx.doi.org/10.54254/2755-2721/8/20230123.
Pełny tekst źródłaLu, Jian, Hongwei Jia, Andres Arias, Xun Gong i Z. John Shen. "On-Chip Bondwire Magnetics with Ferrite-Epoxy Glob Coating for Power Systems on Chip". International Journal of Power Management Electronics 2008 (16.07.2008): 1–9. http://dx.doi.org/10.1155/2008/678415.
Pełny tekst źródłaNandi, Purab, K. R. Anupama, Himanish Agarwal, Arav Jain i Siddharth Paliwal. "Use of the k-nearest neighbour and its analysis for fall detection on Systems on a Chip for multiple datasets". Acta IMEKO 12, nr 3 (18.09.2023): 1–11. http://dx.doi.org/10.21014/actaimeko.v12i3.1489.
Pełny tekst źródłaRozprawy doktorskie na temat "Systems on chip (SoCs)"
Yoon, Jang-Sup. "Embedded test circuit and methods for radio frequency (RF) systems-on-a-chip (SoCs)". [Gainesville, Fla.] : University of Florida, 2006. http://purl.fcla.edu/fcla/etd/UFE0015657.
Pełny tekst źródłaWeiss, Alexander. "Effiziente externe Beobachtung von CPU-Aktivitäten auf SoCs". Doctoral thesis, Saechsische Landesbibliothek- Staats- und Universitaetsbibliothek Dresden, 2015. http://nbn-resolving.de/urn:nbn:de:bsz:14-qucosa-184227.
Pełny tekst źródłaBolzani, Leticia Maria Veiras. "Explorando uma solução híbrida: hardware+software para a detecção de falhas tempo real em systems-on-chip (SoCs)". Pontifícia Universidade Católica do Rio Grande do Sul, 2005. http://hdl.handle.net/10923/3146.
Pełny tekst źródłaThe always increasing number of computer-based safety-critical applications has intensified the research over fault tolerance techniques. While those systems are working, the probability of both permanent and transient faults happens due to the presence of all sort of interference. The common faults are those which affect data and/or modify the expected program execution flow. Thus, the use of techniques allowing detecting these type of faults presents them from propagating to system output. Basically, these techniques are categorized in two groups: software-based approaches and hardware-based approaches. Considering the above introduced, the goal of this work is to specify and to implement a hybrid approach, which combines software-based techniques and hardware-based ones, capable to detect run time data and algorithm control flow faults. It is settled around the techniques proposed in (REBAUDENGO, 2004) and (GOLOUBEVA, 2003). Nevertheless, the proposed approach implements part of its code-transformation rules via software and hardware. These redundant information is added to the software portion and consistency checks are implemented via hardware. Summary, we propose the development of an I-IP (infrastructure intellectual property) core, such as watchdog, to correctly execute the consistency checks concurrently to the application execution. In this work, three different versions of the I-IP were implemented in VHDL and analyzed by means of fault injection experiments. The first implemented version allows data fault detection and, as any prototype, has its limitations. The second version also detects data faults, but eliminates the problems of the former version. The third I-IP version adds the capability of detecting control flow faults to the previous versions of the I-IP. Finally, after implementing these three versions, a fourth version was specified. It adds dependability and robustness to the IIP by using Built-in Self-Test (BIST) techniques. The results obtained from evaluating the different I-IP core versions guarantee that the hybrid approach is efficient, because it features high fault coverage and surpasses the main problems present in software-based techniques proposed in the literature, such as, performance degradation and code/data memory overhead. Finally, this work is a partial result of a joint research project carried by the SiSC Group – PUCRS and CAD – Politecnico di Torino, under the scope of the Alfa Project (##AML/B7-311- 97/0666/II-0086-FI, from 2002 to 2005).
Nos últimos anos, o crescente aumento do número de aplicações críticas baseadas em sistemas eletrônicos, intensificou a pesquisa sobre técnicas de tolerância à falhas. Durante o período de funcionamento destes sistemas, a probabilidade de ocorrerem falhas transientes e permanentes devido à presença de interferências dos mais variados tipos é bastante grande. Dentre as falhas mais freqüentes, salientam-se as falhas que corrompem os dados e as falhas que alteram o fluxo de controle do processador que executa a aplicação. Assim, a utilização de técnicas capazes de detectarem estes tipos de falhas evita que as mesmas se propaguem pelo sistema e acabem gerando saídas incorretas. Basicamente, estas técnicas são classificadas em dois grandes grupos: soluções baseadas em software e soluções baseadas em hardware. Neste contexto, o objetivo principal deste trabalho é especificar e implementar uma solução híbrida, parte em software e parte em hardware, capaz de detectar em tempo de execução eventuais falhas em dados e no fluxo de controle do algoritmo. Esta solução baseia-se nas técnicas propostas em (REBAUDENGO, 2004) e (GOLOUBEVA, 2003) e implementa parte de suas regras de transformação de código via software e parte via hardware. Assim, informações redundantes são agregadas ao código da aplicação e testes de consistência são implementados via hardware. Em resumo, este trabalho propõe o desenvolvimento de um núcleo I-IP (infrastructure intellectual property), tal como um watchdog, para executar os testes de consistência concorrentemente à execução da aplicação. Para isto, três versões diferentes do I-IP foram implementadas em linguagem de descrição de hardware (VHDL) e avaliadas através de experimentos de injeção de falhas.A primeira versão implementada provê a detecção de falhas em dados e, como todo protótipo, este também apresenta algumas restrições e limitações. A segunda versão também detecta falhas em dados, entretanto, supera todos os problemas da versão anterior. A terceira versão do I-IP agrega à versão anterior a capacidade de detectar falhas de fluxo de controle. Finalmente, após a implementação das versões anteriores, foi especificada uma quarta versão que agrega confiabilidade e robustez ao I-IP desenvolvido através da utilização de algumas técnicas de tolerância a falhas e da especificação de um auto-teste funcional. Os resultados obtidos a partir da avaliação das versões do I-IP garantem que a metodologia proposta neste trabalho é bastante eficiente, pois apresenta uma alta cobertura de falhas e supera os principais problemas presentes nas soluções baseadas em software propostas na literatura, ou seja, degradação de desempenho e maior consumo de memória. Finalmente, cabe mencionar que esta dissertação é o resultado parcial de atividades que fazem parte do escopo do Projeto Alfa (#AML/B7-311-97/0666/II-0086-FI) mantido entre os Grupos SiSC – PUCRS (Brasil) e CAD – Politecnico di Torino (Itália) no período de 2002-2005.
Reehal, Gursharan Kaur. "Designing Low Power and High Performance Network-on-Chip Communication Architectures for Nanometer SoCs". The Ohio State University, 2012. http://rave.ohiolink.edu/etdc/view?acc_num=osu1340022240.
Pełny tekst źródłaBolzani, Leticia Maria Veiras. "Explorando uma solu??o h?brida : hardware+software para a detec??o de falhas tempo real em systems-on-chip (SoCs)". Pontif?cia Universidade Cat?lica do Rio Grande do Sul, 2005. http://tede2.pucrs.br/tede2/handle/tede/3001.
Pełny tekst źródłaNos ?ltimos anos, o crescente aumento do n?mero de aplica??es cr?ticas baseadas em sistemas eletr?nicos, intensificou a pesquisa sobre t?cnicas de toler?ncia ? falhas. Durante o per?odo de funcionamento destes sistemas, a probabilidade de ocorrerem falhas transientes e permanentes devido ? presen?a de interfer?ncias dos mais variados tipos ? bastante grande. Dentre as falhas mais freq?entes, salientam-se as falhas que corrompem os dados e as falhas que alteram o fluxo de controle do processador que executa a aplica??o. Assim, a utiliza??o de t?cnicas capazes de detectarem estes tipos de falhas evita que as mesmas se propaguem pelo sistema e acabem gerando sa?das incorretas. Basicamente, estas t?cnicas s?o classificadas em dois grandes grupos: solu??es baseadas em software e solu??es baseadas em hardware. Neste contexto, o objetivo principal deste trabalho ? especificar e implementar uma solu??o h?brida, parte em software e parte em hardware, capaz de detectar em tempo de execu??o eventuais falhas em dados e no fluxo de controle do algoritmo. Esta solu??o baseia-se nas t?cnicas propostas em (REBAUDENGO, 2004) e (GOLOUBEVA, 2003) e implementa parte de suas regras de transforma??o de c?digo via software e parte via hardware. Assim, informa??es redundantes s?o agregadas ao c?digo da aplica??o e testes de consist?ncia s?o implementados via hardware. Em resumo, este trabalho prop?e o desenvolvimento de um n?cleo I-IP (infrastructure intellectual property), tal como um watchdog, para executar os testes de consist?ncia concorrentemente ? execu??o da aplica??o. Para isto, tr?s vers?es diferentes do I-IP foram implementadas em linguagem de descri??o de hardware (VHDL) e avaliadas atrav?s de experimentos de inje??o de falhas. A primeira vers?o implementada prov? a detec??o de falhas em dados e, como todo prot?tipo, este tamb?m apresenta algumas restri??es e limita??es. A segunda vers?o tamb?m detecta falhas em dados, entretanto, supera todos os problemas da vers?o anterior. A terceira vers?o do I-IP agrega ? vers?o anterior a capacidade de detectar falhas de fluxo de controle. Finalmente, ap?s a implementa??o das vers?es anteriores, foi especificada uma quarta vers?o que agrega confiabilidade e robustez ao I-IP desenvolvido atrav?s da utiliza??o de algumas t?cnicas de toler?ncia a falhas e da especifica??o de um auto-teste funcional. Os resultados obtidos a partir da avalia??o das vers?es do I-IP garantem que a metodologia proposta neste trabalho ? bastante eficiente, pois apresenta uma alta cobertura de falhas e supera os principais problemas presentes nas solu??es baseadas em software propostas na literatura, ou seja, degrada??o de desempenho e maior consumo de mem?ria. Finalmente, cabe mencionar que esta disserta??o ? o resultado parcial de atividades que fazem parte do escopo do Projeto Alfa (#AML/B7-311-97/0666/II-0086-FI) mantido entre os Grupos SiSC PUCRS (Brasil) e CAD Politecnico di Torino (It?lia) no per?odo de 2002-2005.
Terosiet, Medhi. "Conception d'un oscillateur robuste contrôlé numériquement pour l'horlogerie des SoCs". Phd thesis, Université Pierre et Marie Curie - Paris VI, 2012. http://tel.archives-ouvertes.fr/tel-00836916.
Pełny tekst źródłaAghaee, Ghaleshahi Nima. "Thermal Issues in Testing of Advanced Systems on Chip". Doctoral thesis, Linköpings universitet, Institutionen för datavetenskap, 2015. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-120798.
Pełny tekst źródłaMEDARDONI, Simone. "Driving the Network-on-Chip Revolution to Remove the Interconnect Bottleneck in Nanoscale Multi-Processor Systems-on-Chip". Doctoral thesis, Università degli studi di Ferrara, 2009. http://hdl.handle.net/11392/2389197.
Pełny tekst źródłaTambara, Lucas Antunes. "Caracterização de circuitos programáveis e sistemas em chip sob radiação". reponame:Biblioteca Digital de Teses e Dissertações da UFRGS, 2013. http://hdl.handle.net/10183/86477.
Pełny tekst źródłaThis work consists in a study about the radiation effects in programmable circuits and System-on-Chips (SoCs) based on FPGAs (Field-Programmable Gate Arrays). Single Event Effects (SEEs) and Total Ionizing Dose (TID) are the two main effects caused by the radiation incidence, and both can imply in the occurrence of failures in integrated circuits. SEEs are due to the incidence of neutrons derived from the interaction of the cosmic rays with the terrestrial atmosphere, as well as heavy ions coming from the space and protons provided from the solar wind and the Van Allen belts. Total Ionizing Dose regards the prolonged exposure of an integrated circuit to the ionizing radiation, which deviates the standard electrical characteristics of the device due to radiation-induced electrical charges accumulated in the semiconductors’ interfaces. In this context, this work aims to describe in details the characterization of Microsemi’s mixed-signal SoC-FPGA SmartFusion A2F200-FG484 when exposed to radiation (SEEs and TID), using a Diverse Redundancy approach for error detection. As well, an architecture using a Diversified Triple Modular Redundancy scheme was tested (SEEs) through its implementation in a Xilinx’s Spartan-6 LX45 FPGA, aiming error detection and correction. The results obtained show that several functional blocks from SmartFusion have different radiation tolerance levels and that the use of the Triple Modular Redundancy together with Diversified Redundancy proved to be extremely efficient in terms of SEEs tolerance.
Cota, Erika Fernandes. "Reuse-based test planning for core-based systems-on-chip". reponame:Biblioteca Digital de Teses e Dissertações da UFRGS, 2003. http://hdl.handle.net/10183/4180.
Pełny tekst źródłaElectronic applications are currently developed under the reuse-based paradigm. This design methodology presents several advantages for the reduction of the design complexity, but brings new challenges for the test of the final circuit. The access to embedded cores, the integration of several test methods, and the optimization of the several cost factors are just a few of the several problems that need to be tackled during test planning. Within this context, this thesis proposes two test planning approaches that aim at reducing the test costs of a core-based system by means of hardware reuse and integration of the test planning into the design flow. The first approach considers systems whose cores are connected directly or through a functional bus. The test planning method consists of a comprehensive model that includes the definition of a multi-mode access mechanism inside the chip and a search algorithm for the exploration of the design space. The access mechanism model considers the reuse of functional connections as well as partial test buses, cores transparency, and other bypass modes. The test schedule is defined in conjunction with the access mechanism so that good trade-offs among the costs of pins, area, and test time can be sought. Furthermore, system power constraints are also considered. This expansion of concerns makes it possible an efficient, yet fine-grained search, in the huge design space of a reuse-based environment. Experimental results clearly show the variety of trade-offs that can be explored using the proposed model, and its effectiveness on optimizing the system test plan. Networks-on-chip are likely to become the main communication platform of systemson- chip. Thus, the second approach presented in this work proposes the reuse of the on-chip network for the test of the cores embedded into the systems that use this communication platform. A power-aware test scheduling algorithm aiming at exploiting the network characteristics to minimize the system test time is presented. The reuse strategy is evaluated considering a number of system configurations, such as different positions of the cores in the network, power consumption constraints and number of interfaces with the tester. Experimental results show that the parallelization capability of the network can be exploited to reduce the system test time, whereas area and pin overhead are strongly minimized. In this manuscript, the main problems of the test of core-based systems are firstly identified and the current solutions are discussed. The problems being tackled by this thesis are then listed and the test planning approaches are detailed. Both test planning techniques are validated for the recently released ITC’02 SoC Test Benchmarks, and further compared to other test planning methods of the literature. This comparison confirms the efficiency of the proposed methods.
Książki na temat "Systems on chip (SoCs)"
Modeling embedded systems and SoCs: Concurrency and time in models of computation. San Francisco: Morgan Kaufmann, 2004.
Znajdź pełny tekst źródłaKempf, Torsten, Gerd Ascheid i Rainer Leupers. Multiprocessor Systems on Chip. New York, NY: Springer New York, 2011. http://dx.doi.org/10.1007/978-1-4419-8153-0.
Pełny tekst źródłaAllard, Bruno, red. Power Systems-On-Chip. Hoboken, NJ, USA: John Wiley & Sons, Inc., 2016. http://dx.doi.org/10.1002/9781119377702.
Pełny tekst źródłaVermeulen, Bart, i Kees Goossens. Debugging Systems-on-Chip. Cham: Springer International Publishing, 2014. http://dx.doi.org/10.1007/978-3-319-06242-6.
Pełny tekst źródłaAbderazek, Ben A. Multicore systems on chip. Trivandrum, Kerala, India: Transworld Research Network, 2007.
Znajdź pełny tekst źródłaBen Abdallah, Abderazek. Advanced Multicore Systems-On-Chip. Singapore: Springer Singapore, 2017. http://dx.doi.org/10.1007/978-981-10-6092-2.
Pełny tekst źródłaSilveira, Luis Miguel, Srinivas Devadas i Ricardo Reis, red. VLSI: Systems on a Chip. Boston, MA: Springer US, 2000. http://dx.doi.org/10.1007/978-0-387-35498-9.
Pełny tekst źródłaBou-Sleiman, Sleiman. Built-in-Self-Test and Digital Self-Calibration for RF SoCs. New York, NY: Springer Science+Business Media, LLC, 2012.
Znajdź pełny tekst źródłaKnipfer, Brent J. Multichip packaging and bare chip systems. Norwalk, CT: Business Communications Co., 1994.
Znajdź pełny tekst źródłaLim, Leycheoh. Chip interleaving for CDMA cellular systems. Ottawa: National Library of Canada = Bibliothèque nationale du Canada, 1999.
Znajdź pełny tekst źródłaCzęści książek na temat "Systems on chip (SoCs)"
Ben Abdallah, Abderazek. "Multicore SoCs Design Methods". W Advanced Multicore Systems-On-Chip, 19–37. Singapore: Springer Singapore, 2017. http://dx.doi.org/10.1007/978-981-10-6092-2_2.
Pełny tekst źródłaChakravarthi, Veena S., i Shivananda R. Koteshwar. "Application-specific SOCs". W System on Chip (SOC) Architecture, 49–63. Cham: Springer Nature Switzerland, 2023. http://dx.doi.org/10.1007/978-3-031-36242-2_4.
Pełny tekst źródłaChakravarthi, Veena S., i Shivananda R. Koteshwar. "Storage in SOCs". W System on Chip (SOC) Architecture, 65–73. Cham: Springer Nature Switzerland, 2023. http://dx.doi.org/10.1007/978-3-031-36242-2_5.
Pełny tekst źródłaBen Abdallah, Abderazek. "Power Optimization Techniques for Multicore SoCs". W Advanced Multicore Systems-On-Chip, 225–44. Singapore: Springer Singapore, 2017. http://dx.doi.org/10.1007/978-981-10-6092-2_8.
Pełny tekst źródłaBen Abdallah, Abderazek. "Multicore SoCs Design Methods". W Multicore Systems On-Chip: Practical Software/Hardware Design, 19–35. Paris: Atlantis Press, 2013. http://dx.doi.org/10.2991/978-94-91216-92-3_2.
Pełny tekst źródłaBen Abdallah, Abderazek. "Power Optimization Techniques for Multicore SoCs". W Multicore Systems On-Chip: Practical Software/Hardware Design, 175–93. Paris: Atlantis Press, 2013. http://dx.doi.org/10.2991/978-94-91216-92-3_8.
Pełny tekst źródłaBen Abdallah, Abderazek. "Soft-Core Processor for Low-Power Embedded Multicore SoCs". W Multicore Systems On-Chip: Practical Software/Hardware Design, 195–213. Paris: Atlantis Press, 2013. http://dx.doi.org/10.2991/978-94-91216-92-3_9.
Pełny tekst źródłaChakravarthi, Veena S., i Shivananda R. Koteshwar. "Introduction to Systems". W System on Chip (SOC) Architecture, 1–15. Cham: Springer Nature Switzerland, 2023. http://dx.doi.org/10.1007/978-3-031-36242-2_1.
Pełny tekst źródłaKirchner, Aljoscha. "Stand der Technik". W Entwicklung von Methoden zur abstrakten Modellierung von Automotive Systems-on-Chips, 49–64. Wiesbaden: Springer Fachmedien Wiesbaden, 2022. http://dx.doi.org/10.1007/978-3-658-38437-1_3.
Pełny tekst źródłaNourani, Mehrdad, Amir Attarha i Krishnendu Chakrabarty. "Signal Integrity: Fault Modeling and Testing in High-Speed SoCs". W SOC (System-on-a-Chip) Testing for Plug and Play Test Automation, 175–90. Boston, MA: Springer US, 2002. http://dx.doi.org/10.1007/978-1-4757-6527-4_12.
Pełny tekst źródłaStreszczenia konferencji na temat "Systems on chip (SoCs)"
Abraham, Jacob A. "“Manufacturing test of systems-on-a-chip (SoCs)”". W 2011 IEEE 24th International SOC Conference (SOCC). IEEE, 2011. http://dx.doi.org/10.1109/socc.2011.6085148.
Pełny tekst źródłaNautiyal, Vivek. "W2B: Design methodologies for SoCs". W 2017 30th IEEE International System-on-Chip Conference (SOCC). IEEE, 2017. http://dx.doi.org/10.1109/socc.2017.8226006.
Pełny tekst źródłaForsell, Martti. "Realizing Multioperations for Step Cached MP-SOCs". W 2006 International Symposium on System-on-Chip. IEEE, 2006. http://dx.doi.org/10.1109/issoc.2006.321972.
Pełny tekst źródłaZhong, Wei, Song Chen, Fei Ma, Takeshi Yoshimura i Satoshi Goto. "Floorplanning driven Network-on-Chip synthesis for 3-D SoCs". W 2011 IEEE International Symposium on Circuits and Systems (ISCAS). IEEE, 2011. http://dx.doi.org/10.1109/iscas.2011.5937785.
Pełny tekst źródłaFox, Paul J., A. Theodore Markettos i Simon W. Moore. "Reliably prototyping large SoCs using FPGA clusters". W 2014 9th International Symposium on Reconfigurable and Communication-Centric Systems-on-Chip (ReCoSoC). IEEE, 2014. http://dx.doi.org/10.1109/recosoc.2014.6861350.
Pełny tekst źródłaLiao, Xiongfei, Jun Zhou i Xin Liu. "Exploring AMBA AXI on-Chip interconnection for TSV-based 3D SoCs". W 2011 IEEE International 3D Systems Integration Conference (3DIC). IEEE, 2012. http://dx.doi.org/10.1109/3dic.2012.6263036.
Pełny tekst źródłaMishra, S., V. Sankatali, B. Vermeersch, M. Brunion, M. Lofrano, D. Abdi, H. Oprins i in. "Towards Chip-Package-System Co-optimization of Thermally-limited System-On-Chips (SOCs)". W 2023 IEEE International Reliability Physics Symposium (IRPS). IEEE, 2023. http://dx.doi.org/10.1109/irps48203.2023.10117979.
Pełny tekst źródłaTomoutzoglou, Othon, Dimitrios Bakoyannis, George Kornaros i Marcello Coppola. "Efficient communication in heterogeneous SoCs with unified address space". W 2016 11th International Symposium on Reconfigurable Communication-Centric Systems-on-Chip (ReCoSoC). IEEE, 2016. http://dx.doi.org/10.1109/recosoc.2016.7533904.
Pełny tekst źródłaOrsila, H., T. Kangas i T. D. Hamalainen. "Hybrid Algorithm for Mapping Static Task Graphs on Multiprocessor SoCs". W 2005 International Symposium on System-on-Chip. IEEE, 2005. http://dx.doi.org/10.1109/issoc.2005.1595665.
Pełny tekst źródłaOrsila, Heikki, Tero Kangas, Erno Salminen i Timo Hamalainen. "Parameterizing Simulated Annealing for Distributing Task Graphs on Multiprocessor SoCs". W 2006 International Symposium on System-on-Chip. IEEE, 2006. http://dx.doi.org/10.1109/issoc.2006.321971.
Pełny tekst źródłaRaporty organizacyjne na temat "Systems on chip (SoCs)"
Bambha, Neal K., i Shuvra S. Bhattacharyya. Interconnect Synthesis for Systems on Chip. Fort Belvoir, VA: Defense Technical Information Center, lipiec 2004. http://dx.doi.org/10.21236/ada448078.
Pełny tekst źródłaBambha, Neal K., Shuvra S. Bhattacharyya i Gary Euliss. Design Considerations for Optically Connected Systems on Chip. Fort Belvoir, VA: Defense Technical Information Center, czerwiec 2003. http://dx.doi.org/10.21236/ada457628.
Pełny tekst źródłaAnton Carl Greenwald. MEMS CHIP CO2 SENSOR FOR BUILDING SYSTEMS INTEGRATION. Office of Scientific and Technical Information (OSTI), wrzesień 2005. http://dx.doi.org/10.2172/860161.
Pełny tekst źródłaKirshberg, Jeffrey A. Microelectromechanical Systems (MEMS)-Based Microcapillary Pumped Loop for Chip-Level Temperature Control. Fort Belvoir, VA: Defense Technical Information Center, styczeń 2002. http://dx.doi.org/10.21236/ada405777.
Pełny tekst źródłaPapapolymerou, Ioannis. Instrumentation for the Development of Reconfigurable Microwave/MM-Wave FGC Passive Elements Using MEMS Switches for 'Smart' Systems on a Chip. Fort Belvoir, VA: Defense Technical Information Center, lipiec 2001. http://dx.doi.org/10.21236/ada394800.
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