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Sharan, Bibhuti, i Ashish Malik. "Soft Switching Technique in Bidirectional Dc-Dc Converter for Hybrid Electric Vehicle". Journal of Futuristic Sciences and Applications 4, nr 1 (2021): 36–39. http://dx.doi.org/10.51976/jfsa.412106.
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The voltage at halfway should be equal for optimum voltage gain and energy transfer in order to achieve gentle switching in the bidirectional converter. Both from the side of high voltage to the side of low voltage. But,It is challenging to charge the battery during soft switching. Due to the same voltage level but a larger charging current in the middle. The battery split that is feasible for grid-to-vehicle (G2V) mode of operation when a vehicle's battery splits in two equal voltage part by using relay or breaker circuit configuration. [The forward converter is based on buck topology, the flyback converter is based on buck-boost topology, and both full-bridge and half-bridge converters can be formed from buck and boost topologies. In addition, converter types can be divided into using transformer cores . A net DC current flows in the forward and flyback topologies.
2
Leite, Rafael, João Afonso i Vítor Monteiro. "A Novel Multilevel Bidirectional Topology for On-Board EV Battery Chargers in Smart Grids". Energies 11, nr 12 (10.12.2018): 3453. http://dx.doi.org/10.3390/en11123453.
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This paper proposes a novel on-board electric vehicle (EV) battery charger (EVBC) based on a bidirectional multilevel topology. The proposed topology is formed by an AC-DC converter for the grid-side interface and by a DC-DC converter for the battery-side interface. Both converters are interfaced by a split DC-link used to achieve distinct voltage levels in both converters. Characteristically, the proposed EVBC operates with sinusoidal grid-side current, unitary power factor, controlled battery-side current or voltage, and controlled DC-link voltages. The grid-side converter operates with five voltage levels, while the battery-side operates with three voltage levels. An assessment, for comparison with classical multilevel converters for EVBCs is considered along the paper, illustrating the key benefits of the proposed topology. As the proposed EVBC is controlled in bidirectional mode, targeting the EV incorporation into smart grids, the grid-to-vehicle (G2V) and vehicle-to-grid (V2G) operation modes are discussed and evaluated. Both converters of the proposed EVBC use discrete-time predictive control algorithms, which are described in the paper. An experimental validation was performed under real operating conditions, employing a developed laboratory prototype.
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Luna, Massimiliano, Antonino Sferlazza, Angelo Accetta, Maria Carmela Di Piazza, Giuseppe La Tona i Marcello Pucci. "Modeling and Performance Assessment of the Split-Pi Used as a Storage Converter in All the Possible DC Microgrid Scenarios. Part II: Simulation and Experimental Results". Energies 14, nr 18 (7.09.2021): 5616. http://dx.doi.org/10.3390/en14185616.
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Bidirectional DC/DC converters such as the Split-pi can be used to integrate an energy storage system (ESS) into a DC microgrid providing manifold benefits. However, this integration deserves careful design because the ESS converter must behave like a stiff voltage generator, a non-stiff voltage generator, or a current generator depending on the microgrid configuration. Part I of this work presented a comprehensive theoretical analysis of the Split-pi used as an ESS converter in all the possible DC microgrid scenarios. Five typical microgrid scenarios were identified. Each of them required a specific state-space model of the Split-pi and a suitable control scheme. The present paper completes the study validating the theoretical analysis based on simulations and experimental tests. The chosen case study encompassed a 48 V, 750 W storage system interfaced with a 180 V DC microgrid using a Split-pi converter. It can represent a reduced-power prototype of terrestrial and marine microgrids. A prototypal Split-pi converter was realized in the lab, and several experimental tests were performed to assess the performance in each scenario. The results obtained from the experimental tests were coherent with the simulations and validated the study.
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Dwivedi, Dewang, Arun Kumar Maurya, Ayush Gangwar, Anas Ahmad, Ayush Pratap Maury i Hemant Ahuja. "Performance analysis of solar PV system for different converter configurations". Journal of Physics: Conference Series 2570, nr 1 (1.08.2023): 012009. http://dx.doi.org/10.1088/1742-6596/2570/1/012009.
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Abstract In present scenario power electronic converters are of great usage. Almost every electronic industry uses converters in one way or the other. If the converters are integrated with solar PV system, then their various parameters could be thoroughly studied and the most suitable converter could be chosen on the results obtained asper the performance parameters. This research work presents the thorough analysis of a PV system under different converter configurations. Mainly 6 converters are used in this entire research work Buck converter (Step down chopper), Boost converter (Step up chopper), Buck-Boost converter, Split-pi converter, Flyback converter and Linear voltage regulator. Simulations were done on MATLAB/Simulink and on the basis of it results were obtained graphically.
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Luna, Massimiliano, Antonino Sferlazza, Angelo Accetta, Maria Carmela Di Piazza, Giuseppe La Tona i Marcello Pucci. "Modeling and Experimental Validation of a Voltage-Controlled Split-Pi Converter Interfacing a High-Voltage ESS with a DC Microgrid". Energies 16, nr 4 (6.02.2023): 1612. http://dx.doi.org/10.3390/en16041612.
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The Split-pi converter can suitably interface an energy storage system (ESS) with a DC microgrid when galvanic isolation is not needed. Usually, the ESS voltage is lower than the grid-side voltage. However, limitations in terms of the ESS current make the use of a high-voltage ESS unavoidable when high power levels are required. In such cases, the ESS voltage can be higher than the microgrid voltage, especially with low microgrid voltages such as 48 V. Despite its bidirectionality and symmetry, the Split-pi exhibits a completely different dynamic behavior if its input and output ports are exchanged. Thus, the present work aims to model the Split-pi converter operating with an ESS voltage higher than the grid-side voltage in three typical microgrid scenarios where the controlled variable is the converter’s output voltage. The devised state-space model considers the parasitic elements and the correct load model for each scenario. Furthermore, it is shown that the presence of the input LC filter can make the design of the loop controllers more complicated than in the case of a lower ESS voltage than the grid-side voltage. Finally, the study is validated through simulations and experimental tests on a lab prototype, and a robustness analysis is performed.
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Ali, Salman, Santiago Bogarra, Muhammad Mansooor Khan, Ahmad Taha, Pyae Pyae Phyo i Yung-Cheol Byun. "Prospective Submodule Topologies for MMC-BESS and Its Control Analysis with HBSM". Electronics 12, nr 1 (21.12.2022): 20. http://dx.doi.org/10.3390/electronics12010020.
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Battery energy storage systems and multilevel converters are the most essential constituents of modern medium voltage networks. In this regard, the modular multilevel converter offers numerous advantages over other multilevel converters. The key feature of modular multilevel converter is its capability to integrate small battery packs in a split manner, given the opportunity to submodules to operate at considerably low voltages. In this paper, we focus on study of potential SMs for modular multilevel converter based battery energy storage system while, keeping in view the inconsistency of secondary batteries. Although, selecting a submodule for modular multilevel converter based battery energy storage system, the state of charge control complexity is a key concern, which increases as the voltage levels increase. This study suggests that the half-bridge, clamped single, and full-bridge submodules are the most suitable submodules for modular multilevel converter based battery energy storage system since, they provide simplest state of charge control due to integration of one battery pack along with other advantages among all 24 submodule topologies. Depending on submodules analysis, the modular multilevel converter based battery energy storage system based on half-bridge submodules is investigated by splitting it into AC and DC equivalent circuits to acquire the AC and DC side power controls along with an state of charge control. Subsequently, to validate different control modes, a downscaled laboratory prototype has been developed.
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Siton, Yarden, Vladimir Yuhimenko, Dmitry Baimel i Alon Kuperman. "Baseline for Split DC Link Design in Three-Phase Three-Level Converters Operating with Unity Power Factor Based on Low-Frequency Partial Voltage Oscillations". Machines 10, nr 9 (24.08.2022): 722. http://dx.doi.org/10.3390/machines10090722.
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The study sets a baseline for split DC link capacitance values and voltage set points in three-phase three-level AC/DC (or DC/AC) converters operating with unity power factor. In order to equalize the average values of partial DC link voltages, the controller generates a zero-sequence containing DC components only while employing neither dedicated DC link capacitance balancing hardware nor high-order zero-sequence component injection. Such a baseline is required in order to evaluate the effectiveness of different DC link capacitance reduction methods proposed in the literature. Unlike most previous works, utilizing neutral point current based on cumbersome analytical expressions to determine neutral point potential oscillations, the instantaneous power balance-based approach is employed in this paper, resulting in greatly simplified and more intuitive expressions. It is demonstrated that while the total DC link voltage is low-frequency ripple-free under unity power factor balanced AC-side operation, split DC link capacitors absorb triple-fundamental frequency power components with one-sixth load power magnitude. This yields significant opposite phase partial voltage ripples. In such a case, selection of DC link capacitances and voltage set points must take into account the expected values of AC-side phase voltage magnitude and split DC link capacitor voltage and current ratings. Simulation and experimental results validate the proposed methodology by application to a 10 kVA T-type converter prototype.
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De Kooning, Jeroen D. M., Dimitar Bozalakov i Lieven Vandevelde. "Discrete Time Domain Modeling and Control of a Grid-Connected Four-Wire Split-Link Converter". Electronics 10, nr 4 (21.02.2021): 506. http://dx.doi.org/10.3390/electronics10040506.
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Distributed generation (DG) allows the production of renewable energy where it is consumed, avoiding transport losses. It is envisioned that future DG units will become more intelligent, not just injecting power into the grid but also actively improving the power quality by means of active power filtering techniques. In this manner, voltage and current harmonics, voltage unbalance or over-voltages can be mitigated. To achieve such a smart DG unit, an appropriate multi-functional converter topology is required, with full control over the currents exchanged with the grid, including the neutral-wire current. For this purpose, this article studies the three-phase four-wire split-link converter. A known problem of the split-link converter is voltage unbalance of the bus capacitors. This mid-point can be balanced either by injecting additional zero-sequence currents into the grid, which return through the neutral wire, or by injecting a compensating current into the mid-point with an additional half-bridge chopper. For both methods, this article presents a discrete time domain model to allow controller design and implementation in digital control. Both techniques are validated and compared by means of simulation results and experiments on a test setup.
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Rao, S. Nagaraja, D. V. Ashok Kumar i Ch Sai Babu. "Grid Connected Distributed Generation System with High Voltage Gain Cascaded DC-DC Converter Fed Asymmetric Multilevel Inverter Topology". International Journal of Electrical and Computer Engineering (IJECE) 8, nr 6 (1.12.2018): 4047. http://dx.doi.org/10.11591/ijece.v8i6.pp4047-4059.
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The paper presents distributed generation (DG) system in grid connected mode of operation with asymmetric multi-level inverter (AMLI) topology. Cascaded type DC-DC converter is employed to feed proposed AMLI topology. The DG output voltage (generally low voltage) is stepped up to the required level of voltage using high-gain DC-DC converter. Proposed AMLI topology consists of capacitors at the primary side. The output of high-gain DC-DC converter is fed to split voltage balance single-input multi-output (SIMO) circuit to maintain voltage balance across capacitors of AMLI topology. Cascaded DC-DC converters (both high-gain converter and SIMO circuit) are operated in closed-loop mode. The proposed AMLI feeds active power to grid converting DC type of power generated from DG to AC type to feed the grid. PWM pattern to trigger power switches of AMLI is also presented. The inverting circuit of MLI topology is controlled using simplified Id-Iq control strategy in this paper. With the proposed control theory, the active power fed to grid from DG is controlled and power factor is maintained at unity. The proposed system of DG integration to grid through cascaded DC-DC converters and AMLI structure is validated from fixed active power to grid from DG condition. The proposed system is developed and results are obtained using MATLAB/SIMULINK software.
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Lin, Bor-Ren. "Soft Switching DC Converter for Medium Voltage Applications". Electronics 7, nr 12 (18.12.2018): 449. http://dx.doi.org/10.3390/electronics7120449.
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A dc-dc converter with asymmetric pulse-width modulation is presented for medium voltage applications, such as three-phase ac-dc converters, dc microgrid systems, or dc traction systems. To overcome high voltage stress on primary side and high current rating on secondary side, three dc-dc circuits with primary-series secondary-parallel structure are employed in the proposed converter. Current doubler rectifiers are used on the secondary side to achieve low ripple current on output side. Asymmetric pulse-width modulation is adopted to realize soft switching operation for power switches for wide load current operation and achieve high circuit efficiency. Current balancing cells with magnetic component are used on the primary side to achieve current balance in each circuit cell. The voltage balance capacitors are also adopted on primary side to realize voltage balance of input split capacitors. Finally, the circuit performance is confirmed and verified from the experiments with a 1.44 kW prototype.
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Rao, S. Nagaraja, D. V. Ashok Kumar i Ch Sai Babu. "Integration of Reversing Voltage Multilevel Inverter Topology with High Voltage Gain boost Converter for Distributed Generation". International Journal of Power Electronics and Drive Systems (IJPEDS) 9, nr 1 (1.03.2018): 210. http://dx.doi.org/10.11591/ijpeds.v9.i1.pp210-219.
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<table width="0" border="1" cellspacing="0" cellpadding="0"><tbody><tr><td valign="top" width="593"><p>The conventional energy sources available to us are on the verge of depletion. This depletion of conventional energy source leads to concentrate more on alternative energy sources. In this research, the focus is on the role of renewable energy sources (RES) in electrical power generation. Even though, the RES based plants produce power, we cannot directly connect it to the grid or loads. Because, the voltage ratings and nature supply of RES plants would not match with the load. Hence, this is a major issue for connecting RES plants to load or other utility. The power electronic converters are extensively being used as a link between load and supply. As most of the renewable energy power generation is DC in nature, the DC-DC converter is used to increase the voltage level and this DC must be converted to AC for grid connection. Therefore, inverters are used for DC to AC conversion. In this paper, the DC supply of renewable energy is connected to load by using cascade DC-DC converters along with a proposed reversing voltage (RV) multilevel inverter (MLI). The first DC-DC converter is used to enhance the voltage level with high gain and second converter is used to split the DC supply for inverter convenience. In this paper, proposed RV symmetrical and asymmetrical MLI generates 7, 9, 11, 13 and 15 levels with only ten power switches. In-phase level-shifted triangular carrier type sine pulse width modulation (PWM) technique is employed to trigger the commutating switches of proposed RV MLI. Switches of H-Bridge for reverse voltage appearance across the load are triggered by simple pulse generator. The circuits are modeled and simulated in MATLAB/SIMULINK software. Results are presented and discussed.</p></td></tr></tbody></table>
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Zhu, Donglin, Maliang Liu i Zhangming Zhu. "A High Energy Efficiency and Low Common-Mode Voltage Variation Switching Scheme for SAR ADCs". Journal of Circuits, Systems and Computers 27, nr 01 (23.08.2017): 1850010. http://dx.doi.org/10.1142/s021812661850010x.
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In this paper, a high energy saving digital-to-analog converter (DAC) switching scheme with common-mode voltage variation in 1LSB is proposed for successive approximation register (SAR) analog-to-digital converters (ADCs). Based on the third reference ([Formula: see text]), split-capacitor technique and complementary switching method, the proposed switching scheme achieves a 99.6% switching energy reduction and a 75% area reduction compared to the conventional architecture, furthermore, the common-mode voltage varies only 1LSB during a conversion cycle.
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Lara, Jorge, Lesedi Masisi, Concepcion Hernandez, Marco A. Arjona i Ambrish Chandra. "Novel Single-Phase Grid-Tied NPC Five-Level Converter with an Inherent DC-Link Voltage Balancing Strategy for Power Quality Improvement". Energies 14, nr 9 (5.05.2021): 2644. http://dx.doi.org/10.3390/en14092644.
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This paper presents a novel single-phase grid-tied neutral-point-clamped (NPC) five-level converter (SPFLC). Unlike the literature on five-level NPC topologies, the proposed one is capable of inherently balancing the voltage of the DC-link split capacitors. For this purpose, a simple Multicarrier Phase Disposition (MPD) Pulse Width Modulation (PWM) technique is used, thus avoiding both complex modifications to the Space Vector Modulation (SVM) and offset voltage injections into the carrier based (CB) PWM, as commonly done in most conventional balancing algorithms. Bearing in mind that the proposed balancing strategy only requires measuring the capacitors’ voltages and the sign of the converter output current, it has a very low complexity. The developed strategy is not only straightforwardly implemented but is also very effective for obtaining symmetrical and undistorted voltage levels from the proposed multilevel converter, as well as for significantly improving the power quality of the SPFLC output voltage and, in turn, of the grid current. The simulation results obtained with MATLAB-SimPowerSystems as well as the experimental results obtained with the prototype built in the laboratory validate the topology of the proposed NPC five-level converter and the voltage balancing strategy, by showing a good performance under step-changes and exhaustive operating test conditions.
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Al-Ateeq, A., i A. J. Alateeq. "Soft-Charging Effects on a High Gain DC-to-DC Step-up Converter with PSC Voltage Multipliers". Engineering, Technology & Applied Science Research 10, nr 5 (26.10.2020): 6323–29. http://dx.doi.org/10.48084/etasr.3773.
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This paper proposes a split-phase control diagram for a new design of a DC-to-DC boost converter which is called PSC-boost and studies its performance. The PSC-boost has two sides, the primary is a PSC converter and the secondary is a DC-to-DC boost converter. The effect of applying the split-phase control diagram helps reduce the output impedance successfully and increases efficiency by 3%. The simulated and analytical results have been proven to validate the effect of the split-phase diagram. The simulated design contains five switches, five capacitors, seven diodes, and three inductors to step up 10V into 160V at 200KHz and 100KHz switching frequencies. The LTspice simulator was used to design and test the proposed model.
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Lin, Bor-Ren, i Kun-Yi Chen. "Hybrid LLC Converter with Wide Range of Zero-Voltage Switching and Wide Input Voltage Operation". Applied Sciences 10, nr 22 (20.11.2020): 8250. http://dx.doi.org/10.3390/app10228250.
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A new hybrid inductor-inductor-capacitor (LLC) converter is investigated to have wide voltage input operation capability and zero-voltage turn-on characteristics. The presented circuit topology can be applied for consumer power units without power factor correction or with long hold-up time requirement, photovoltaic energy conversion and renewable energy power transfer. To overcome the weakness of narrow voltage gain of resonant converter, the hybrid LLC converter with different turns ratio of transformer is presented and the experimental investigation is provided to achieve wide voltage input capability (400 V–50 V). On the input-side, the converter can operate as full bridge resonant circuit or half bridge resonant circuit with input split capacitors for high or low voltage input region. On the output-side, the less or more winding turns is selected to overcome wide voltage input operation. According to the circuit structures and transformer turns ratio, the single stage LLC converter with wide voltage input operation capability (400 V–50 V) is accomplished. The laboratory prototype has been developed and the experimental waveforms are measured and demonstrated to investigate the effectiveness of the presented hybrid LLC converter.
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A. Mejbel, Ihsan, i Turki K. Hassan. "DESIGN AND SIMULATION OF HIGH GAIN SEPIC DC–DC CONVERTER". Journal of Engineering and Sustainable Development 27, nr 1 (3.01.2023): 138–48. http://dx.doi.org/10.31272/jeasd.27.1.12.
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This paper proposes a new model of the converter, a single-ended primary-inductor converter (SEPIC) type with a high gain voltage for clean energy sources. The suggested model is established by combining the traditional SEPIC DC-DC converter with two different circuits. The first circuit is a split-inductor circuit that is made of three diodes and two inductors, while the second circuit consists of two capacitors and two diodes. The suggested SEPIC DC-DC converter achieves a high voltage gain of 7.5 times the supply voltage when the duty cycle value is kept at 0.5 with only a unique controlled switch. The gain of the proposed converter is greatly increased while the ripple of output voltage and the input current is decreased for higher values of the duty cycle. In addition, the decreased value of the input current ripple results in limited switching stress. The suggested converter is analyzed in detail for continuous conduction mode (CCM). A MATLAB/ Simulink program is used to confirm the analysis of the suggested converter.
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Cittanti, Davide, Matteo Gregorio, Eugenio Bossotto, Fabio Mandrile i Radu Bojoi. "Three-Level Unidirectional Rectifiers under Non-Unity Power Factor Operation and Unbalanced Split DC-Link Loading: Analytical and Experimental Assessment". Energies 14, nr 17 (25.08.2021): 5280. http://dx.doi.org/10.3390/en14175280.
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Three-phase three-level unidirectional rectifiers are among the most adopted topologies for general active rectification, achieving an excellent compromise between cost, complexity and overall performance. The unidirectional nature of these rectifiers negatively affects their operation, e.g., distorting the input currents around the zero-crossings, limiting the maximum converter-side displacement power factor, reducing the split DC-link mid-point current capability and limiting the converter ability to compensate the low-frequency DC-link mid-point voltage oscillation. In particular, the rectifier operation under non-unity power factor and/or under constant zero-sequence voltage injection (i.e., when unbalanced split DC-link loading occurs) typically yields large and uncontrolled input current distortion, effectively limiting the acceptable operating region of the converter. Although high bandwidth current control loops and enhanced phase current sampling strategies may improve the rectifier input current distortion, especially at light load, these approaches lose effectiveness when significant phase-shift between voltage and current is required and/or a constant zero-sequence voltage must be injected. Therefore, this paper proposes a complete analysis and performance assessment of three-level unidirectional rectifiers under non-unity power factor operation and unbalanced split DC-link loading. First, the theoretical operating limits of the converter in terms of zero-sequence voltage, modulation index, power factor angle, maximum DC-link mid-point current and minimum DC-link mid-point charge ripple are derived. Leveraging the derived zero-sequence voltage limits, a unified carrier-based pulse-width modulation (PWM) approach enabling the undistorted operation of the rectifier in all feasible operating conditions is thus proposed. Moreover, novel analytical expressions defining the maximum rectifier mid-point current capability and the minimum peak-to-peak DC-link mid-point charge ripple as functions of both modulation index and power factor angle are derived, the latter enabling a straightforward sizing of the split DC-link capacitors. The theoretical analysis is verified on a 30 kW, 20 kHz T-type rectifier prototype, designed for electric vehicle ultra-fast battery charging. The input phase current distortion, the maximum mid-point current capability and the minimum mid-point charge ripple are experimentally assessed across all rectifier operating points, showing excellent performance and accurate agreement with the analytical predictions.
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Anusha, P., i B. V. Rajanna. "Induction drive system with DSTATCOM based asymmetric twin converter". International Journal of Power Electronics and Drive Systems (IJPEDS) 11, nr 4 (1.12.2020): 1826. http://dx.doi.org/10.11591/ijpeds.v11.i4.pp1826-1834.
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High power demands are usually met by advanced power electronics converters in several large utility and electric drives applications. Applications from high power drives commonly uses solution based multi pulse and multilevel converters. A common DC link with atleast one voltage source converter (VSC) working with almost fundamental switching frequency are used in converters of multipulse type, and each output module is connected with the multipulse transformer in series. When compared to that of solution with single-VSC, Several VSCs generating different triggering pulses are adjused in order to achieve current injected with low specified total harmonic distortion (THD) with losses of abridged switching. Huge structure in complexity and expensive cost expenditure of the multipulse transformer is the major limitation of this scheme. DC link split capacitors in addition are eliminated by modifying the topology of the circuit. Thus, the independent voltages of the DC capacitor are controlled and decreased in number and the flow of third harmonic current component in the transformer is eliminated. The scheme of the designed controller is depending on the derived mathematical system model. Simulaion observation is used to check the scheme performance and efficiency in a detailed way with drive control technique.
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Huang, Ming, i Jianhua Li. "Analysis and Design of the Split-Capacitor-Based Sub-Modules Equipped for Hybrid Modular Multilevel Converter". Energies 15, nr 7 (24.03.2022): 2370. http://dx.doi.org/10.3390/en15072370.
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The hybrid modular multilevel converter (MMC) is always featured and profited by the merits of the equipped power valves. Referring to this, a novel hybrid MMC topology equipped with the split-capacitor-based sub-modules (SCSMs) on the AC side is proposed. It aims to increase the utilization of the DC bus voltage with DC fault blocking capability. Especially compared to the hybrid MMC equipped with the full-bridge-based sub-modules (FBSMs) on the AC side, smaller power losses can be achieved for the proposed hybrid MMC, due to the reason that only one semiconductor device of the SCSM is inserted into the current flow route. Structurally, the proposed converter mainly consists of the half-bridge-based sub-module (HBSM) stacks and SCSM stacks. The HBSMs located on the DC converter side of the proposed hybrid MMC are in charge of exchanging active powers, while the SCSMs located on the AC converter side are in charge of shaping the circuit waveforms. Additionally, profited by the specific structure of the SCSM, the DC fault current could be cut off by imposing inversed voltages collected from the SCSM capacitor voltages on the uncontrollable diodes of the IGBTs. For the deep study, a detailed mathematical model and modulation control of the proposed hybrid MMC are analyzed. In addition, an analysis of the balancing control for SCSMs is also provided. Finally, the simulation and experimental results are proposed to verify the effectiveness of the theoretical analysis.
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Liu, Wenjie, Yongheng Yang, Tamas Kerekes, Elizaveta Liivik, Dmitri Vinnikov i Frede Blaabjerg. "Common-Mode Voltage Analysis and Reduction for the Quasi-Z-Source Inverter with a Split Inductor". Applied Sciences 10, nr 23 (4.12.2020): 8713. http://dx.doi.org/10.3390/app10238713.
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In transformerless grid-connected photovoltaic (PV) systems, leakage currents should be properly addressed. The voltage fluctuations between the neutral point of the grid and the PV array, i.e., common-mode voltage (CMV), will affect the value of the leakage currents. Therefore, the leakage currents can be attenuated through proper control of the CMV. The CMV depends on the converter topology and the modulation strategy. For the quasi-Z-source inverter (qZSI), the amplitude of the high-frequency components in the CMV increases due to the extra shoot-through (ST) state. The CMV reduction strategies for the conventional voltage source inverter (VSI) should be modified when applied to the qZSI. In this paper, an input-split-inductor qZSI is introduced to reduce the CMV, in which all the CMV reduction strategies for the VSI can be used directly with appropriate ST state insertion. Moreover, the proposed method can be extended to impedance source converters with a similar structure. Simulations and experimental tests demonstrate the effectiveness of the proposed strategy for the qZSI in terms of CMV reduction.
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Lin. "Analysis of a DC Converter with Low Primary Current Loss and Balance Voltage and Current". Electronics 8, nr 4 (17.04.2019): 439. http://dx.doi.org/10.3390/electronics8040439.
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A dc/dc pulse width modulation (PWM) circuit was investigated to realize the functions of reduced primary current loss and balanced voltage and current distribution. In the presented dc/dc converter, two full bridge pulse width modulation circuits were used with the series/parallel connection on the high-voltage/low-voltage side. The flying capacitor was adopted on the input side to achieve voltage balance on input split capacitors. The magnetic coupling element was employed to achieve current sharing between two parallel circuits. A capacitor-diode passive circuit was adopted to lessen the primary current at the commutated interval. The phase-shifted duty cycle control approach was employed to regulate load voltage and implement soft switching characteristics of power metal-oxide-semiconductor field-effect transistors (MOSFETs). Finally, the experimental results using a 1.68 kW prototype converter were obtained to confirm the performance and feasibility of the studied circuit topology.
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Samiullah, Md, Atif Iqbal, Imtiaz Ashraf i Sandy Rahme. "Split Duty Super Boost Converter for High Voltage Applications in a DC Microgrid". IEEE Access 9 (2021): 101078–88. http://dx.doi.org/10.1109/access.2021.3097887.
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Heidinger, Michael, Qihao Xia, Christoph Simon, Fabian Denk, Santiago Eizaguirre, Rainer Kling i Wolfgang Heering. "Current Mode Control of a Series LC Converter Supporting Constant Current, Constant Voltage (CCCV)". Energies 12, nr 14 (20.07.2019): 2793. http://dx.doi.org/10.3390/en12142793.
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This paper introduces a control algorithm for soft-switching series LC converters. The conventional voltage-to-voltage controller is split into a master and a slave controller. The master controller implements constant current, constant voltage (CCCV) control, required for demanding applications, for example, lithium battery charging or laboratory power supplies. It defines the set-current for the open-loop current slave controller, which generates the pulse width modulation (PWM) parameters. The power supply achieves fast large-signal responses, e.g., from 5 V to 24 V , where 95% of the target value is reached in less than 400 s . The design is evaluated extensively in simulation and on a prototype. A match between simulation and measurement is achieved.
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Chang, Fei, Zhongping Yang i Fei Lin. "Research on Control Strategy of AC-DC-AC Substation Based on Modular Multilevel Converter". Mathematical Problems in Engineering 2017 (2017): 1–14. http://dx.doi.org/10.1155/2017/4157165.
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Significant disadvantages in power quality especially the unbalance problem and neutral sections restrict the evolution of conventional traction power supply system. A new traction power supply system based on three-phase to single-phase converter is studied, which can transfer active power from three-phase grid to single-phase catenary. One catenary section could be utilized in the new traction power supply system instead of the multiple split sections in conventional system. Three-phase to single-phase converter is the core equipment of new traction power system. MMC (modular multilevel converter) structure of AC-DC-AC substation is proposed in this paper. To solve the problem of the capacitor voltage balancing in MMC, a parallel sorting algorithm based on field programmable gate array (FPGA) is studied. And the correctness and effectiveness of the algorithm are verified by experiments. In addition, it is inevitable that the AC grid voltage will be unbalanced caused by the fault in the new system. Therefore, this paper focuses on the analysis of the effect of the unbalanced grid voltage on the operating characteristics of the MMC system. Finally, the correctness of the theoretical analysis is verified by simulation.
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Sega, Naonori, Yuta Somei, Hiroshi Shimada i Yoshinao Mizugaki. "Operation of a 4-bit RSFQ digital-to-analog converter based on a binary split-confluence configuration". Journal of Physics: Conference Series 2323, nr 1 (1.08.2022): 012033. http://dx.doi.org/10.1088/1742-6596/2323/1/012033.
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Abstract One of the unique applications of single-flux-quantum (SFQ) circuitry is a digital-to-analog converter (DAC) of which the output voltage is defined by the Josephson effect. Recently, we have designed and operated rapid single-flux-quantum (RSFQ) DACs with frequency modulation of SFQ pulse sequences. In this paper, we report our design and test results of a 4-bit RSFQ-DAC based on the configuration of the “sum of selected bits sequence (Σ-SBS)”. By adjusting the timing margins, in addition to the fabrication using the Nb integration process with the critical current density as high as 10 kA/cm2, the maximum output voltage up to 260 μV was demonstrated.
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Annambhotla, Lalitha T. S., i P. Parthiban. "Non-Isolated Power Factor Corrected AC/DC Converter with High Step-Down Voltage Ratio for Low-Power Applications". International Transactions on Electrical Energy Systems 2022 (15.10.2022): 1–16. http://dx.doi.org/10.1155/2022/7142957.
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This paper proposes a high step-down ratio AC-DC converter employing a quadratic buck converter with power factor correction. Conventional active power factor correction topologies employ boost-based correction schemes for unity power factor operation. This will require a steeper step-down ratio and higher switch voltage stress apart from complexity in the control scheme with sensors. The structure of the proposed topology is developed by combining the power factor correction stage with a high step-down stage. The passive input filter is split up into two for the purpose of reducing the thermal heating apart from offering a higher power factor. A single switch operation reduces the complexity of the control scheme. In addition, the number of conducting devices during the current path is also the same as the conventional buck converter due to cascading and hence offers lower conduction losses. The need for the converter to operate at an extremely low duty cycle is reduced due to the quadratic stage structure. The proposed converter operates at a moderate duty cycle, offering higher step-down voltage apart from reducing filtering requirements. MATLAB R2020b is used for carrying out simulation studies. Xilinx FPGA-based controller using system generator is implemented for the generation of pulses of appropriate duty cycle. Simulation and experimental results for a 150 W prototype are presented. An investigation and comparative evaluation of the conventional bridgeless buck system with the quadratic buck converter are carried out. The proposed structure offers the benefit of a higher step-down voltage ratio incorporating an inherent power factor correction stage along with the AC/DC stage.
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Lin, Lei, Jialu He i Chen Xu. "Analysis on Circulating Current and Split Capacitor Voltage Balance for Modular Multilevel Converter Based Three-phase Four-wire Split Capacitor DSTATCOM". Journal of Modern Power Systems and Clean Energy 9, nr 3 (2021): 657–67. http://dx.doi.org/10.35833/mpce.2019.000213.
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Shah, Syed Asmat Ali, Saad Arslan i Hyungwon Kim. "A Reconfigurable Voltage Converter With Split-Capacitor Charging and Energy Recycling for Ultra-Low-Power Applications". IEEE Access 6 (2018): 68311–23. http://dx.doi.org/10.1109/access.2018.2879471.
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Cittanti, Davide, Matteo Gregorio, Eugenio Bossotto, Fabio Mandrile i Radu Bojoi. "Full Digital Control and Multi-Loop Tuning of a Three-Level T-Type Rectifier for Electric Vehicle Ultra-Fast Battery Chargers". Electronics 10, nr 12 (17.06.2021): 1453. http://dx.doi.org/10.3390/electronics10121453.
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The rapid development of electric vehicle ultra-fast battery chargers is increasingly demanding higher efficiency and power density. In particular, a proper control of the grid-connected active front–end can ensure minimum passive component size (i.e., limiting design oversizing) and reduce the overall converter losses. Moreover, fast control dynamics and strong disturbance rejection capability are often required by the subsequent DC/DC stage, which may act as a fast-varying and/or unbalanced load. Therefore, this paper proposes the design, tuning and implementation of a complete digital multi-loop control strategy for a three-level unidirectional T-type rectifier, intended for EV ultra-fast battery charging. First, an overview of the operational basics of three-level rectifiers is presented and the state-space model of the considered system is derived. A detailed analysis of the mid-point current generation process is also provided, as this aspect is widely overlooked in the literature. In particular, the converter operation under unbalanced split DC-link loads is analyzed and the converter mid-point current limits are analytically identified. Four controllers (i.e., dq-currents, DC-link voltage and DC-link mid-point voltage balancing loops) are designed and their tuning is described step-by-step, taking into account the delays and the discretization introduced by the digital control implementation. Finally, the proposed multi-loop controller design procedure is validated on a 30 kW, 20 kHz T-type rectifier prototype. The control strategy is implemented on a single general purpose microcontroller unit and the performances of all control loops are successfully verified experimentally, simultaneously achieving low input current zero-crossing distortion, high step response and disturbance rejection dynamics, and stable steady-state operation under unbalanced split DC-link loading.
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Zorig, Abdelmalik, Mohammed Belkeiri, Said Barkat i Abdelhamid Rabhi. "Control of Grid Connected Photovoltaic System Using Three-Level T-Type Inverter". International Journal of Emerging Electric Power Systems 17, nr 4 (1.08.2016): 377–84. http://dx.doi.org/10.1515/ijeeps-2016-0067.
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Abstract Three-level T-Type inverter (3LT2I) topology has numerous advantageous compared to three-level neutral-point-clamped (NPC) inverter. The main benefits of 3LT2I inverter are the efficiency, inverter cost, switching losses, and the quality of output voltage waveforms. In this paper, a photovoltaic distributed generation system based on dual-stage topology of DC-DC boost converter and 3LT2I is introduced. To that end, a decoupling control strategy of 3LT2I is proposed to control the current injected into the grid, reactive power compensation, and DC-link voltage. The resulting system is able to extract the maximum power from photovoltaic generator, to achieve sinusoidal grid currents, and to ensure reactive power compensation. The voltage-balancing control of two split DC capacitors of the 3LT2I is achieved using three-level space vector modulation with balancing strategy based on the effective use of the redundant switching states of the inverter voltage vectors. The proposed system performance is investigated at different operating conditions.
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Kanuch, Jan, Peter Girovsky, Jaroslava Zilkova i Marek Pastor. "Design and Measurement of a Frequency Converter with SPWM Modulation of Output Voltage for a Two-Phase Induction Motor". Elektronika ir Elektrotechnika 29, nr 3 (27.06.2023): 11–18. http://dx.doi.org/10.5755/j02.eie.33865.
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This paper deals with the design, implementation, and measurements of a frequency converter with bipolar sinusoidal pulse width modulation (SPWM) of output voltage for two-phase induction motors. The paper is dedicated to an analysis of the operation of a two-phase frequency converter and its implementation. The inverter has a single-phase H-bridge topology with split DC link and bipolar switching to minimise the number of components. Insulated gate bipolar transistors (IGBTs) are used in the realisation of the inverter power section. The inverter is controlled using a digital signal processor (DSP) TMS320F28335. Measurements with a 0.12 kW two-phase induction motor were performed to verify the correct operation of the inverter. The influence of the switching frequency on the motor current ripple is measured for frequencies of the first harmonic up to 100 Hz.
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Yang, Xiao Guang. "Winding Loss Simulation and Optimal Design of a High Frequency Coaxial Transformer". Advanced Materials Research 466-467 (luty 2012): 567–71. http://dx.doi.org/10.4028/www.scientific.net/amr.466-467.567.
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A high frequency coaxial transformer (HFCT) with a split winding structure and litz wire has been developed for high frequency (HF) and high power DC/DC converter applications. A method combined numerical analysis of magnetic field and analytical calculation of litz wire winding losses, taking into account conduction losses and proximity effect losses, is proposed for the designed HFCT. The experimental results validate the winding loss calculation method. The measured results demonstrate that the voltage ratio has a good agreement with the turn ratio over the frequency range from 0.1MHz to 1MHz, indicating that the high coupling efficiency has been obtained.
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Jia, Yihang, Hongfei Wu, Yanfeng Zhang, Yue Liu i Yan Xing. "Single-Phase AC–DC Converter With Dual-Output Rectifier, Dual-Input DC Transformer, and Voltage-Split/Sigma Principle". IEEE Transactions on Power Electronics 35, nr 1 (styczeń 2020): 158–68. http://dx.doi.org/10.1109/tpel.2019.2914507.
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Kumar, Amritesh, i Vishal Verma. "Analysis and control of improved power quality single‐phase split voltage cascaded converter feeding three‐phase OEIM drive". IET Power Electronics 10, nr 8 (4.04.2017): 903–10. http://dx.doi.org/10.1049/iet-pel.2016.0488.
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Manandhar, Ujjal, Xinan Zhang, Hoay Beng Gooi, Benfei Wang i Feng Fan. "Active DC-link balancing and voltage regulation using a three-level converter for split-link four-wire system". IET Power Electronics 13, nr 12 (16.09.2020): 2424–31. http://dx.doi.org/10.1049/iet-pel.2020.0067.
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Bhattacharya, Shilpi, Prabal Deb, Sujit K. Biswas i Ambarnath Banerjee. "Open-Delta VSC Based Voltage Controller in Isolated Power Systems". International Journal of Power Electronics and Drive Systems (IJPEDS) 6, nr 2 (1.06.2015): 376. http://dx.doi.org/10.11591/ijpeds.v6.i2.pp376-386.
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<p>This paper proposes a reduced switch Open-Delta (OD-VSC) voltage controller for an standalone asynchronous generator (SAG), also known as the self-excited induction generator (SEIG),used in constant power applications such as pico hydro uncontrolled turbine driven isolated induction generator (IAG) for feeding three-phase loads. The proposed reduced switch voltage controller is used to regulate and control the generator terminal voltage as it is subjected to voltage drops, dips or flickers when the isolated power system is subjected to various critical loads. Generally this purpose is carried out by a STATCOM comprising of a three-leg six-switch inverter structure. Here, in this work the DSTATCOM is realized using a three-leg four-switch insulated gate bipolar transistor (IGBT)-based current controlled voltage-sourced converter (CC-VSC) and a self-supporting dc bus containing two split capacitors. The proposed generating system along with the controller is modeled and simulated in MATLAB along with Simulink and power system blockset (PSB) toolboxes. The system is simulated and the capability of the isolated generating system along with the reduced switch based voltage controller is presented here where the generator feeds linear and non-linear loads are investigated.</p>
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Chandra Rao, A. Purna, Y. P. Obulesh i Ch Sai Babu. "Power Factor Correction in Two Leg Inverter Fed BLDC Drive Using Cuk Dc-Dc Converter". International Journal of Power Electronics and Drive Systems (IJPEDS) 6, nr 2 (1.06.2015): 196. http://dx.doi.org/10.11591/ijpeds.v6.i2.pp196-204.
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Earlier for variable speed application conventional motors were used, but these motors have poor characteristics. These drawbacks were overcome by brushless Dc motor drive. Now days in most of the applications such as industrial, domestic, aerospace, defense, medical and traction etc, brushless DC motor (BLDCM) is popular for its high efficiency, high torque to weight ratio, small size, and high reliability, ease of control and low maintenance etc. BLDC motor is a electronic commutator driven drive i.e. it uses a three-phase voltage source inverter for its operation, electronic devices means there is a problem of poor power quality, more torque ripple and speed fluctuations. This paper deals with the CUK converter two leg inverter fed BLDCM drive in closed loop operation. The proposed control strategy on CUK converter two leg inverter fed BLDCM drive with split DC source is modeled and implemented using MATLAB / Simulink. The proposed method improves the efficiency of the drive system with Power factor correction feature in wide range of the speed control, less torque ripple and smooth speed control.
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El Ouardi, Hind, Ayoub El Gadari, Youssef Ounejjar i Kamal Al-Haddad. "Conception and Experimental Validation of a Standalone Photovoltaic System Using the SUPC5 Multilevel Inverter". Electronics 11, nr 17 (3.09.2022): 2779. http://dx.doi.org/10.3390/electronics11172779.
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In this work, an advanced pulse width modulation (PWM) technique was developed to provide the auto-balancing of the capacitors voltages of the five-level split-packed U-Cells (SPUC5) single-phase inverter, and then, the latter was applied to a photovoltaic (PV) system in standalone mode to evaluate its performance in this kind of application. The SPUC5 inverter makes use of only five switches (four active bidirectional switches and one four quadrant switch), one DC source and two capacitors to generate five levels of output voltage and a current with a quasi-sinusoidal waveform which reduces the total harmonic distortion (THD) without the need to add filters or sensors, and also reduces its cost compared to the other multilevel inverters. In the proposed system; the incremental conductance (INC) algorithm is combined with a DC/DC boost converter to reach the maximum power (MP) of the PV array by tracking the MP point (MPP). The offered concept has been constructed and then simulated in the MATLAB/Simulink environment to evaluate its efficiency. According to the results, the self-balancing of the capacitors voltages has been achieved. A comparative study was performed with the traditional PWM technique. The proposed PV system has been validated by experimental results.
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Haricharan, Mr Voggu, i S. Radha Krishna Reddy. "Power Quality Improvement by Using Discrete Wavelet Transform Based DSTATCOM". International Journal for Research in Applied Science and Engineering Technology 11, nr 3 (31.03.2023): 736–48. http://dx.doi.org/10.22214/ijraset.2023.49442.
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Abstract: The discrete wavelet transform-based control technique for the distribution static compensator (DSTATCOM) is utilized in this paper to improve power quality at common points of interconnection (CPI). The discrete wavelet transform, the time frequency analysis technique, is used here to split distorted load current of each phase in order to recover the line frequency of harmonic components for estimating the respective active power components. The difference between the estimated reference active component and the detected load currents is utilized to create reference currents for DSTATCOM's voltage source converter (VSC) management. The performance of DSTATCOM is presented using MATLAB software under varied linear and non-linear load circumstances. Under various load situations, total harmonic distortion (THD) of the source current is less than 5% with a power factor of unity.
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Lara, Jorge, Lesedi Masisi, Concepcion Hernandez, Marco A. Arjona i Ambrish Chandra. "Novel Five-Level ANPC Bidirectional Converter for Power Quality Enhancement during G2V/V2G Operation of Cascaded EV Charger". Energies 14, nr 9 (5.05.2021): 2650. http://dx.doi.org/10.3390/en14092650.
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This paper presents a novel single-phase (SP) active-neutral point clamped (ANPC) five-level bidirectional converter (FLBC) for enhancing the power quality (PQ) during the grid-to-vehicle (G2V) and vehicle-to-grid (V2G) operation of an electric vehicle (EV) charger connected in series. This EV charger is based on a dual-active half-bridge DC-DC converter (DAHBC) with a high frequency isolation transformer. Unlike the comparable ANPC topologies found in literature, the proposed one has two more switches, i.e., ten instead of eight. However, with the addition of these components, the proposed multilevel converter not only becomes capable of properly balancing the voltage of the DC-link split capacitors under various step-changing conditions but it achieves a better efficiency, a lower stress of the switching devices and a more even distribution of the power losses. The resulting grid-tied ANPC-SPFLBC and DAHBC are accurately controlled with a cascaded control strategy and a single-phase shift (SPS) control technique, respectively. The simulation results obtained with MATLAB-SimPowerSystems as well as the experimental results obtained in laboratory validate the proposed ANPC-SPFLBC for a set of exhaustive tests in both V2G and G2V modes. A detailed power quality analysis carried out with a Fluke 43B alike demonstrates the good performance of the proposed topology.
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Lakhdari, Abdelkader, Boualam Benlahbib i Thameur Abdelkrim. "Model Predictive Control for Three-Phase Three-Level NPC Inverter Based APF Interfacing Single Stage Photovoltaic System to the Grid". Journal Européen des Systèmes Automatisés 55, nr 1 (28.02.2022): 25–34. http://dx.doi.org/10.18280/jesa.550103.
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A finite control set model predictive control (FCS-MPC) based controller has a fast dynamic response and robustness. furthermore, the presence of a cost function gives designers a degree of freedom to include system control targets, constraints and system non-linearities. On the other hand, Multilevel inverter (MI) topologies are becoming a strong alternative in distributed power generation system (DPGS), among these topologies is the three-phase three-level NPC (TTLNPC) inverter. Generally, to properly operate this topology, the applied current control ensures the achievement of two main objectives. First, the output current must be controlled to track its reference. Second, the two dc-link capacitor voltages have to be equal and balanced. In this paper, FCS-MPC is proposed to control the TTLNPC inverter based parallel active power filter (APF) adopted to connect a photovoltaic system (PVS) to the grid and perform a harmonic mitigation. The proposed FCS-MPC exploit the model of the system to predict the future values of the inverter currents by selecting the best voltage vector that aims to minimize a predefined cost function. Instead of using the popular redundant vectors algorithms to balance the two-split dc-link capacitor voltages, another term will be added to the expression of the cost function to achieve this goal. The PV panel is coupled directly to the inverter without DC/DC converter, the P&O MPPT algorithm is responsible to generate the capacitor reference voltage whatever the climatic conditions are. Simulations using Matlab/Simulink were performed to prove the efficiency of the proposed technique to mitigate the grid current harmonics, and to ensure a continuous power injection and perform a load power sharing.
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Luan, Jian, Xuqiang Zheng, Danyu Wu, Yuzhen Zhang, Linzhen Wu, Lei Zhou, Jin Wu i Xinyu Liu. "A 56 GS/s 8 Bit Time-Interleaved ADC in 28 nm CMOS". Electronics 11, nr 5 (23.02.2022): 688. http://dx.doi.org/10.3390/electronics11050688.
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This paper presents a real-time output 56 GS/s 8 bit time-interleaved analog-to-digital converter (ADC), where the full-speed converted data are output by 16-lane transmitters. A 64-way 8 bit asynchronous SAR array using monotonous and split switching strategy with 1 bit redundancy is utilized to achieve a high linearity and high-power efficiency. A low-power ring voltage-controlled oscillator-based injection-locked phase-locked loop combining with a phase interpolator-based time-skew adjuster is developed to generate the 8 equally spaced sampling phases. Digital gain correction, digital-detection-analog-correction offset calibration, and coarse–fine two-step time-skew calibration are combined to optimize the ADC’s performances. An edge detector and phase selector associated with a common near-end data-transmission position and far-end data-collection instant are designed to avoid reset competition and implement deterministic latency. Fabricated in a 28 nm CMOS process, the prototype ADC achieves an outstanding SNDR of 36.38 dB at 56 GS/s with a 19.9 GHz input, where 7.25 dB and 9.33 dB are optimized by offset-gain calibration and time-skew calibration, respectively. The ADC core occupies an area of 1.2 mm2 and consumes 432 mW power consumption.
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Arafa, Kawther I., Dina M. Ellaithy, Abdelhalim Zekry, Mohamed Abouelatta i Heba Shawkey. "Successive Approximation Register Analog-to-Digital Converter (SAR ADC) for Biomedical Applications". Active and Passive Electronic Components 2023 (4.01.2023): 1–29. http://dx.doi.org/10.1155/2023/3669255.
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This study presents a survey of the most promising reported SAR ADC designs for biomedical applications, stressing advantages, disadvantages, and limitations, and concludes with a quantitative comparison. Recent progress in the development of a single SAR ADC architecture is reviewed. In wearable and biosensor systems, a very small amount of total power must be devoured by portable batteries or energy-harvesting circuits in order to function correctly. During the past decade, implementation of the high energy efficiency of SAR ADC has become the most necessary. So, several different implementation schemes for the main components of the SAR ADC have been proposed. In this review study, the various circuit architectures have been explained, beginning with the sample and hold (S/H) switching circuits, the dynamic comparator, the internal digital-to-analog converter (DAC), and the SAR control logic. In order to achieve low power consumption, numerous different configurations of dynamic comparator circuits are revealed. At the end of this overview, the evolutions of DAC architecture in distinct biomedical applications today can make a tradeoff between resolution, speed, and linearity, which represent the challenges of a single SAR ADC. For high resolution, the dual split capacitive DAC (CDAC) array technique and hybrid capacitor technique can be used. Also, for ultralow power consumption, various voltage switching schemes are achieved to reduce the number of switches. These schemes can save switching energy and reduce capacitor array area with high linearity. Additionally, to increase the speed of the conversion process, a prediction-based ADC design is employed. Therefore, SAR ADC is considered the ideal solution for biomedical applications.
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T., Yuvaraja, i K. Ramya. "Statistical data analysis for harmonic reduction in 3Ø -fragmented source using novel fuzzy digital logic switching technique". Circuit World 45, nr 3 (5.08.2019): 148–55. http://dx.doi.org/10.1108/cw-12-2018-0107.
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Purpose The purpose of this paper is to analyze the Luo super boost converter coupled fragmented source inversion system (LC-FSIS) and the progress of a controller structure for energy stored. The inversion system is characterized by a diode arm structure and can be easily amassed into a conversion system for high/medium- power conversion systems. Design/methodology/approach The investigation is based on the practice of a simplified circuit established as common anode/common cathode, where all the diodes in each arm are connected to a renewable DC voltage source. In this proposed work, a novel fuzzy digital logic switching technique (FDLST) for three-phase fragmented source inversion (FSI) for enhancement in power excellence is measured to enterprise the novel fuzzy digital logic switching technique to authorize operative voltage utilization and enhanced harmonic spectrum. Findings Sequential circuit design using flip-flops is used in the analysis of fuzzy digital logic switching technique. Originality/value The three-phase fragmented source configuration is designed using a split DC source which is obtained from the Opto-electric source and is implemented using MOSFET. The procedure of novel FDLST reduces the Statistical Harmonic Reduction (SHR). Simulation and results are carried out to prove the dominance of designed FDLST.
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Cui, Tongkai, Qishuang Ma i Ping Xu. "Sufficient Condition-Based Stability Analysis of a Power Converter Applied Switching Transient Waveform Modification Using Kharitonov’s Theorem". Electronics 8, nr 2 (21.02.2019): 245. http://dx.doi.org/10.3390/electronics8020245.
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The rapid switching action of power metal-oxide-semiconductor field-effect transistor (MOSFET) causes high-level electromagnetic interference (EMI) in power converters. The switching transient waveform modification method realized by closed-loop gate drive has been recognized as an effective high-frequency EMI reduction approach. However, feedback control of power MOSFET in the saturation region would introduce stability problems. This paper presents a sufficient condition-based stability analysis of all the operating points during turn-off using Kharitonov’s theorem. Firstly, a small-signal MOSFET model during turn-off was used to derive the closed-loop system transfer function. The nonlinear capacitances and the rest constant parameters of the small-signal model were determined based on the device characteristics and the expected outcome of the drain-source voltage. Then we split the turn-off switching transient into several subintervals, during which the system characteristic equation became an interval polynomial due to the nonlinear capacitances. Finally, Kharitonov’s theorem was applied in each subinterval to evaluate the stability, thereby achieving the overall system stability analysis during turn-off. Experiments were conducted to investigate the system’s stability and the results confirmed the validity of the proposed analysis. This work presents an implementable design guideline for the applied switching transient waveform modification of power converters via closed-loop gate drive.
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Tang, Fang, Qiyun Ma, Zhou Shu, Yuanjin Zheng i Amine Bermak. "A 28 nm CMOS 10 bit 100 MS/s Asynchronous SAR ADC with Low-Power Switching Procedure and Timing-Protection Scheme". Electronics 10, nr 22 (19.11.2021): 2856. http://dx.doi.org/10.3390/electronics10222856.
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This paper presents a 10 bit 100 MS/s asynchronous successive approximation register (SAR) analog-to-digital converter (ADC) without calibration for industrial control system (ICS) applications. Several techniques are adopted in the proposed switching procedure to achieve better linearity, power and area efficiency. A single-side-fixed technique is utilized to reduce the number of capacitors; a parallel split capacitor array in combination with a partially thermometer coded technique can minimize the switching energy, improve speed, and decrease differential non-linearity (DNL). In addition, a compact timing-protection scheme is proposed to ensure the stability of the asynchronous SAR ADC. The proposed ADC is fabricated in a 28 nm CMOS process with an active area of 0.026 mm2. At 100 MS/s, the ADC achieves a signal-to-noise-and-distortion ratio (SNDR) of 51.54 dB and a spurious free dynamic range (SFDR) of 55.12 dB with the Nyquist input. The measured DNL and integral non-linearity (INL) without calibration are +0.37/−0.44 and +0.48/−0.63 LSB, respectively. The power consumption is 1.1 mW with a supply voltage of 0.9 V, leading to a figure of merit (FoM) of 35.6 fJ/conversion-step.
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Zhao, Zuoqin, Yufei Nai, Zhiguo Yu, Xin Xu, Xiaoyang Cao i Xiaofeng Gu. "Design of Low-Power ECG Sampling and Compression Circuit". Applied Sciences 13, nr 5 (6.03.2023): 3350. http://dx.doi.org/10.3390/app13053350.
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Compressed Sensing (CS) has been applied to electrocardiogram monitoring in wireless sensor networks, but existing sampling and compression circuits consume too much hardware. This paper proposes a low-power and small-area sampling and compression circuit with an Analog-to-Digital Converter (ADC) and a CS module. The ADC adopts split capacitors to reduce hardware consumption and uses a calibration technique to decrease offset voltage. The CS module uses an approximate addition calculation for compression and stores the compressed data in pulsed latches. The proposed addition completes the accurate calculation of the high part and the approximate calculation of the low part. In a 55 nm CMOS process, the ADC has an area of 0.011 mm2 and a power consumption of 0.214 μW at 10 kHz. Compared with traditional design, the area and power consumption of the proposed CS module are reduced by 19.5% and 31.7%, respectively. The sampling and compression circuit area is 0.325 mm2, and the power consumption is 2.951 μW at 1.2 V and 100 kHz. The compressed data are reconstructed with a percentage root mean square difference of less than 2%. The results indicate that the proposed circuit has performance advantages of hardware consumption and reconstruction quality.
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Urrea-Quintero, Jorge-Humberto, Nicolás Muñoz-Galeano i Jesús M. López-Lezama. "Robust Control of Shunt Active Power Filters: A Dynamical Model-Based Approach with Verified Controllability". Energies 13, nr 23 (27.11.2020): 6253. http://dx.doi.org/10.3390/en13236253.
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This paper presents the robust control of Three-Leg Split-Capacitor Shunt Active Power Filters (TLSC SAPFs) by means of structured H∞ controllers for reactive, unbalanced, and harmonic compensation and the DC-link bus voltage regulation. Robust controller synthesis is performed based on the TLSC SAPF dynamical model including power losses in passive elements. Before the control implementation, a systematic procedure for the nonlinear controllability verification of the converter and its quantification using the set-theoretic approach is presented. Controllability verification serves to accurately design the SAPF’s operation region. Thus, a Voltage Oriented Control (VOC) structure is implemented by using two different approaches to determine the PI controller parameters: (1) the traditional Pole-Placement method (PP-PI) and (2) the H∞-PI structured synthesis approach, which leads to PI robust controllers. From the latter approach, two sets of parameters are obtained. The first set considers the nominal model (H∞-PI), and the second one explicitly accounts for the model parametric uncertainties (H∞-uPI). An optimization procedure is presented for obtaining the optimal H∞-PI and H∞-uPI controller parameters where four complementary constrains are defined to establish a trade-off between the controllers performance and robustness. The enforcement of constraints is later evaluated for each of three PI controllers obtained. This work aims to establish a common ground for the comparison of robust control strategies applied to TLSC APFs; therefore, the TLSC SAPF compensation performance is measured and compared with the performance indices: integral of the absolute error (IAE), integral of the time-weighted absolute error (ITAE), integral of the absolute control action (IUA), and maximum sensitivity (Ms).
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Shen, Shiqi, Hui Wang, Mengqiu Li, Yaojing Feng i Yichang Zhong. "Torque-Enhanced Phase Current Detection Schemes for Multiphase Switched Reluctance Motors with Reduced Sensors". Applied Sciences 12, nr 12 (11.06.2022): 5956. http://dx.doi.org/10.3390/app12125956.
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An n/2-sensor-based and an (m + 1)/2-sensor-based phase current detection scheme are proposed for even-numbered switched reluctance motors (EMSRMs) with n phases and odd-numbered switched reluctance motors (OMSRMs) with m phases. For the EMSRMs, the phases are divided into n/2 groups each of which includes two phases furthest from each other, and the lower dc bus is split into n/2 + 1 buses such that the currents through the lower switches of a group flow through a bus whose current is detected by a sensor. For the OMSRMs, the phases are divided into (m + 1)/2 groups and the currents through the lower switches of a group are detected by a multiplexed sensor without converter modification; the phase grouping is generalized as an optimization problem considering the volume and measuring range of the sensors. The schemes can detect the magnetization and freewheeling phase currents under multiphase excitation without pulse injection and voltage penalty. Compared to the existing schemes using cross-winding sensors, the proposed schemes can increase the motor torque by extending the phase conduction region. In addition, the proposed scheme for EMSRMs can combine the low-cost low-side shunt current sensing technique, and the proposed scheme for OMSRMs can increase the current sensing resolution. Simulations are carried out to validate the two proposed schemes. The proposed (m + 1)/2-sensor-based scheme is further verified experimentally.
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Jiao, Y., F. L. Luo i B. K. Bose. "Voltage-lift split-inductor-type boost converters". IET Power Electronics 4, nr 4 (2011): 353. http://dx.doi.org/10.1049/iet-pel.2010.0093.
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