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Artykuły w czasopismach na temat „SPICE Implementation”

Autor: Grafiati

Data publikacji: 6 września 2023

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1

Fauzi, Ahmad, Novita Indriyani i Andika Bayu Hasta Yanto. "IMPLEMENTATION OF SALES INFORMATION SYSTEM OF INDONESIAN SPICES AT PT.INDO REMPAH". JURNAL TEKNOLOGI DAN OPEN SOURCE 4, nr 1 (22.06.2021): 01–07. http://dx.doi.org/10.36378/jtos.v4i1.1227.

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Spices and herbs are biological resources that have long played an important role in human life. In the current pandemic where our bodies have an immune system that can manage the body's power, but the factors of age, lifestyle and regular use of drugs can affect the level of body power, therefore this spice has been considered to provide health and this has led to the demand for spices. high enough. The continuous use of spices, both from the household sector to the industrial sector, makes consumers have to find or buy these spices every day to the market or to spice collectors for industrial consumers. To meet market needs and consumer needs directly, therefore the proposed solution to overcome this problem is to use e-commerce media. The system development model used in making this information system is the SDCL (System Development Life Cycle) waterfall (Waterfall) or classic life flow. The stages that are passed in the system analysis and design process include: system requirements analysis, design, code generator, testing and support. From the results of this study, it is hoped that the existence of this spice sales information system can help farmers, especially spice producers, in terms of increasing the selling power of their agriculture, making it easier to carry out promotions, sales transactions to produce sales reports.

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Goteti, U. S., i M. C. Hamilton. "SPICE model implementation of quantum phase‐slip junctions". Electronics Letters 51, nr 13 (czerwiec 2015): 979–81. http://dx.doi.org/10.1049/el.2015.0904.

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Korobkov, Alexander, Amit Agarwal i Subramanian Venkateswaran. "Efficient FinFET Device Model Implementation for SPICE Simulation". IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 34, nr 10 (październik 2015): 1696–99. http://dx.doi.org/10.1109/tcad.2015.2424956.

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4

Lee, Jonghwan. "Low Frequency Noise Modeling and SPICE Implementation of Nanoscale MOSFETs". JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE 21, nr 1 (28.02.2021): 39–48. http://dx.doi.org/10.5573/jsts.2021.21.1.039.

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Sussman-Fort, S. E., i J. C. Hantgan. "SPICE implementation of lossy transmission line and Schottky diode models". IEEE Transactions on Microwave Theory and Techniques 36, nr 1 (1988): 153–55. http://dx.doi.org/10.1109/22.3497.

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Syahroni, Faez, Ulung Pribadi i Suranto Suranto. "Implementation of The Spice Route Program in Aceh Province: Opportunities and Challenges as a World Cultural Heritage". Journal of Governance and Public Policy 10, nr 1 (26.02.2023): PRESS. http://dx.doi.org/10.18196/jgpp.v10i1.16371.

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This study aims to see the implementation, opportunities, and challenges of the Spice Route program in Aceh Province as a world cultural heritage with several indicators, namely Bureaucratic Structure, Resources, Disposition, Communication, Program Content, and Context. A qualitative method with a case study approach and NVivo 12 Plus as a supporter of the analysis. The findings of this study indicate that the implementation of the Spice Route program in Aceh Province has not been fully running well, there are many weaknesses in terms of the bureaucratic structure and budgetary resources as well as human resources, commitments are still minimal, and do not meet standards. Furthermore, in terms of activities, it was found that there were still many activities that were ceremonial in nature and did not lead to physical activities, such as the construction of a spice botanical garden as a center for agro-tourism and agro-industry of Aceh spices. In terms of opportunities, it has excellent potential to be used as a world cultural heritage with historical evidence of its herbs and its location as a gateway to the Straits of Malacca and the Indian Ocean for international trade routes. In terms of challenges, there is no good cooperation between agencies, both vertical agencies and the Aceh government and the Aceh government and Regency / City Government.

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7

Umoh, Ime J., Tom J. Kazmierski i Bashir M. Al-Hashimi. "A Dual-Gate Graphene FET Model for Circuit Simulation—SPICE Implementation". IEEE Transactions on Nanotechnology 12, nr 3 (maj 2013): 427–35. http://dx.doi.org/10.1109/tnano.2013.2253490.

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8

Tanaka, Chika, Kanna Adachi, Motohiko Fujimatsu, Akira Hokazono, Yoshiyuki Kondo i Shigeru Kawanaka. "Implementation of TFET SPICE Model for Ultra-Low Power Circuit Analysis". IEEE Journal of the Electron Devices Society 4, nr 5 (wrzesień 2016): 273–77. http://dx.doi.org/10.1109/jeds.2016.2550606.

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9

Sinha, Dheeraj Kumar, i Amitabh Chatterjee. "SPICE level implementation of physics of filamentation in ESD protection devices". Microelectronics Reliability 79 (grudzień 2017): 239–47. http://dx.doi.org/10.1016/j.microrel.2017.05.022.

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Pandey, Neeta, Sakshi Arora, Rinku Takkar i Rajeshwari Pandey. "DVCCCTA-Based Implementation of Mutually Coupled Circuit". ISRN Electronics 2012 (24.09.2012): 1–6. http://dx.doi.org/10.5402/2012/303191.

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This paper presents implementation of mutually coupled circuit using differential voltage current-controlled conveyor transconductance amplifier (DVCCCTA). It employs only two DVCCCTAs, one grounded resistor, and two grounded capacitors. The primary, secondary, and mutual inductances of the circuit can be independently controlled and tuned electronically. The effect of non-ideal behaviour of DVCCCTA on the proposed circuit is analyzed. The functionality of the proposed circuit is verified through SPICE simulation using 0.25 μm TSMC CMOS technology parameters.

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11

IÑIGUEZ, BENJAMIN, TOR A. FJELDLY, MICHAEL S. SHUR i TROND YTTERDAL. "SPICE MODELING OF COMPOUND SEMICONDUCTOR DEVICES". International Journal of High Speed Electronics and Systems 09, nr 03 (wrzesień 1998): 725–81. http://dx.doi.org/10.1142/s0129156498000312.

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We review recent advances in the modeling of novel and advanced semiconductor devices, including state-of-the-art MESFET and HFETs, heterodimensional FETs, resonant tunneling devices, and wide-bandgap semiconductor transistors. We emphasize analytical, physics-based modeling incorporating the important effects present in modern day devices, including deep sub-micrometer devices. Such an approach is needed in order to accurately describe and predict both stationary and dynamic device behavior and to make the models suitable for implementation in advanced computer aided design tool including circuit simulators such as SPICE.

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12

Kattimani, Akshata O. "Implementation of types of VCO". International Journal for Research in Applied Science and Engineering Technology 9, nr 8 (31.08.2021): 2972–678. http://dx.doi.org/10.22214/ijraset.2021.37881.

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Abstract: A Voltage Controlled Divider (VCO) is a basic building block in most of the electronic systems. Phase-locked loop (PLL), tone synthesizers, Frequency Shift Keying (FSK), frequency synthesizers, etc make use of VCO’s to generate an oscillating frequency that can be decided with the help of components. Voltage Controlled Divider can be implemented for analog applications. The project proposes three types of VCO using Electric tool and LT Spice XVII tool. The three VCO’s that are implemented are CMOS Ring Oscillator, Colpitts Oscillator and Relaxation Oscillator. These circuits generate two oscillating frequencies that is decided by the circult components. Keywords: Voltage Controlled Divider (VCO), CMOS Ring Oscillator, Colpitts Oscillator, Relaxation Oscillator, oscillating frequency.

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13

Li, Bo, i Guoyong Shi. "A Native SPICE Implementation of Memristor Models for Simulation of Neuromorphic Analog Signal Processing Circuits". ACM Transactions on Design Automation of Electronic Systems 27, nr 1 (31.01.2022): 1–24. http://dx.doi.org/10.1145/3474364.

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Since the memristor emerged as a programmable analog storage device, it has stimulated research on the design of analog/mixed-signal circuits with the memristor as the enabler of in-memory computation. Due to the difficulty in evaluating the circuit-level nonidealities of both memristors and CMOS devices, SPICE-accuracy simulation tools are necessary for perfecting the art of neuromorphic analog/mixed-signal circuit design. This article is dedicated to a native SPICE implementation of the memristor device models published in the open literature and develops case studies of applying such a circuit simulation with MOSFET models to study how device-level imperfections can make adversarial effects on the analog circuits that implement neuromorphic analog signal processing. Methods on memristor stamping in the framework of modified nodal analysis formulation are presented, and implementation results are reported. Furthermore, functional simulations on neuromorphic signal processing circuits including memristors and CMOS devices are carried out to validate the effectiveness of the native SPICE implementation of memristor models from the perspectives of simulation accuracy, efficiency, and convergence for large-scale simulation tasks.

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14

Swathi, Panchadi, i Gudla Bhanu Gupta. "Implementation of 2-bit Multiplier Circuit Using Pass Transistor Logic". International Journal for Research in Applied Science and Engineering Technology 10, nr 7 (31.07.2022): 5013–22. http://dx.doi.org/10.22214/ijraset.2022.46100.

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Abstract: In this paper, we implemented 2-bit Multiplier Circuit using Pass Transistor Logic. Pass Transistor Logic is used for high speed technology and is easy to build the basic gate structures. The developed circuit is an extension of pass transistor logic Ex-or gate. The proposed Multiplier circuit is implemented in 2x2 bit multiplier to achieve high speed, low area and less power dissipation. VLSI schematic tool and the analysis is done by using the LT Spice simulator. This paper aims at an optimization of power area and voltages of multiplier to show the better performance. The design is implemented in 0.18um CMOS technology and its functional parameters are compared and the best result is incorporated. Simulation results have been performed on LT Spice tool simulator at 1.8v and 2v supply voltage and simulations are carried out indicate the functionality of the proposed multiplier circuit compared with conventional design to verify the effectiveness and it shows the circuit has low power dissipation at high speeds.

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15

Yasasvi, Bhargava, Charu Rana i Pankaj Rakheja. "Implementation of Parity Checker Using CMOS Logic Techniques". International Journal of Advance Research and Innovation 6, nr 2 (2018): 31–34. http://dx.doi.org/10.51976/ijari.621806.

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The technology is growing rapidly where the sizes of the components are getting reduced as the size gets decreased the, possibility of errors gets increased. These errors can’t be prevented as they are generated in the running phase. To handle such problems, we need a circuit which will be monitoring continuously and correcting the errors generated. This paper proposes different ways to implement a parity checker in the previous self-checking register. When compared with previous techniques. The circuits are stimulated in spice using 90nm CMOS technology.

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16

Aguirre, Fernando Leonel, Jordi Suñé i Enrique Miranda. "SPICE Implementation of the Dynamic Memdiode Model for Bipolar Resistive Switching Devices". Micromachines 13, nr 2 (19.02.2022): 330. http://dx.doi.org/10.3390/mi13020330.

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This paper reports the fundamentals and the SPICE implementation of the Dynamic Memdiode Model (DMM) for the conduction characteristics of bipolar-type resistive switching (RS) devices. Following Prof. Chua’s memristive devices theory, the memdiode model comprises two equations, one for the electron transport based on a heuristic extension of the quantum point-contact model for filamentary conduction in thin dielectrics and a second equation for the internal memory state related to the reversible displacement of atomic species within the oxide film. The DMM represents a breakthrough with respect to the previous Quasi-static Memdiode Model (QMM) since it describes the memory state of the device as a balance equation incorporating both the snapback and snapforward effects, features of utmost importance for the accurate and realistic simulation of the RS phenomenon. The DMM allows simple setting of the initial memory condition as well as decoupled modeling of the set and reset transitions. The model equations are implemented in the LTSpice simulator using an equivalent circuital approach with behavioral components and sources. The practical details of the model implementation and its modes of use are also discussed.

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17

Wang, In-Soo. "Dynamic Pixel Models for a-Si TFT-LCD and Their Implementation in SPICE". ETRI Journal 34, nr 4 (1.08.2012): 633–36. http://dx.doi.org/10.4218/etrij.12.0211.0448.

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18

Marani, Roberto, Gennaro Gelao i Anna Gina Perri. "Comparison of ABM SPICE Library with Verilog-A for Compact CNTFET Model Implementation". Current Nanoscience 8, nr 4 (1.07.2012): 556–65. http://dx.doi.org/10.2174/157341312801784230.

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19

Pappas, I., A. T. Hatzopoulos, D. H. Tassis, N. Arpatzanis, S. Siskos, C. A. Dimitriadis i G. Kamarinos. "A simple and continuous polycrystalline silicon thin-film transistor model for SPICE implementation". Journal of Applied Physics 100, nr 6 (15.09.2006): 064506. http://dx.doi.org/10.1063/1.2226979.

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20

Varanda, Brenno R. "Testing and modeling of nozzle and eartip acoustics for balanced armature tweeter implementation in earphones". Journal of the Acoustical Society of America 153, nr 3_supplement (1.03.2023): A37. http://dx.doi.org/10.1121/10.0018066.

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Balanced armature (BA) receivers can be used as tweeters in earphones to increase their treble and ultra sound bandwidth. Key factors that influence the 9–20 kHz response of earphones when implementing BA tweeters are shown through experimental validation and comparison to newly-developed SPICE lumped parameter models (LPM). While the BA location and acoustic passage inside the earphone are important factors, the study focuses on how changes to the design of the earphone’s nozzle and the choice of ear-tips affect the 9–20 kHz frequency response. Improvements to existing SPICE LPM elements are provided, based on finite element analysis of the acoustic passageway that is formed between the compressed eartip and ear-simulator couplers. The model is compared to measurements from various nozzle and eartip configurations, validating its effectiveness to capture the earphone’s high frequency response due to changes to the earphone’s nozzle and eartip geometry.

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21

Abuelma'atti, Muhammad Taher. "Analog Low-Voltage Current-Mode Implementation of Digital Logic Gates". Active and Passive Electronic Components 26, nr 2 (2003): 111–14. http://dx.doi.org/10.1080/0882751031000073832.

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In this letter a new technique is introduced for implementing the basic logic functions using analog current-mode techniques. By expanding the logic functions in power series expressions, and using summers and multipliers, realization of the basic logic functions is simplified. Since no transistors are working in saturation, the problem of fan-out is alleviated. To illustrate the proposed technique, a circuit for simultaneous realization of the logic functions NOT, OR, NAND and XOR is considered. SPICE simulation results, obtained with 3 V supply, are included

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22

Srivastava, A., i K. Venkatapathy. "Design and Implementation of a Low Power Ternary Full Adder". VLSI Design 4, nr 1 (1.01.1996): 75–81. http://dx.doi.org/10.1155/1996/94696.

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In this work, the design and implementation of a low power ternary full adder are presented in CMOS technology. In a ternary full adder design, the basic building blocks, the positive ternary inverter (PTI) and negative ternary inverter (NTI) are developed using a CMOS inverter and pass transistors. In designs of PTI and NTI, W/L ratios of transistors have been varied for their optimum performance. The ternary full adder and its building blocks have been simulated with SPICE 2G.6 using the MOSIS model parameters. The rise and fall times of PTI show an improvement by a factor of 14 and 4, respectively, and that of the NTI by a factor of nearly 4 and 17, respectively over that of earlier designs implemented in depletion-enhancement CMOS (DECMOS) technology. The noise margins improve by a factor of nearly 2 in PTI and NTI, respectively.The ternary full adder has been fabricated in MOSIS two micron n-well CMOS technology. The full adder and its building blocks, NTI and PTI have been tested experimentally for static and dynamic performance, compared with the SPICE simulated behavior, and close agreement is observed.The ternary-valued logic circuits designed in the present work which do not use depletion mode MOSFETS perform better than that implemented earlier in DECMOS technology. The present design is fully compatible with the current CMOS technology, uses fewer components and dissipates power in the microwatt range.

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23

Silfa Ayu Safika, Rina Tri Agustini i Lies Permana. "Pemberdayaan Masyarakat dalam Penyusunan Program Pemanfaatan dan Penanaman TOGA". Jurnal Pengabdian Pada Masyarakat 7, nr 4 (30.11.2022): 939–48. http://dx.doi.org/10.30653/002.202274.193.

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COMMUNITY EMPOWERMENT IN THE PREPARATION OF TOGA UTILIZATION AND PLANTING PROGRAMS. The community of the RT 29 area have a tendency to use traditional medicine, especially herb and spice plants. However, the local community is still processing spice plants empirically and there is no management of the Family Medicine Garden (TOGA) in the area around the community settlements. The purpose of this community empowerment is to enable the community of RT 29 Sidodamai Village in the proper use of herb and spice plants as traditional medicine through education, the establishment of a TOGA cadre communication forum, and the preparation of a follow-up plan for TOGA planting. The implementation of activities in community empowerment uses the Participatory Rural Action (PRA) method which is carried out in 6 stages, i.e. community introduction, problem introduction, problem awareness, program implementation and program evaluation. The programs carried out included discussions, health education, mentoring TOGA cadres and the preparation of follow-up plans in the form of planting TOGA in RT 29. The results of this series of activities were that there was knowledge after being given health education material on the use of herb and spice plants, the existence of a communication forum for TOGA cadres with the Puskesmas Sidomulyo in planning the follow-up plan, and the independence of the community in carrying out the preparation for TOGA planting activities according to the planned schedule.

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24

Puspita Sari, Diana, Sela Tri Parwati, Dyah Ika Rinawati i Purnawan A. Wicaksono. "Analysis of Scraps Cause of Noodle Production in PT. Indofood CBP Success Makmur Tbk. using Fault Tree Analysis Methods". SHS Web of Conferences 49 (2018): 02012. http://dx.doi.org/10.1051/shsconf/20184902012.

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Food industry can survive when they can improve the productivity to meets the customer needs. PT Indofood CBP Sukses Makmur Noodle Division is one of food industry in Indonesia. Based on the production data of PT Indofood CBP Sukses Makmur Noodle Division Cibitung plant 3, found that the number of scrap noodles is almost always above the company minimum limit. This condition causes the company losing a profit of about 1.3 million per day per line. Based on these problems, this study aims to find the root causes of scraps of noodles production, then provide the advice on prevention of high amount of scrap of noodle production. The method used in this research is Fault Tree Analysis (FTA) and Five Step Plan analysis. The result of FTA analysis shows the cause of the high scrap of noodle production is the number of blocks noodles that fall as it passes through the conveyor in the frying and packing process, and because the operator less observant in connects the spice etiquette, less thorough to set the speed of the autoloader engine, less careful in case of handling the noodles. Suggested solutions include the implementation of 'seiri' by sorting reject spice oil and spices; 'seiton' by placing rolls of etiquette in easily reach place by the operator; 'seiko' by discarding etiquette, spices, and spiced oils into their respective containers; 'seiketsu' which is the division of responsibility for cleanliness of each operator; and 'shitsuke' ie routine briefing based on schedule.

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Anam, Choiroel, Nindyah Widyamurti, Danar Praseptiangga, Anastriyani Yulviatun i Dwi Aries Himawanto. "Aplikasi Mesin Pemasak Minuman Rempah Jahe (Zingiber officinale) Dengan Pengaduk Otomatis di UKM Polanmadu". PRIMA: Journal of Community Empowering and Services 5, nr 2 (31.12.2021): 199. http://dx.doi.org/10.20961/prima.v5i2.44202.

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<p><em><strong>Cooking Machine Application of Ginger Drink (Zingiber officinale) with Automatic Stirrer at UKM Polanmadu</strong></em>. The trend of instant spice drinks that function to maintain the body’s immunity is growing rapidly in the era of the Covid-19 pandemic. Ginger, which is a spice with various benefits, has made many Small and Medium Enterprises (SMEs) industry players take advantage of this potential. One of them is the instant spice drink SME industry player "Polanmadu" which produces natural instant spice drinks. The processing of instant spice drinks is still done conventionally, making Polanmadu SMEs unable to reach consumer demands. The purpose of these activities was to the introduction of appropriate technology in the production of instant spice drinks to produce products with more guaranteed quality and able to generate additional income for partners. The application of the cooking machine is useful so that the stirring process which has been going on for 3 hours conventionally using human power is replaced with electric power so that it is more efficient and profitable. The implementation begins with identification, planning, assembling tools, testing tools, and introducing tools to the spice instant drink production unit. The result showed that the introduction of a spice instant drink cooking machine can produce 20% more crystal ginger extract, automatic stirring while at the same time speeding up the formation of crystals from 3 hours to 2.5 hours, and the product crystal size is more homogenous and an increase in profit of Rp906,000-/day. Overall, the introduction of this spice-cooking machine makes the productivity of SMEs for instant spice drinks increase in quality and quantity.</p>

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Chimento, Filippo, Muhammad Nawaz, Niccoló Mora i Salvatore Tomarchio. "A Simplified Model for SiC Power Diode Modules for Implementation in Spice Based Simulators". Materials Science Forum 740-742 (styczeń 2013): 1089–92. http://dx.doi.org/10.4028/www.scientific.net/msf.740-742.1089.

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A simplified model for SiC Power diodes has been developed and implemented in Spice simulator in order to get the advantages of a modular and hierarchical structure that can be easily used for modeling of power semiconductor modules. The proposed approach is based on the lumped charge technique. One of the main targets for the proposed model is the implementation of a modeling structure starting from the evaluation and simplification of the semiconductor equations. The paper will show the implementation of the model along with an experimental evaluation of the proposed method.

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Batas, Daniel, i Horst Fiedler. "A Memristor SPICE Implementation and a New Approach for Magnetic Flux-Controlled Memristor Modeling". IEEE Transactions on Nanotechnology 10, nr 2 (marzec 2011): 250–55. http://dx.doi.org/10.1109/tnano.2009.2038051.

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Gao, X. F., J. J. Liou, J. Bernier, G. Croft i A. Ortiz-Conde. "Implementation of a comprehensive and robust MOSFET model in cadence SPICE for ESD applications". IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 21, nr 12 (grudzień 2002): 1497–502. http://dx.doi.org/10.1109/tcad.2002.804379.

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Niu, Dan, Xiao Jun Wang, Xing Peng Zhou, Guo Rui He i Zhou Rong Huang. "An Effective Implementation of the Nonlinear Homotopy Method for MOS Transistor Circuits". Applied Mechanics and Materials 619 (sierpień 2014): 166–72. http://dx.doi.org/10.4028/www.scientific.net/amm.619.166.

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Recently, an efficient homotopy method termed the nonlinear homotopy method (NLH) has been proposed for finding DC operating points of MOS transistor circuits. This method is not only efficient but also globally convergent. However, the programming of sophisticated homotopy methods is often difficult for non-experts or beginners. In this paper, an effective method for implementing the MOS NLH method on SPICE is proposed. By this method, we can implement the MOS NLH method from a good initial solution with various efficient techniques and without programming.

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Suryelita, Suryelita, Syamsi Aini, Desy Kurniawati, Indang Dewata, Sri Benti Etika, Melindra Mulia i Trisna Kumala Sari. "PKM Utilization of Natural Ingredients, Spices and Coconut as Family Drinks in an Effort to Increase Body Immune During Covid Conditions in Bungus Teluk Kabung District, Bungus Barat Village, Padang City". Pelita Eksakta 5, nr 1 (31.03.2022): 1. http://dx.doi.org/10.24036/pelitaeksakta/vol5-iss1/163.

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During the pandemic, people's activities are limited outside the home. However, this condition has an impact on their income economy. People can return to their activities to meet their needs by implementing a new normal life through health protocols. However, information and knowledge on how to maintain body immunity and the implementation of a new normal life are still limited. Therefore, it is necessary to disseminate information about the importance of body immunity during this pandemic. One of the areas affected by this pandemic is Bungus Barat Village, Bungus Teluk Kabung District. To answer the problems that arise in this area, it is necessary to carry out service activities that aim to provide information to the community, especially mothers who are the spearheads of families who are members of the association of PKK women in West Bungus Village on how to increase and maintain immunity during the pandemic. This increase in immunity includes lifestyle and diet that must be followed in the new normal life. Participants in this service activity include representatives of PKK women in West Bungus Village. The activity is in the form of implementation which is divided into two stages, namely guided activities, and independent activities. In the guided activities, interactive and practical counseling methods are used. Meanwhile, in independent activities, the target is to carry out the practice of making spice drinks and VCO in groups again. The results of the activity showed an increase in target knowledge about kitchen spices and coconut into VCO and nutritious spice drinks. The target community, namely PKK women, is also interested in consuming and producing their own VCO and spice drinks that have been made. In addition, from this activity, the community gained a good understanding of what to do during this pandemic, not only in complying with health protocols but also in regulating lifestyle and eating patterns.

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Melikyan, V. Sh, V. D. Hovhannisyan, M. T. Grigoryan, A. A. Avetisyan i H. T. Grigoryan. "Real Number Modeling Flow of Digital to Analog Converter". Proceedings of Universities. Electronics 26, nr 2 (kwiecień 2021): 144–53. http://dx.doi.org/10.24151/1561-5405-2021-26-2-144-153.

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This work introduces a flow of digital to analog (DAC) implementation in digital environment of SystemVerilog. Unlike the classical Verilog models, this digital to analog converter behavioral model is analog. Such type of model creation in general is called real number modeling. The DAC model is verified by the HSPICE and SystemVerilog Co-simulations which show its applicability in different register transfer level verification environments. The digital environment with real number modeled DAC runs around 8 times faster than the same environment with SPICE model. At the same time, the output signal’s voltage difference between RNM and SPICE models is less than 2 mV.

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Sun, Jun-Wei, Yu-Qi Tian i Yan-Feng Wang. "Eight-Person Voter Implementation Based on Hewlett-Packard Memristor". Journal of Nanoelectronics and Optoelectronics 15, nr 3 (1.03.2020): 404–14. http://dx.doi.org/10.1166/jno.2020.2728.

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The logic function based on memristor has been proved and can be applied to the future large scale integrated circuits. In this paper, we use logic circuit based on memristor to realize the function of eight-person voter. The basic logic circuit designed in this paper is consisted of two Hewlett-Packard memristors in series connection and an operational amplifier. Operational amplifiers are used to regulate the output voltages to meet the requirements of the input signals in the next stage circuits. The adder, binary comparator and multi-input logic gate are realized by using the designed logic circuit. Full adders, binary comparators and multi-input logic gates are combined into eight-person voter circuit. Theoretical analysis and spice simulation results verify the feasibility of the circuit under different cases. This method is expected to be applied to more complex voter logic circuits based on memristor.

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Graedel, Thomas E., i Alessio Miatto. "Alloy Profusion, Spice Metals, and Resource Loss by Design". Sustainability 14, nr 13 (21.06.2022): 7535. http://dx.doi.org/10.3390/su14137535.

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One of the most unfortunate attributes of technology’s routine and widespread use of most of the elements in the periodic table is the abysmal functional recycling rates that result from the complexity of modern technology and the rudimentary technological state of the recycling industry. In this work, we demonstrate that the vast profusion of alloys, and the complexities and miniaturization of modern electronics, render functional recycling almost impossible. This situation is particularly true of “spice metals”: metals employed at very low concentrations to realize modest performance improvements in advanced alloys or complex electronics such as smartphones or laptops. Here, we present a formal definition of spice metals and explore the significant challenges that product design decisions impose on the recycling industry. We thereby identify nine spice metals: scandium (Sc), vanadium (V), gallium (Ga), arsenic (As), niobium (Nb), antimony (Sb), tellurium (Te), erbium (Er), and hafnium (Hf). These metals are considered fundamental for the properties they provide, yet they are rarely recycled. Their routine use poses severe problems for the implementation of closed material loops and the circular economy. Based on the data and discussions in this paper, we recommend that spice metals be employed only where their use will result in a highly significant improvement, and that product designers place a strong emphasis on enabling the functional recycling of these metals after their first use.

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TEKDEMİR, ENIS İLKER, i HAKAN KUNTMAN. "Implementation of a novel BJT model into the SPICE simulation program to obtain extended accuracy". International Journal of Electronics 75, nr 6 (grudzień 1993): 1185–99. http://dx.doi.org/10.1080/00207219308907194.

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Pandey, Neeta, i Rajeshwari Pandey. "Current Mode Full-Wave Rectifier Based on a Single MZC-CDTA". Active and Passive Electronic Components 2013 (2013): 1–5. http://dx.doi.org/10.1155/2013/967057.

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This paper presents a current mode full-wave rectifier based on single modified Z copy current difference transconductance amplifier (MZC-CDTA) and two switches. The circuit is simple and is suitable for IC implementation. The functionality of the circuit is verified with SPICE simulation using 0.35 μm TSMC CMOS technology parameters.

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Kang, Haixia, Yuping Wu, Lan Chen i Xuelian Zhang. "Research on Device Modeling Technique Based on MLP Neural Network for Model Parameter Extraction". Applied Sciences 12, nr 3 (27.01.2022): 1357. http://dx.doi.org/10.3390/app12031357.

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The parameter extraction of device models is critically important for circuit simulation. The device models in the existing parameter extraction software are physics-based analytical models, or embedded Simulation program with integrated circuit emphasis (SPICE) functions. The programming implementation of physics-based analytical models is tedious and error prone, while it is time consuming to run the device model evaluation for the device model parameter extraction software by calling the SPICE. We propose a novel modeling technique based on a neural network (NN) for the optimal extraction of device model parameters in this paper, and further integrate the NN model into device model parameter extraction software. The technique does not require developers to understand the device model, which enables faster and less error-prone parameter extraction software developing. Furthermore, the NN model improves the extraction speed compared with the embedded SPICE, which expedites the process of parameter extraction. The technique has been verified on the BSIM-SOI model with a multilayer perceptron (MLP) neural network. The training error of the NN model is 4.14%, and the testing error is 5.38%. Experimental results show that the trained NN model obtains an extraction error of less than 6%, and its extraction speed is thousands of times faster than SPICE in device model parameter extraction.

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Zarwinda, Irma, Elfariyanti Elfariyanti, Hardiana Hardiana i Yuni Dewi Safrida. "Sosialisasi Minuman Rempah Penambah Imunitas Tubuh Dalam Upaya Mencegah Terpapar Virus Corona (Covid-19)". BAKTIMAS : Jurnal Pengabdian pada Masyarakat 3, nr 1 (30.03.2021): 22–29. http://dx.doi.org/10.32672/btm.v3i1.3024.

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Coronavirus Disease 2019 (COVID-19) adalah penyakit jenis baru yang belum pernah diidentifikasi sebelumnya pada manusia. Menjaga daya tahan tubuh atau imunitas termasuk salah satu kunci mencegah terinveksi virus tersebut diantaranya dengan cara mengkonsumsi minuman yang dibuat dari rempah-rempah seperti jahe, kunyit, sereh, kapulaga, cengkeh, kayu manis dan lainnya. Pelaksanaan PKM ini bertujuan untuk melakukan sosialisasi minuman rempah penambah imunitas tubuh dalam upaya mencegah terpapar virus covid-19. Kegiatan ini dilaksanakan di Desa Mireuk Lamreudeup Kecamatan Baitussalam Kabupaten Aceh Besar, hari Kamis Tanggal 10 Desember 2020, metode sosialisasi berupa ceramah dan diskusi. Bahan dan peralatan yang di gunakan di kegiatan ini seperti Spanduk, Brosur, minuman rempah kunyit asam dan bahan rempah yang digunakan untuk pembuatan minuman rempah. Peserta yang mengikuti kegiatan ini adalah 30 orang. Kegiatan ini berjalan dengan lancar dan mendapatkan tanggapan yang baik dari masyarakat Desa Mireuk Lamreudeup. Peserta sangat antusias dalam proses penyuluhan ini karena mendapatkan ilmu dan pengetahuan baru tentang minuman rempah yang ternyata memiliki khasiat yang luar biasa untuk tubuh. Kegiatan ini juga menjelaskan tentang menjaga pola hidup sehat di masa pandemi.Kata kunci : Covid-19, Minuman, RempahABSTRACTCoronavirus Disease 2019 (COVID-19) is a new type of disease that has never been previously identified in humans. Maintaining immunity is one of the keys to preventing being infected with the virus, including by consuming drinks made from spices such as ginger, turmeric, lemongrass, cardamom, cloves, cinnamon and others. The implementation of this PKM aims to socialize the immune-boosting spice drink in an effort to prevent exposure to the COVID-19 virus. This activity was carried out in Mireuk Lamreudeup Village, Baitussalam District, Aceh Besar District, Thursday, December 10, 2020, the method of socialization was in the form of lectures and discussions. Materials and equipment used in this activity such as banners, brochures, sour turmeric spice drinks and spice ingredients used for making spice drinks. The participants who took part in this activity were 30 people. this activity went smoothly and received a good response from the people of Mireuk Lamreudeup Village. Participants were very enthusiastic in this counseling process because they gained new knowledge and knowledge about spice drinks which turned out to have extraordinary properties for the body. This activity also explains about maintaining a healthy lifestyle during the pandemic.Keywords : Covid-19, Drinks, Spices

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Pandey, Neeta, Bharat Choudhary, Kirti Gupta i Ankit Mittal. "Bus Implementation Using New Low Power PFSCL Tristate Buffers". Active and Passive Electronic Components 2016 (2016): 1–8. http://dx.doi.org/10.1155/2016/4517292.

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This paper proposes new positive feedback source coupled logic (PFSCL) tristate buffers suited to bus applications. The proposed buffers use switch to attain high impedance state and modify the load or the current source section. An interesting consequence of this is overall reduction in the power consumption. The proposed tristate buffers consume half the power compared to the available switch based counterpart. The issues with available PFSCL tristate buffers based bus implementation are identified and benefits of employing the proposed tristate buffer topologies are put forward. SPICE simulation results using TSMC 180 nm CMOS technology parameters are included to support the theoretical formulations. The performance of proposed tristate buffer topologies is examined on the basis of propagation delay, output enable time, and power consumption. It is found that one of the proposed tristate buffer topology outperforms the others in terms of all the performance parameters. An examination of behavior of available and the proposed PFSCL tristate buffer topologies under parameter variations and mismatch shows a maximum variation of 14%.

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Yaminikumari, Jampani, i Gudla Bhanu Gupta. "Implementation of 1-bit Full Adder Circuit Using Pass Transistor Logic". International Journal for Research in Applied Science and Engineering Technology 10, nr 7 (31.07.2022): 4974–82. http://dx.doi.org/10.22214/ijraset.2022.46097.

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Abstract: In this work, we have implemented 1-bit Full Adder Circuit using Pass Transistor Logic. Pass Transistor Logic is used for high-speed technology and is easy to build the basic gate structures. The developed circuit is an extension of pass transistor logic Ex-or gate. The 1-bit Full Adder Circuit has been performed and obtained I-V characteristics and power for sum and carry were calculated. The effect of scaling on the overall performance is also analysed through the performance evaluation of 1-bit full adder circuit. Simulation results have been performed on LT Spice tool simulator at 1.8v single ended supply voltage and simulations are carried out to indicate the functionality of the proposed full adder circuit compared with conventional design to verify the effectiveness and it shows the circuit has low power dissipation at high speeds.

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Jin, Guang Lei, Hao Chen, Chuan Gao, Yun Peng Zhang, Mu Rong Li, Haruo Kobayashi, Shu Wu, Nobukazu Takai, Kiichi Niitsu i Khayrollah Hadidi. "Digital Auto-Tuning for Center Frequency and Q-Factor of Gm-C Band-Pass Filter". Key Engineering Materials 643 (maj 2015): 123–30. http://dx.doi.org/10.4028/www.scientific.net/kem.643.123.

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This paper describes digital auto-tuning schemes for second-order Gm-C bandpass filters which are suitable for fine CMOS implementation. We propose a switched Gm-C analog filter and two digital tuning schemes: a center frequency tuning scheme using the phase information and a Q factor tuning scheme using the magnitude information. We present circuits, describe their operations, and present SPICE simulation results.

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METIN, BILGIN, i KIRAT PAL. "NEW ALL-PASS FILTER CIRCUIT COMPENSATING FOR C-CDBA NON-IDEALITIES". Journal of Circuits, Systems and Computers 19, nr 02 (kwiecień 2010): 381–91. http://dx.doi.org/10.1142/s0218126610006128.

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In this paper, a CMOS current controlled current differencing buffered amplifier (C-CDBA) realization is presented. Also, a new first-order all-pass filter that compensates for some C-CDBA non-idealities is given as an application example. The all-pass filter circuit has low output impedance for easy cascadability and it can be made electronically tunable using the proposed C-CDBA implementation. The theoretical results are verified with SPICE simulations.

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Pandey, Neeta, Kirti Gupta i Bharat Choudhary. "New Proposal for MCML Based Three-Input Logic Implementation". VLSI Design 2016 (19.09.2016): 1–10. http://dx.doi.org/10.1155/2016/8712768.

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This paper presents a new proposal for three-input logic function implementation in MOS current mode logic (MCML) style. The conventional realization of such logic employs three levels of stacked source-coupled transistor pairs. It puts restriction on minimum power supply requirement and results in increased static power. The new proposal presents a circuit element named as quad-tail cell which reduces number of stacked source-coupled transistor levels by two. A three-input exclusive-OR (XOR) gate, a vital element in digital system design, is chosen to elaborate the approach. Its behavior is analyzed and SPICE simulations using TSMC 180 nm CMOS technology parameters are included to support the theoretical concept. The performance of the proposed circuit is compared with its counterparts based on CMOS complementary pass transistor logic, conventional MCML, and cascading of existing two input tripple-tail XOR cells and applying triple-tail concept in conventional MCML topology. It is found that the proposed XOR gate performs best in terms of most of the performance parameters. The sensitivity of the proposed XOR gate towards process variation shows a variation of 1.54 between the best and worst case. As an extension, a realization of 4 : 1 multiplexer has also been included.

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Eichenseer, Frank, Hans‐Martin Heinkel, Martin Benedikt, Maurizio Ahmann, Michael Holzner i Christoph Stadler. "Modeling & Simulation SPICE: Assessing the Capability of Credible Simulation Processes". INCOSE International Symposium 33, nr 1 (lipiec 2023): 399–415. http://dx.doi.org/10.1002/iis2.13029.

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AbstractWhile systems or products are becoming increasingly complex and new technologies emerge to manage this growing complexity, the potential of virtualized or simulation‐based product development is not yet fully exploited. This is mainly due to the fact that simulation results are still not trusted enough. Therefore, this paper outlines a possible approach to derive and ensure required levels of modeling and simulation credibility from the criticality of a simulation task. Furthermore, a framework is presented for assessing the implementation of a credible simulation process. This framework is based on an existing process reference model, ensuring modeling and simulation credibility, and on a process assessment model, which has proven itself in the German automotive industry in the assessment of process capability. Finally, the introduction to this framework is demonstrated using an example from the automotive domain, i.e., the simulation‐based safety approval for the virtual testing of an Automated Lane Keeping System.

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Vaidyanathan, S., Ch K. Volos i V. T. Pham. "Analysis, Control, Synchronization and SPICE Implementation of a Novel 4 - D Hyperchaotic Rikitake Dynamo System without Equilibrium". Journal of Engineering Science and Technology Review 8, nr 2 (kwiecień 2015): 232–44. http://dx.doi.org/10.25103/jestr.082.29.

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Vaidyanathan, Sundarapandian, Ahmad Taher Azar, Karthikeyan Rajagopal i Prasina Alexander. "Design and SPICE implementation of a 12-term novel hyperchaotic system and its synchronisation via active control". International Journal of Modelling, Identification and Control 23, nr 3 (2015): 267. http://dx.doi.org/10.1504/ijmic.2015.069936.

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Vaidyanathan, Sundarapandian, Christos Volos, Viet-Thanh Pham i Kavitha Madhavan. "Analysis, adaptive control and synchronization of a novel 4-D hyperchaotic hyperjerk system and its SPICE implementation". Archives of Control Sciences 25, nr 1 (1.03.2015): 135–58. http://dx.doi.org/10.1515/acsc-2015-0009.

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Abstract A hyperjerk system is a dynamical system, which is modelled by an nth order ordinary differential equation with n ⩾ 4 describing the time evolution of a single scalar variable. Equivalently, using a chain of integrators, a hyperjerk system can be modelled as a system of n first order ordinary differential equations with n ⩾ 4. In this research work, a 4-D novel hyperchaotic hyperjerk system has been proposed, and its qualitative properties have been detailed. The Lyapunov exponents of the novel hyperjerk system are obtained as L1 = 0.1448, L2 = 0.0328, L3 = 0 and L4 = −1.1294. The Kaplan-Yorke dimension of the novel hyperjerk system is obtained as DKY= 3.1573. Next, an adaptive backstepping controller is designed to stabilize the novel hyperjerk chaotic system with three unknown parameters. Moreover, an adaptive backstepping controller is designed to achieve global hyperchaos synchronization of the identical novel hyperjerk systems with three unknown parameters. Finally, an electronic circuit realization of the novel jerk chaotic system using SPICE is presented in detail to confirm the feasibility of the theoretical hyperjerk model.

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Wang, Longyan, Xiyang Jia, Guohua Zhao, Longfei Fan, Jianlong Wu, Zhenzhen Han, Siming Hu i in. "1.2: Invited Paper: Implementation of Full Panel IR-Drop Simulation for AMOLED Display Using Current SPICE Toolkit". SID Symposium Digest of Technical Papers 49 (kwiecień 2018): 2–5. http://dx.doi.org/10.1002/sdtp.12622.

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Godlevskyi, Mykhaylo, i Georgii Burlakov. "VERBAL DESCRIPTION OF THE TECHNOLOGY FOR PLANNING THE QUALITY IMPROVEMENT OF A SUBSET OF THE PROCESSES OF THE SPICE MATURITY REFERENCE MODEL". Bulletin of National Technical University "KhPI". Series: System Analysis, Control and Information Technologies, nr 1 (9) (15.07.2023): 41–48. http://dx.doi.org/10.20998/2079-0023.2023.01.06.

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It is noted that to solve the problem of developing information technology for planning the increase of maturity level of a subset of the processes of the SPICE reference maturity model, this issue must first be considered at the verbal level as a technology (sequence of stages) for the implementation of the given problem. At the first stage, the structure of the SPICE reference model, which consists of a number of separate processes, was formalized. This set is presented as a hierarchical structure: the first level is a set of processes and subprocesses; the second level is a set of process groups; the third level is a set of process categories. At the second stage, the method of assessing the level of possibility of a separate process/sub-process of the reference maturity model SPICE is considered. It is given from the point of view of two dimensions of the SPICE model: the purpose of the processes; the attributes of the processes (measurable characteristics necessary for managing the process and increasing the possibility of its execution). The third stage of the technology is focused on the synthesis of planning model of the subset development processes for the SPICE model, which determines the quality level of a separate component of the software development process (SDP), which in turn has a positive effect on the level of development of software systems. Assessment and planning of the possibility level of a subset of processes is implemented during a certain planning period under conditions of limited resources based on their optimal distribution, taking into account the importance of individual processes and their practices during the planning period. At the fourth stage of the technology, an algorithm for planning the development of a subset of processes of the reference maturity model SPICE is considered based on the method of sequential analysis of options. This is primarily due to the fact that the optimization model has an additive objective function. The method allows discarding those appropriate solutions that do not contain optimal solutions. In the future, when specifying the model, it is planned to choose an algorithm that belongs to this method and adapt it to the solution of the given problem. The fifth stage is devoted to information technology implementation of the developed model and algorithm. At this stage, the following set of problems is solved. Analysis of business processes of the technology of improving the quality of software development process. Definition of software requirements. Forming a diagram of use cases. Development of data models. Justification of the choice of tools for software development. Selection of reference system architecture. Next, software coding and testing. At the sixth stage, based on information technology, a number of variants of the plan for improving the quality of a subset of the processes of the SPICE maturity model are formed in order to support decision-making by the management of the IT company. For this, a set of effective solutions is preliminarily determined, which is proposed to determine the final option, which is implemented later.

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Lee, Dong-Jin, i Igor L. Markov. "CONTANGO: Integrated Optimization of SoC Clock Networks". VLSI Design 2011 (17.03.2011): 1–12. http://dx.doi.org/10.1155/2011/407507.

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On-chip clock networks are remarkable in their impact on the performance and power of synchronous circuits, in their susceptibility to adverse effects of semiconductor technology scaling, as well as in their strong potential for improvement through better CAD algorithms and tools. Existing literature is rich in ideas and techniques but performs large-scale optimization using analytical models that lost accuracy at recent technology nodes and have rarely been validated by realistic SPICE simulations on large industry designs. Our work offers a methodology for SPICE-accurate optimization of clock networks, coordinated to satisfy slew constraints and achieve best tradeoffs between skew, insertion delay, power, as well as tolerance to variations. Our implementation, called Contango, is evaluated on 45 nm benchmarks from IBM Research and Texas Instruments with up to 50 K sinks. It outperforms all published results in terms of skew and shows superior scalability.

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Mannan, Zubaer I., Hyongsuk Kim i Leon Chua. "Implementation of Neuro-Memristive Synapse for Long-and Short-Term Bio-Synaptic Plasticity". Sensors 21, nr 2 (18.01.2021): 644. http://dx.doi.org/10.3390/s21020644.

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In this paper, we propose a complex neuro-memristive synapse that exhibits the physiological acts of synaptic potentiation and depression of the human-brain. Specifically, the proposed neuromorphic synapse efficiently imitates the synaptic plasticity, especially long-term potentiation (LTP) and depression (LTD), and short-term facilitation (STF) and depression (STD), phenomena of a biological synapse. Similar to biological synapse, the short- or long-term potentiation (STF and LTP) or depression (STD or LTD) of the memristive synapse are distinguished on the basis of time or repetition of input cycles. The proposed synapse is also designed to exhibit the effect of reuptake and neurotransmitters diffusion processes of a bio-synapse. In addition, it exhibits the distinct bio-realistic attributes, i.e., strong stimulation, exponentially decaying conductance trace of synapse, and voltage dependent synaptic responses, of a neuron. The neuro-memristive synapse is designed in SPICE and its bio-realistic functionalities are demonstrated via various simulations.

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