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Portero, Trujillo Antoni. "Design Space Exploration of heterogeneous SoC Platforms for a Data-Dominant Application". Doctoral thesis, Universitat Autònoma de Barcelona, 2009. http://hdl.handle.net/10803/5365.
Pełny tekst źródłaPara este propósito, se ha elegido SystemC/C++ como lenguaje de descripción del sistema e idear los diferentes flujos de implementación para las diferentes arquitecturas y plataformas de silicio. Este poderoso marco de trabajo permite comparar implementaciones de una forma objetiva y razonada. Ya que nuestros resultados vienen de un αnico modelo y los diseños fueron mapeados en la misma tecnología de silicio (90nm CMOS).
El resultado de este trabajo de investigación es un juego de criterios y un mapa de las soluciones disponibles sobre el espacio de funcionamiento más bien que una aserción que dice que una solución αnica es mejor que las otras. Mi intención ha sido desarrollar técnicas y formular los métodos que pueden permitir aumentar la productividad en el diseño.
Este desarrollo puede ser extendido al nuevo paradigma de intercomunicación: Aquellos que usan técnicas DVFS y basadas en NoC para exploraciones e implementaciones MPSoC.
Consideramos la contribución mas significativa es el desarrollo del modelo con el cual se han realizado los diversos experimentos: El compresor MPEG que se ha realizado en SystemC/C++. Se ha realizado de la forma que implementaciones mαltiples son posibles: que van desde una parte grande en HW hasta la que se carga en un VLIW. En el caso de la FPGA y el ASIC, se han realizado dos implementaciones. Hemos obtenido un conjunto de resultados para siete diferentes implementaciones con cuatro diferentes objetivos HW (FPGA, ASIC, DSP y ASIP) con diferentes arquitecturas internas, seleccionadas para obtener puntos óptimos. Esto nos da que un incremento en eficiencia del 56 % para velocidad versus 26 % en energía en la solución FSME (20% para velocidad y 57 % para energía en la solución FAST). En el caso de los ISPs, las mejoras en el código se han realizado de forma que se obtienen implementaciones mejores que las que se conseguirían con una implementación directa del código no solo mejoras en el código sino mejoras en las microarquitecturas de silicio que forman el VLIW en el caso del ASIP. Otra contribución ha sido la realización de una NoC a nivel funcional en SystemC.
The main goal of this thesis is to obtain a set of results for the implementation of a given system level application down to different architectural platforms. This allowed carrying out a fair comparison that includes to build the whole system and to complete the design chain to the diverse silicon targets. This comparison uses four variables for its evaluation (execution time, chip area, energy consumption and design time) and produces a map of different optimal implementation points according to a given set or operating requirements. I built a complete MPEG-4 MP. This standard is a well known reference example, pretty popular in the scientific literature and this compressor is also a fine example of data-flow application. Therefore, results extracted from this thesis can be extended to other data-flow applications. I considered necessary to compute image compression with real-time constraints. Hence, I would like to dispose of the most flexible design possible in order to map the same specification into the different platforms.
For that purpose, I chose SystemC/C++ as description system level language and setup the different implementation flows for the different architectural and silicon platforms. This powerful framework allows comparing implementations in a reasonably objective way. Since our results come from a unique reference model and all designs were finally mapped in the same silicon technology (90nm CMOS).
The result of this research work is a set of criteria and a map of the available solutions on the performance space rather than an assertion saying that a unique solution is better than others. My intention has been to develop techniques and formulate methods that increased design productivity. This development can be further applied to the new parading of implementations: those that use DVFS techniques and NoC-based MPSoc implementation explorations.
We consider the most important contribution is the development of the model able to achieve the different experiments: the MPEG compressor that has been realized in SystemC/C ++. It is designed in a way that multiple implementations are possible, ranging from a large part in HW up to loaded in an accelerator as a VLIW. In case of the FPGA and ASIC, two implementations have been carried out. We obtained a set of values for seven different implementations targeting four different HW platforms (FPGA, ASIC, DSP and ASIP) with diverse internal architectures, selected to get optimal points. In the case of ASIC, we managed to end up with the layouts of the two solutions. This led to an increase in efficiency of 56 % for speed versus 26 % for energy (in FSME solution 20% for speed and 57% for energy in FAST solution). In case of the ISPs, code improvements have been accomplished to come up to more ideal solutions with regard to those who would be obtained by a direct implementation. In case of the ASIP the improvements have not only been realized in the code but also in the silicon micro architecture that form the VLIW. Other contribution is the accomplishment of a functional NoC in SystemC.
Rouxel, Samuel. "Modélisation et Caractérisation d'une Plate-Forme SOC Hétérogène : Application à la Radio Logicielle". Phd thesis, Université de Bretagne Sud, 2006. http://tel.archives-ouvertes.fr/tel-00124433.
Pełny tekst źródłaUne chaîne UMTS a permis la validation de l'outil réalisé, en confrontant les résultats estimés de l'outil, à ceux mesurés sur une plate-forme temps réel hétérogène (multi-DSP, multi-FPGA). Une partie du travail s'est concentré sur l'identification des composants utiles à la conception des systèmes SoC, et de leurs caractéristiques, en adéquation avec le niveau d'abstraction considéré. Une autre partie des travaux a porté sur la définition des modèles UML, et donc du profil, qui définissent la sémantique des différents composants identifiés en fonction de la configuration (PIM, PSM), ainsi que leurs relations. Une réflexion a été nécessaire afin d'élaborer les diverses règles de vérification et modèles d'exécution qui permettent d'informer le concepteur de ses erreurs et de la faisabilité du système modélisé. Un modèle de système d'exploitation a également été inclus, enrichissant la liste des éléments (composants) déjà définis et démontrant l'extensibilité du profil.
Rouxel, Samuel. "Modélisation et caractérisation de plates-formes SoC hétérogènes : application à la radio logicielle". Lorient, 2006. http://www.theses.fr/2006LORIS077.
Pełny tekst źródłaThe work of this PhD has been carried out within the framework of the A3S project and relies on component aspects integrated within a SoC platform design methodology, which is based on the UML language. This methodology proposes a high-level design framework based on the A3S UML profile developed to provide real-time embedded system semantic especially in SDR domain. An MDA approach has been considered to deal with different abstraction levels when specifying systems. First part of the work focused on identifying the component required designing a SoC system, and their characteristics depending on the component abstraction levels. Several types of component (software and hardware) whose characteristics depend on their modelling (PIM or PSM models) have been considered. Second part of the work focused on the definition of UML metamodels, which are grouped to define the A3S UML profile that establish the semantic of identified components depending on their modelling and their relations. We have defined extensive verification rules and applied a model of computation to inform designers about errors that have been done and to ensure the feasibility of their systems. Finally an operating system model has been included to demonstrate the scalability and the extension mechanisms of the UML language and profile which improve the list of components that have been already integrated within our framework. An UMTS application has validated our approach by comparing the estimated results computed by the tool with measured results obtained on a heterogeneous real-time platform (with several DSP and FPGA)
Zedek, Sabeha Fettouma. "Intégration d'architectures mixtes reconfigurables : Application à la détection de défauts dans des structures hétérogènes". Thesis, Toulouse, INSA, 2015. http://www.theses.fr/2015ISAT0005/document.
Pełny tekst źródłaScientific activities described in this PhD thesis are part of the theme of smart environment, strategy axes of ADREAM with the LAAS-CNRS. Since several years, our research team (N2IS) had a field of interest in SHM (Structural Health Monitoring) with the objective of doing a smart diagnostic on different heterogeneous structures. Indeed, the maturity of innovative materials such as composites triggering interest among aircraft manufacturers, or even the use of materials like concrete structures of civil engineering, all those heterogeneous structures that require periodic monitoring and / or continuous one. This is to detect cracks, disbond, surface corrosion or even delamination. To do this, existing solutions usually rely on technologies of nondestructive testing (NDT) that incorporate mostly sensor networks low-power systems interfaced with analysis of signals. These approaches have significant functional limitations: they are not versatile and do not allow for continuity of service in a "degraded" when operating on battery power with a minimum level of energy mode. Our research is a view related to the quantization level of robustness of a heterogeneous structure. Its aim is the development and integration of hardware reconfigurable mixed (A / D ) systems. After an investigation of the main technological solutions reprogrammable hardware and given the problems associated with developments in analytical embedded and minimizing the energy consumption of sensor algorithms. The choice was based on technologies like FPAA and FPGA. Initially our research studies have focused on the study of reconfigurable analog hardware analog. The objective was to show a conceptual feasibility of integrating a complex conditioning system (implementation of a synchronous detection technique), considering the tradeoff between a decision on the fly reconfiguration and a rational energy management system. Therefore, the question of how to integrate and store data necessary for the development of an efficient digital processing. A solution based on a hybrid approach with a chip produced by Xilinx called Zynq and embedded on a Zedboard. This solution is more efficient than a PSoC approach and allowed the development and implementation of signal processing techniques with tools for optimization and provided a solution of self-generation code trough a graphic interface. Following this research, the results obtained demonstrate the validity of the concepts implemented and allow us to imagine the next smart generation architectures
Lacouture, Mayleen. "A chemical programming language for orchestrating services : Application to interoperability problems". Thesis, Nantes, Ecole des Mines, 2014. http://www.theses.fr/2014EMNA0011/document.
Pełny tekst źródłaWith the emergence of cloud computing and mobile applications, it is possible to find a web service for almost everything. Moreover, developers can create complex applications by combining several independent services, whose arrangement and execution can be automated with the aid of orchestration languages. Nevertheless, the diversity of technologies and the lack of standardization can hinder the collaboration between services. An example of this limitation is the case of photo management with services such as Flickr and Picasa,which not only differ on the way photos are organized, but also in the services they provide. The heterogeneity of the two services leads to interoperability problems, namely adaptation, integration and coordination problems. We propose a framework for helping at the resolution of these issues, in the form of an architecture that integrates different orchestration languages with heterogeneous service providers around a pivot language. As a pivot language we propose an orchestration language based on the chemical programming paradigm. Concretely, this dissertation presents the language Criojo that implements and extends the Heta-calculus, an original calculus associated to a chemical abstract machine dedicated to service-oriented computing. The consequence of adopting this approach would bean improvement in the interoperability of services and orchestration languages, thus easing the development of composite services. The high level of abstraction of Criojo could allow developers to write very concise orchestrations since message exchanges are represented in a natural and intuitive way
Nazer, Rouba Al. "Système de mesure d'impédance électrique embarqué, application aux batteries Li-ion". Thesis, Grenoble, 2014. http://www.theses.fr/2014GRENT007/document.
Pełny tekst źródłaEmbedded electrical impedance measurement is a key issue to enhance battery monitoring and diagnostic in a vehicle. It provides additional measures to those of the pack's current and cell's voltage to enrich the aging's indicators in a first time, and the battery states in a second time. A classical method for battery impedance measurements is the electrochemical impedance spectroscopy (EIS). At each frequency, a sinusoidal signal current (or voltage) of a variable frequency sweeping a range of frequencies of interest is at the input of the battery and the output is the measured voltage response (or current). An active identification technique based on the use of wideband signals composed of square patterns is proposed. Particularly, simulations were used to compare the performance of different excitation signals commonly used for system identification in several domains and to verify the linear and time invariant behavior for the electrochemical element. The evaluation of the estimation performance is performed using a specific quantity: the spectral coherence. This statistical value is used to give a confidence interval for the module and the phase of the estimated impedance. It allows the selection of the frequency range where the battery respects the assumptions imposed by the non-parametric identification method. To experimentally validate the previous results, an electronic test bench was designed. Experimental results are used to evaluate the wideband frequency impedance identification. A reference circuit is first used to evaluate the performance of the used methodology. Experimentations are then done on a Li–ion battery. Comparative tests with EIS are realized. The specifications are established using a simulator of Li-ion battery. They are used to evaluate the performance of the proposed wide band identification method and fix its usefulness for the battery states estimation: the state of charge and the state of health
Lelong, Lionel. "Architecture SoC-FPGA pour la mesure temps réel par traitement d'image. Conception d'un système embarqué : imageur CMOS et Circuit Logique Programmable". Phd thesis, Université Jean Monnet - Saint-Etienne, 2004. http://tel.archives-ouvertes.fr/tel-00374865.
Pełny tekst źródłaAkgul, Bilge Ebru Saglam. "The System-on-a-Chip Lock Cache". Diss., Georgia Institute of Technology, 2004. http://hdl.handle.net/1853/5253.
Pełny tekst źródłaBuitenga, John. "An embedded microcontroller core for SOC applications". Thesis, National Library of Canada = Bibliothèque nationale du Canada, 2000. http://www.collectionscanada.ca/obj/s4/f2/dsk1/tape4/PQDD_0032/MQ65868.pdf.
Pełny tekst źródłaBuitenga, John. "An embedded microcontroller core for SOC applications". Ottawa : National Library of Canada = Bibliothèque nationale du Canada, 2002. http://www.nlc-bnc.ca/obj/s4/f2/dsk1/tape4/PQDD%5F0032/MQ65868.pdf.
Pełny tekst źródłaGopalakrishnan, Harish. "Energy Reduction for Asynchronous Circuits in SoC Applications". Wright State University / OhioLINK, 2011. http://rave.ohiolink.edu/etdc/view?acc_num=wright1324264498.
Pełny tekst źródłaLee, Kyung-Min. "Nanoscale Materials Applications: Thermoelectrical, Biological, and Optical Applications with Nanomanipulation Technology". Thesis, University of North Texas, 2011. https://digital.library.unt.edu/ark:/67531/metadc84238/.
Pełny tekst źródłaJavid, Gelareh. "Contribution à l’estimation de charge et à la gestion optimisée d’une batterie Lithium-ion : application au véhicule électrique". Thesis, Mulhouse, 2021. https://www.learning-center.uha.fr/.
Pełny tekst źródłaThe State Of Charge (SOC) estimation is a significant issue for safe performance and the lifespan of Lithium-ion (Li-ion) batteries, which is used to power the Electric Vehicles (EVs). In this thesis, the accuracy of SOC estimation is investigated using Deep Recurrent Neural Network (DRNN) algorithms. To do this, for a one cell Li-ion battery, three new SOC estimator based on different DRNN algorithms are proposed: a Bidirectional LSTM (BiLSTM) method, Robust Long-Short Term Memory (RoLSTM) algorithm, and a Gated Recurrent Units (GRUs) technique. Using these, one is not dependent on precise battery models and can avoid complicated mathematical methods especially in a battery pack. In addition, these models are able to precisely estimate the SOC at varying temperature. Also, unlike the traditional recursive neural network where content is re-written at each time, these networks can decide on preserving the current memory through the proposed gateways. In such case, it can easily transfer the information over long paths to receive and maintain long-term dependencies. Comparing the results indicates the BiLSTM network has a better performance than the other two. Moreover, the BiLSTM model can work with longer sequences from two direction, the past and the future, without gradient vanishing problem. This feature helps to select a sequence length as much as a discharge period in one drive cycle, and to have more accuracy in the estimation. Also, this model well behaved against the incorrect initial value of SOC. Finally, a new BiLSTM method introduced to estimate the SOC of a pack of batteries in an Ev. IPG Carmaker software was used to collect data and test the model in the simulation. The results showed that the suggested algorithm can provide a good SOC estimation without using any filter in the Battery Management System (BMS)
Vesterlund, Elias. "Reporting application at SDC : A low bandwidth mobile application". Thesis, Mittuniversitetet, Avdelningen för informations- och kommunikationssystem, 2014. http://urn.kb.se/resolve?urn=urn:nbn:se:miun:diva-23402.
Pełny tekst źródłaLemke, Laurent. "Modèles partagés et infrastructures ouverte pour l'internet des objets de la ville Intelligente". Thesis, Université Grenoble Alpes (ComUE), 2017. http://www.theses.fr/2017GREAM022/document.
Pełny tekst źródłaNowadays cities face several challenges and are concerned by ecological, energetic, economical, and demographical aspects. Smart cities, equipped with sensors, actuators, and digital infrastructures, are meant to tackle these issues.Current smart cities are operated by several actors without sharing sensor data or accesses to the actuators. This is a vertical organization, in which each actor deploys its own sensors and actuators, and manages its own digital infrastructure. Each actor may be interested in a different aspect of city management, for instance traffic management, air control, etc. The current trend is a transition towards a more horizontal organization, based on an open and shared mediation platform. In such a platform, sensor data and accesses to actuators can be shared among several actors. The costs related to nfrastructure deployment and management are therefore reduced for each individual actor. This PhD is a contribution to this volution towards horizontal organizations, with open and shared platforms. We propose: (1) an abstraction layer for the ontrol and supervision of the city; (2) a concurrency management mechanism; (3) a coordination mechanism that helps haring actuators; (4) a proof-of-concept implementation of these contributions. The abstraction layer we propose helps users control and supervise a city. It is based upon formal models inspired by the ones used in the programming of reactive systems. They represent the physical elements present in each smart city, with genericity principles. In order to ease application development, the interface of those models is made uniform. Since applications, especially control ones, may ave real-time constraints, we also list the constraints this poses on distributed infrastructures. As soon as actuators are shared, conflicts may occur between users. Our proposals include a concurrency management mechanism, based on eservation principles. We also provide a coordination mechanism for the users to be able to perform several actions in an tomic way.All these principles have been implemented as a proof of concept. We review several use cases, to demonstrate he potential benefits of our proposals
Carter, Geoffrey A. "Controlling precipitation of value added zirconia". Thesis, Curtin University, 2009. http://hdl.handle.net/20.500.11937/1356.
Pełny tekst źródłaDuquesne, Loys. "Caractérisation thermique de structures composites SiCf/SiC tubulaires pour applications nucléaires". Thesis, Paris, ENSAM, 2015. http://www.theses.fr/2015ENAM0052/document.
Pełny tekst źródłaResearches on the development on SiCf/SiC refractory composites for generation IV nuclear fuel cladding led the CEA to focus on the thermal behavior of these materials. In particular, knowingthe thermal properties is essential for their components design. Regarding the development of the sandwich" concept, whose complexity and geometry differ from the conventionally used at tubes,usual measurement methods are unsuitable.This PhD reports on the characterization and modeling of the thermal behavior of these structures. The first part concerns the identification of the global thermal parameters of the diferent layers of a"sandwich" sheath. To do so, a ash method is used and an experimental bench suitable for tubular geometries was developed. A new estimation method based on the combination of both collectedsignals in front and rear faces allows the identification of the thermal diffusivity of tubular composites using infrared thermography. The second part focuses on a virtual material approach, established todescribe the thermal behavior of a "sandwich" cladding, starting from the properties of the elementary components (bers and matrix). These properties, obtained using two different estimation methods,allows exploiting the measurements of two separate experiments based on infrared thermography.They are then used as data for the heat transfer modeling in these ducts. Confrontations betweenexperimental measurements and numerical results finally allow gaining insight into the in uence ofthe different key parameters governing the heat transfer
Linewih, Handoko, i h. linewih@griffith edu au. "Design and Application of SiC Power MOSFET". Griffith University. School of Microelectronic Engineering, 2003. http://www4.gu.edu.au:8080/adt-root/public/adt-QGU20030506.013152.
Pełny tekst źródłaLinewih, Handoko. "Design and Application of SiC Power MOSFET". Thesis, Griffith University, 2003. http://hdl.handle.net/10072/367638.
Pełny tekst źródłaThesis (PhD Doctorate)
Doctor of Philosophy (PhD)
School of Microelectronic Engineering
Full Text
Gustafsson, Johan. "Desktop Integration with a Web Based Application". Thesis, Linköpings universitet, Institutionen för datavetenskap, 2012. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-76913.
Pełny tekst źródłaBerdoyes, Inès. "Interactions entre le silicium liquide et le carbure de silicium, application au composite SiC/SiC". Thesis, Bordeaux, 2018. http://www.theses.fr/2018BORD0113/document.
Pełny tekst źródłaIncrease of the air traffic and recent environmental standards require the reduction of the energy consumption and gas emission of the new aircraft engines. For this purpose, new materials have been developed.Lighter, chemically inert and suitable for high temperature applications, the Ceramic Matrix Composites SiC/SiC are promising materials for replacing some of the metallic turbine engine pieces and improving energy efficiency.From now on, CMC matrix was mainly elaborated by Ceramic Chemical Vapor Infiltration (CVI). However, this process is slow and costly, and the residual porosity is high. Then, the infiltration of liquid silicon (Melt Infiltration) in a SiC fibrous preform, coated with SiC (SiCCVI), and densified by SiC powders (SiCp) is an alternative route to full CVI.Even if liquid silicon (SiL) should fill the pores of the preform without reacting with SiC, local interactions have been noticed between the liquid silicon and the Sic deposit, which is deleterious to the final material mechanical properties. Therefore, this thesis aims at understanding the interactions SiL- SiCCVI and identifying the main parameters. This requires beforehand to characterize deeply and precisely the microstructure of the SiCCVI. Thereafter, research will focus on the control of the SiL- SiCCVI interactions
Register, Joseph. "SiC For Advanced Biological Applications". Scholar Commons, 2014. https://scholarcommons.usf.edu/etd/5113.
Pełny tekst źródłaOsmík, Lukáš. "Integrace pomocí frameworku SwitchYard". Master's thesis, Vysoká škola ekonomická v Praze, 2013. http://www.nusl.cz/ntk/nusl-165085.
Pełny tekst źródłaSolanki, Jigar. "Approche générative conjointe logicielle-matérielle au développement du support protocolaire d’applications réseaux". Thesis, Bordeaux, 2014. http://www.theses.fr/2014BORD0301/document.
Pełny tekst źródłaCommunications between network applications is achieved by using rulesets known as protocols. Protocol messages are managed by the application layer known as the protocol parsing layer or protocol handling layer. Protocol parsers are coded in software, in hardware or based on a co-design approach. They represent the interface between the application logic and the outside world. Thus, they are critical components of network applications. Global performances of network applications are directly linked to the performances of their protocol parser layers.Developping protocol parsers consists of translating protocol specifications, written in a high level language such as ABNF towards low level software or hardware code. As the use of embedded systems is growing, hardware ressources become more and more available to applications on systems on chip (SoC). Nonetheless, developping a network application that uses hardware ressources is challenging, requiring not only expertise in hardware design, but also a knowledge of the protocols involved and an understanding of low-level network programming.This thesis proposes a generative hardware-software co-design based approach to the developpement of network protocol message parsers, to improve their performances without increasing the expertise the developper may need. Our approach is based on a dedicated language, called Zebra, that generates both hardware and software elements that compose protocol parsers. The necessary expertise is deported in the use of the Zebra language and the generated hardware components permit to improve global performances.The contributions of this thesis are as follows : We provide an analysis of network protocols and applications. This analysis allows us to detect the elements which performances can be improved using hardware ressources. We present the domain specific language Zebra to describe protocol handling layers. Software and hardware components are then generated according to Zebra specifications. We have built a SoC running a Linux operating system to assess our approach.We have designed hardware accelerators for different network protocols that are deployed and driven by applications. To increase sharing of parsing units between several tasks, we have developped a middleware that seamlessly manages all the accesses to the hardware components. The Zebra middleware allows several clients to access the ressources of a hardware accelerator. We have conducted several set of experiments in real conditions. We have compared the performances of our approach with the performances of well-knownprotocol handling layers. We observe that protocol handling layers baded on our approach are more efficient that existing approaches
Phan, Hoang-Phuong. "The Piezoresistive Effect of p-type Single Crystalline 3C-SiC for Mechanical Sensors". Thesis, Griffith University, 2016. http://hdl.handle.net/10072/366955.
Pełny tekst źródłaThesis (PhD Doctorate)
Doctor of Philosophy (PhD)
Griffith School of Engineering
Science, Environment, Engineering and Technology
Full Text
Kuszewski, Maciej. "Performance Analysis And Comparison Of Soa Servers In Different Applications". Master's thesis, METU, 2010. http://etd.lib.metu.edu.tr/upload/12612193/index.pdf.
Pełny tekst źródłaDias, Junior José Jorge Lima. "A software architecture process for SOA-based enterprise applications". Universidade Federal de Pernambuco, 2008. https://repositorio.ufpe.br/handle/123456789/1665.
Pełny tekst źródłaO crescimento do tamanho, complexidade e demanda por qualidade dos sistemas de software são alguns dos motivos que tem aumentado o interesse na área de arquitetura de software. Consequentemente, processos de arquitetura de software surgiram a fim de auxiliar os arquitetos na construção dessas arquiteturas. Arquitetura Orientada a Serviços (SOA) surgiu como um tipo de arquitetura de software para construir sistemas através da composição de serviços. Assim como o paradigma de orientação a objetos, o paradigma de orientação a serviços tem trazido uma abordagem de projeto distinta que introduz princípios que governam o posicionamento e o projeto dos componentes arquiteturais. Além disso, SOA é um paradigma para organização e utilização de capacidades distribuídas que podem estar sob o controle de diferentes domínios. No contexto empresarial, SOA permite que organizações, que tenham uma infra-estrutura de aplicações fragmentadas sob a administração de diferentes áreas de negócio, possam integrar estas aplicações no nível de serviço. Por um lado, os processos de arquitetura tradicionais não abrangem estes aspectos de SOA. Por outro lado, as abordagens de SOA disponíveis não satisfazem todos os fundamentos da arquitetura de software. Neste sentido, esta dissertação propõe um processo sistemático de arquitetura de software baseado em SOA que compreende os principais fundamentos da arquitetura de software e características inerentes a SOA a fim de guiar os arquitetos na construção de uma descrição arquitetural para SOA. Adicionalmente, um estudo experimental foi definido, planejado, executado e analisado a fim de avaliar o processo proposto
Hu, Yang. "Study of GdBaCo2-xMxO5+δ (M=Ni, Fe; x = 0, 0.1, 0.2,...) as new cathode materials for IT-SOFC application". Phd thesis, Ecole Centrale Paris, 2011. http://tel.archives-ouvertes.fr/tel-00619609.
Pełny tekst źródłaCamelin, Christian. "Oxydation du silicium monocristallin sous haute pression d'oxygène sec". Bordeaux 1, 1985. http://www.theses.fr/1985BOR10583.
Pełny tekst źródłaMd, Foisal AR. "Optoelectronic effects in 3C-SiC/Si heterostructure and applications". Thesis, Griffith University, 2019. http://hdl.handle.net/10072/385880.
Pełny tekst źródłaThesis (PhD Doctorate)
Doctor of Philosophy (PhD)
School of Eng & Built Env
Science, Environment, Engineering and Technology
Full Text
Bah, Abdramane. "Interopérabilité et sécurité des systèmes d'information : application aux systèmes de gestion de l'éducation". Thesis, Nantes, 2020. http://www.theses.fr/2020NANT4028.
Pełny tekst źródłaAccess control for shared services is an essential requirement for a federation of services from different domains. In this thesis, we tackled two access control problems : authorizing users and delegating user authentication to their own domains. To address these problems, we have proposed a method of authorizing users based on the attribute mapping technique and a federated access control mechanism to implement this authorization method. We have proposed a service federation method to delegate user authentication to their domains. The main objective is to allow various domains to collaborate despite the heterogeneity of their security models
Hinoki, Tatsuya. "Investigation of Mechanical Properties and Microstructure of SiC/SiC Composites for Nuclear Application". Kyoto University, 2001. http://hdl.handle.net/2433/150496.
Pełny tekst źródła0048
新制・課程博士
博士(エネルギー科学)
甲第9050号
エネ博第37号
新制||エネ||10(附属図書館)
UT51-2001-F380
京都大学大学院エネルギー科学研究科エネルギー応用科学専攻
(主査)教授 香山 晃, 教授 塩津 正博, 教授 木村 晃彦
学位規則第4条第1項該当
Pham, Tuan Anh. "Multifunctional silicon carbide nanowires for sensing applications in harsh environments". Thesis, Griffith University, 2022. http://hdl.handle.net/10072/414588.
Pełny tekst źródłaThesis (PhD Doctorate)
Doctor of Philosophy (PhD)
School of Environment and Sc
Science, Environment, Engineering and Technology
Full Text
Rich, David. "On-site application of self-compacting concrete (SCC)". Thesis, Loughborough University, 2014. https://dspace.lboro.ac.uk/2134/17229.
Pełny tekst źródłaWahid, Mohamad H. B. A. "Application of SOA-NOLM in all-optical processing". Thesis, Aston University, 2009. http://publications.aston.ac.uk/15403/.
Pełny tekst źródłaUdroiu, Sorina-Nicoleta. "Développement de piles à combustible de type SOFC en technologie planaire couches épaisses. Application à l'étude de dispositifs en configuration monochambre". Phd thesis, Ecole Nationale Supérieure des Mines de Saint-Etienne, 2009. http://tel.archives-ouvertes.fr/tel-00392071.
Pełny tekst źródłaDans cette étude, les électrodes ont été déposées en couches épaisses par la technologie de sérigraphie sur des pastilles support d'électrolyte. Au niveau matériaux, des électrolytes à base de cérine (en particulier GDC et SDC) ont été utilisés afin de diminuer la température de fonctionnement des piles de type SOFC (par rapport à celles avec un électrolyte YSZ). Des électrodes à propriétés catalytiques bien spécifiques vis à vis du mélange gazeux, ont été aussi étudiés : cermets Ni - GDC ou Ni - SDC pour l'anode, cathodes à base de LSM, BSCF ou SSC. Les poudres initiales ainsi que les couches sérigraphiées ont été caractérisées (analyse de phase, microstructure, stabilité chimique, conductivité électrique...) par diverses méthodes physico-chimiques. Différentes piles ont été élaborées et testées dans un réacteur monochambre sous des mélanges air-propane. L'influence des conditions gazeuses (débit, composition) ainsi que de la température de fonctionnement sur les performances des piles a été étudiée. Compte tenu de nos conditions de test, les performances se sont avérées relativement modestes (densité de puissance maximale de l'ordre de 12 mW.cm-2). Néanmoins, cette étude confirme la validité du concept des piles SOFC monochambres, et a aussi permis de développer un savoir-faire au niveau du laboratoire pour poursuivre les études sur cette thématique.
Jons, Mattias. "Doped 3C-SiC Towards Solar Cell Applications". Thesis, Linköpings universitet, Halvledarmaterial, 2018. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-148595.
Pełny tekst źródłaSingh, Sherjang. "SiC-C Composite Microelectrode for Biomedical Applications". University of Cincinnati / OhioLINK, 2007. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1170556512.
Pełny tekst źródłaŠtúň, Jaroslav. "Návrh a implementace podnikového intranetového systému". Master's thesis, Vysoké učení technické v Brně. Fakulta podnikatelská, 2008. http://www.nusl.cz/ntk/nusl-221815.
Pełny tekst źródłaStackler, Caroline. "Transformateurs électroniques pour applications ferroviaires". Thesis, Toulouse, INPT, 2019. http://www.theses.fr/2019INPT0015.
Pełny tekst źródłaCurrent on-board converters, running on AC catenaries, are mainly composed by a low frequency transformer, then rectifiers, supplying traction motors through three-phase inverters. Due to volume and mass constraints on the converter, the efficiency of the transformer is limited. Moreover, this transformer is quite bulky and heavy. Thanks to the development of high voltage and high power semiconductors, such as Si IGBTs or SiC MOSFETs, and of medium frequency transformer, i.e. operating at a few kilohertz, new topologies of on-board converters, named Power Electronic Traction Transformer (PETT), are studied. Though several structures have been studied in the literature, they have never been compared. The main objective of this thesis is, thus, to develop a methodology to size PETT topologies, in order to compare them. In the first chapter, a state of the art of the PETT structures proposed in literature is presented. The second chapter is dedicated to the comparison of indirect topologies. A methodology, optimising the sizing of each structure to maximise its efficiency under mass and volume constraints, is developed. It is applied on topologies using SiC MOSFETs, contrary to Si IGBT structures developed in the literature. The magnetizing inductance is also considered to insure soft switching and reduce the losses. In the third chapter, an novel active filter, included in the DC-DCs of the converter, is proposed. The aim is to reduce the volume of the filtering capacitors on the intermediate buses, and thus, of the entire converter, without impacting the intrinsic reliability of the converter. Its impact on the losses of the DC-DC is studied. The last chapter deals with the interactions between the on-board converter and the infrastructure. Thus, the 25 kV-50 Hz railway network is modeled. It includes a novel circuit, modelling the skin effect in the catenary. Some resonances, dependant on the sector geometry and the train position, are highlighted in the impedance seen by a train. Moreover, the models are implemented in a numerical simulator to supply a small scale mock-up of a PETT. PHIL tests have, a priori, never been carried on a PETT. A conclusion and some perspectives of future work close thisdissertation
Preißler, Steffen. "Skalierbare Ausführung von Prozessanwendungen in dienstorientierten Umgebungen". Doctoral thesis, Saechsische Landesbibliothek- Staats- und Universitaetsbibliothek Dresden, 2012. http://nbn-resolving.de/urn:nbn:de:bsz:14-qucosa-99727.
Pełny tekst źródłaVanSant, April Nelson. "Studies on Hydrogen-Pinch Analysis and Application of COSMO-SAC to Electrolytes". Thesis, Virginia Tech, 2008. http://hdl.handle.net/10919/34828.
Pełny tekst źródłaMaster of Science
Liu, Chih-Feng, i 劉智. "Programmable Arbiter Design for SoC Application". Thesis, 2004. http://ndltd.ncl.edu.tw/handle/31696095258507373392.
Pełny tekst źródła義守大學
電子工程學系
92
In order to obtain high bandwidth utilization and low latency for on-chip bus communication, a hybrid arbitration algorithm and a programmable arbiter architecture are described in this thesis. The hybrid arbitration algorithm contains static fixed priority algorithm in conjunction with dynamic algorithm to gain low latency in system performance is explained. The implementation of a programmable arbiter to increase the bandwidth utilization is proposed. The analysis of various combinations of the arbitration algorithms indicates a better performance can be achieved as compared with the traditional arbitration assignment scheme. The simulation results of the programmable arbiter are shown on Altera Max Plus II design environment and implementation in Altera EPF10K100ARC240-1 FPGA and verified in ARM AMBA University Kit (AUK) environment.
Yang, Yu-Chun, i 楊寓鈞. "FPGA Implementation of Biomedical Application SoC". Thesis, 2009. http://ndltd.ncl.edu.tw/handle/39493766290766325590.
Pełny tekst źródła國立交通大學
電機與控制工程系所
97
In the study of biomedical electronics nowadays, processing and analyzing masses of physiological signals in time is a critical issue in real world. In the past, electronic treatment and analysis instruments are very expansive and large. Therefore, the requirement of portable and embedded biomedical electronic product is growing rapidly. Based on these two reasons, this thesis presents a system-on-chip (SoC) design for biomedical applications to provide the integration of systematic resources. In this thesis, the SOC design for biomedical signal processing is presented. It has the following features. (1) The ability of programmable monitoring and analyzing biomedical signals. (2) The flexibility for further hardware extension. The SoC design is composed of a programmable CPU, biomedical signal processing (BSP) units, system bus, communication, and display interface. The programmable CPU manages the process schedule and I/O control. The BSP unit is treated as digital signal processing (DSP) cores which can separate and analyze physiological signals. The system bus makes it flexible to add or to remove DSP IPs. By experimental results, the proposed design implemented on FPGA can achieve real-time analysis and waveform displays under at 100 MHz. Comparison with other high-speed DSP processors, the system presents some optimization such as less execution cycles, lower power consumption, use of fewer PCB area. Finally, the SoC design is demonstrated in this thesis with the Altera DE2 development board. The whole design is consisted of 29,640 logic elements.
Yu-kuang, Lien. "Application-Aware On-Chip Networking System Design for SoC Applications". 2006. http://www.cetd.com.tw/ec/thesisdetail.aspx?etdun=U0001-2606200617213900.
Pełny tekst źródłaLien, Yu-kuang, i 連育廣. "Application-Aware On-Chip Networking System Design for SoC Applications". Thesis, 2006. http://ndltd.ncl.edu.tw/handle/48854309733743991887.
Pełny tekst źródła國立臺灣大學
電子工程學研究所
94
As the complexity of SoC systems is increasing, it is hard to interconnect a variety of IPs. OCN (On-Chip Networking) system is a new method to solve the chip communication problems. Based upon pre-defined components and architecture, we can build a high performance and reliable communication environment. Currently, OCN system adopts simple or fixed architectures, such as star and mesh. However, these architectures may cause inefficient bandwidth usage and high hardware cost. Therefore, analytical decision and performance evaluation for OCN system are important issues before implementation. The goal of this thesis is to map SoC to OCN and optimize the hardware cost. We propose an application-aware design flow and approaches, called AMAP. Due to the differences between SoC Applications, we analyze the requirements of SoC applications. In view of that deciding the location of each IP on OCN system is very important, we propose binomial mapping algorithm to get a fast and efficient 2D-mesh topology. According to the traffic load after mapping, we propose several approaches to optimize the hardware cost and improve the OCN utilization. By using the proposed binomial mapping algorithm, we can save 37% traffic load and 46% Hop. Moreover, we can save 75~87.5% hardware cost by the optimization approaches under bandwidth constraints. Furthermore, the OCN architecture is successfully verified on established infrastructure, CoWare ConvergenSC and FPGA platform.
MITTAL, PULKIT. "BUS CONTROLLED AMBA 2.0 AHB2APB BRIDGE FOR SOC APPLICATION". Thesis, 2022. http://dspace.dtu.ac.in:8080/jspui/handle/repository/19122.
Pełny tekst źródłaDer-WeiYang i 楊得煒. "Advanced Architecture and Application Development of Video SoC". Thesis, 2015. http://ndltd.ncl.edu.tw/handle/qt8b76.
Pełny tekst źródłaChang, Shao-Pin, i 張紹斌. "Design of LCD Driver IP for SOC Application". Thesis, 2004. http://ndltd.ncl.edu.tw/handle/42397719932832050845.
Pełny tekst źródła義守大學
電子工程學系
92
In this thesis, we proposed a Memory Map LCD driver IP design based on the conventional B-type driving method. In the proposed LCD driver IP architecture, the display data RAM is improved as memory array composed of 4 banks which allows the central processor can access the other memory banks even the display is progressing, then the use of bus become more flexible. The methodology to integrate the proposed LCD driver IP in System-On-Chip (SOC) as an AMBA AHB slave component is also described. In order to communicate with the Example AMBA System (EASY) which is based on ARM922T processor, an AMBA AHB slave wrapper is designed for the proposed LCD driver. The stand alone LCD driver IP is simulated and verified in ISE environment. The embedded LCD driver IP is also simulated by running the ARM922T Design Sign-off Model (DSM) in EASY system. The results indicate that the proposed LCD driver IP is capable for SOC applications as in AMBA system.
Chiu, Tzu-Yao, i 邱子耀. "Image Enhancement Application Implemented on an All Programmable SoC Platform". Thesis, 2018. http://ndltd.ncl.edu.tw/handle/ctu6pk.
Pełny tekst źródła國立臺灣科技大學
電子工程系
106
There are many kinds of image/vision devices surrounding us, includes environment / crowd surveillance and monitoring, real-time imaging record of personal mobile devices, or around-view system of vehicles, etc... How to perform vision display, video data storage, subject recognition and video processing functions? This is the design concept of smart vision systems. For the hardware architecture design of smart vision system, we need optical devices such as video cameras, light sensors and optical transceivers/receivers. We also need a high-performance processor platform for image format transformation, data analysis and calculation. It requests algorithms for such tasks. Xilinx Zynq SoC (System on Chip) platform is suitable for high-performance requests of smart vision systems. It contains ARM Cortex A9 dual-core processor, 29K to 85K LUTs (Look-Up-Table) logic units, support high-performance processing ability and many kinds of video/data interfaces. And we can implement embedded design blocks or control units in FPGA (Field Programmable Gate Array) to achieve high-flexibility design requirements. We discussed how to migirate the image enhancement application program to all programmable SoC platform in this paper. I selected SVDK (Smart Vision Development Kit) for hardware development platform and Xilinx Vivado tool for software developing environment. First, we integrated the image enhancement IP into Zynq platform, and then go to capture image data from the high-resolution camera. Then we can do image pre-processing progress in Zynq platform. We learned how to get different performances through different image processing progresses/algorithms. In the end, we summarized the user experience and the conclusion.