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Artykuły w czasopismach na temat "SOC APPLICATION"
Wang, Da Wei, i Si Kun Li. "Application Specific Architecture Template Reuse for SoC Transaction Level Modeling". Applied Mechanics and Materials 198-199 (wrzesień 2012): 911–16. http://dx.doi.org/10.4028/www.scientific.net/amm.198-199.911.
Pełny tekst źródłaWang, Qiuju, Xin Liu, Jingyang Li, Xiaoyu Yang i Zhenhua Guo. "Straw application and soil organic carbon change: A meta-analysis". Soil and Water Research 16, No. 2 (9.04.2021): 112–20. http://dx.doi.org/10.17221/155/2020-swr.
Pełny tekst źródłaWei, Meng, Aijun Zhang, Zhonghou Tang, Peng Zhao, Hong Pan, Hui Wang, Quangang Yang, Yanhong Lou i Yuping Zhuge. "Active carbon pool-size is enhanced by long-term manure application". Plant, Soil and Environment 66, No. 11 (2.11.2020): 598–605. http://dx.doi.org/10.17221/426/2020-pse.
Pełny tekst źródłaMiller, J. J., M. L. Owen, X. Hao, X. M. Yang, C. F. Drury i D. S. Chanasyk. "Influence of continuous application of feedlot manure and legacy treatments on soil organic carbon, soil hydrophobicity, and soil water repellency". Canadian Journal of Soil Science 101, nr 3 (1.09.2021): 439–51. http://dx.doi.org/10.1139/cjss-2020-0074.
Pełny tekst źródłaXu, Gang, Jiawei Song, Yang Zhang i Yingchun Lv. "Effects of biochar application on soil organic carbon mineralization during drying and rewetting cycles". BioResources 14, nr 4 (31.10.2019): 9957–67. http://dx.doi.org/10.15376/biores.14.4.9957-9967.
Pełny tekst źródłaBarančíková, G., J. Halás, M. Gutteková, J. Makovníková, M. Nováková, R. Skalský i Z. Tarasovičová. "Application of RothC model to predict soil organic carbon stock on agricultural soils of Slovakia". Soil and Water Research 5, No. 1 (26.02.2010): 1–9. http://dx.doi.org/10.17221/23/2009-swr.
Pełny tekst źródłaGross, Arthur, Tobias Bromm i Bruno Glaser. "Soil Organic Carbon Sequestration after Biochar Application: A Global Meta-Analysis". Agronomy 11, nr 12 (5.12.2021): 2474. http://dx.doi.org/10.3390/agronomy11122474.
Pełny tekst źródłaQiu, Husen, Zhuangzhuang Hu, Jieyun Liu, Haiyang Zhang i Weiliang Shen. "Effect of Biochar on Labile Organic Carbon Fractions and Soil Carbon Pool Management Index". Agronomy 13, nr 5 (17.05.2023): 1385. http://dx.doi.org/10.3390/agronomy13051385.
Pełny tekst źródłaYan, Y., H. He, X. Zhang, Y. Chen, H. Xie, Z. Bai, P. Zhu, J. Ren i L. Wang. "Long-term fertilization effects on carbon and nitrogen in particle-size fractions of a Chinese Mollisol". Canadian Journal of Soil Science 92, nr 3 (marzec 2012): 509–19. http://dx.doi.org/10.4141/cjss2010-004.
Pełny tekst źródłaZuo, Wengang, Lu Xu, Meihua Qiu, Siqiang Yi, Yimin Wang, Chao Shen, Yilin Zhao i in. "Effects of Different Exogenous Organic Materials on Improving Soil Fertility in Coastal Saline-Alkali Soil". Agronomy 13, nr 1 (24.12.2022): 61. http://dx.doi.org/10.3390/agronomy13010061.
Pełny tekst źródłaRozprawy doktorskie na temat "SOC APPLICATION"
Portero, Trujillo Antoni. "Design Space Exploration of heterogeneous SoC Platforms for a Data-Dominant Application". Doctoral thesis, Universitat Autònoma de Barcelona, 2009. http://hdl.handle.net/10803/5365.
Pełny tekst źródłaPara este propósito, se ha elegido SystemC/C++ como lenguaje de descripción del sistema e idear los diferentes flujos de implementación para las diferentes arquitecturas y plataformas de silicio. Este poderoso marco de trabajo permite comparar implementaciones de una forma objetiva y razonada. Ya que nuestros resultados vienen de un αnico modelo y los diseños fueron mapeados en la misma tecnología de silicio (90nm CMOS).
El resultado de este trabajo de investigación es un juego de criterios y un mapa de las soluciones disponibles sobre el espacio de funcionamiento más bien que una aserción que dice que una solución αnica es mejor que las otras. Mi intención ha sido desarrollar técnicas y formular los métodos que pueden permitir aumentar la productividad en el diseño.
Este desarrollo puede ser extendido al nuevo paradigma de intercomunicación: Aquellos que usan técnicas DVFS y basadas en NoC para exploraciones e implementaciones MPSoC.
Consideramos la contribución mas significativa es el desarrollo del modelo con el cual se han realizado los diversos experimentos: El compresor MPEG que se ha realizado en SystemC/C++. Se ha realizado de la forma que implementaciones mαltiples son posibles: que van desde una parte grande en HW hasta la que se carga en un VLIW. En el caso de la FPGA y el ASIC, se han realizado dos implementaciones. Hemos obtenido un conjunto de resultados para siete diferentes implementaciones con cuatro diferentes objetivos HW (FPGA, ASIC, DSP y ASIP) con diferentes arquitecturas internas, seleccionadas para obtener puntos óptimos. Esto nos da que un incremento en eficiencia del 56 % para velocidad versus 26 % en energía en la solución FSME (20% para velocidad y 57 % para energía en la solución FAST). En el caso de los ISPs, las mejoras en el código se han realizado de forma que se obtienen implementaciones mejores que las que se conseguirían con una implementación directa del código no solo mejoras en el código sino mejoras en las microarquitecturas de silicio que forman el VLIW en el caso del ASIP. Otra contribución ha sido la realización de una NoC a nivel funcional en SystemC.
The main goal of this thesis is to obtain a set of results for the implementation of a given system level application down to different architectural platforms. This allowed carrying out a fair comparison that includes to build the whole system and to complete the design chain to the diverse silicon targets. This comparison uses four variables for its evaluation (execution time, chip area, energy consumption and design time) and produces a map of different optimal implementation points according to a given set or operating requirements. I built a complete MPEG-4 MP. This standard is a well known reference example, pretty popular in the scientific literature and this compressor is also a fine example of data-flow application. Therefore, results extracted from this thesis can be extended to other data-flow applications. I considered necessary to compute image compression with real-time constraints. Hence, I would like to dispose of the most flexible design possible in order to map the same specification into the different platforms.
For that purpose, I chose SystemC/C++ as description system level language and setup the different implementation flows for the different architectural and silicon platforms. This powerful framework allows comparing implementations in a reasonably objective way. Since our results come from a unique reference model and all designs were finally mapped in the same silicon technology (90nm CMOS).
The result of this research work is a set of criteria and a map of the available solutions on the performance space rather than an assertion saying that a unique solution is better than others. My intention has been to develop techniques and formulate methods that increased design productivity. This development can be further applied to the new parading of implementations: those that use DVFS techniques and NoC-based MPSoc implementation explorations.
We consider the most important contribution is the development of the model able to achieve the different experiments: the MPEG compressor that has been realized in SystemC/C ++. It is designed in a way that multiple implementations are possible, ranging from a large part in HW up to loaded in an accelerator as a VLIW. In case of the FPGA and ASIC, two implementations have been carried out. We obtained a set of values for seven different implementations targeting four different HW platforms (FPGA, ASIC, DSP and ASIP) with diverse internal architectures, selected to get optimal points. In the case of ASIC, we managed to end up with the layouts of the two solutions. This led to an increase in efficiency of 56 % for speed versus 26 % for energy (in FSME solution 20% for speed and 57% for energy in FAST solution). In case of the ISPs, code improvements have been accomplished to come up to more ideal solutions with regard to those who would be obtained by a direct implementation. In case of the ASIP the improvements have not only been realized in the code but also in the silicon micro architecture that form the VLIW. Other contribution is the accomplishment of a functional NoC in SystemC.
Rouxel, Samuel. "Modélisation et Caractérisation d'une Plate-Forme SOC Hétérogène : Application à la Radio Logicielle". Phd thesis, Université de Bretagne Sud, 2006. http://tel.archives-ouvertes.fr/tel-00124433.
Pełny tekst źródłaUne chaîne UMTS a permis la validation de l'outil réalisé, en confrontant les résultats estimés de l'outil, à ceux mesurés sur une plate-forme temps réel hétérogène (multi-DSP, multi-FPGA). Une partie du travail s'est concentré sur l'identification des composants utiles à la conception des systèmes SoC, et de leurs caractéristiques, en adéquation avec le niveau d'abstraction considéré. Une autre partie des travaux a porté sur la définition des modèles UML, et donc du profil, qui définissent la sémantique des différents composants identifiés en fonction de la configuration (PIM, PSM), ainsi que leurs relations. Une réflexion a été nécessaire afin d'élaborer les diverses règles de vérification et modèles d'exécution qui permettent d'informer le concepteur de ses erreurs et de la faisabilité du système modélisé. Un modèle de système d'exploitation a également été inclus, enrichissant la liste des éléments (composants) déjà définis et démontrant l'extensibilité du profil.
Rouxel, Samuel. "Modélisation et caractérisation de plates-formes SoC hétérogènes : application à la radio logicielle". Lorient, 2006. http://www.theses.fr/2006LORIS077.
Pełny tekst źródłaThe work of this PhD has been carried out within the framework of the A3S project and relies on component aspects integrated within a SoC platform design methodology, which is based on the UML language. This methodology proposes a high-level design framework based on the A3S UML profile developed to provide real-time embedded system semantic especially in SDR domain. An MDA approach has been considered to deal with different abstraction levels when specifying systems. First part of the work focused on identifying the component required designing a SoC system, and their characteristics depending on the component abstraction levels. Several types of component (software and hardware) whose characteristics depend on their modelling (PIM or PSM models) have been considered. Second part of the work focused on the definition of UML metamodels, which are grouped to define the A3S UML profile that establish the semantic of identified components depending on their modelling and their relations. We have defined extensive verification rules and applied a model of computation to inform designers about errors that have been done and to ensure the feasibility of their systems. Finally an operating system model has been included to demonstrate the scalability and the extension mechanisms of the UML language and profile which improve the list of components that have been already integrated within our framework. An UMTS application has validated our approach by comparing the estimated results computed by the tool with measured results obtained on a heterogeneous real-time platform (with several DSP and FPGA)
Zedek, Sabeha Fettouma. "Intégration d'architectures mixtes reconfigurables : Application à la détection de défauts dans des structures hétérogènes". Thesis, Toulouse, INSA, 2015. http://www.theses.fr/2015ISAT0005/document.
Pełny tekst źródłaScientific activities described in this PhD thesis are part of the theme of smart environment, strategy axes of ADREAM with the LAAS-CNRS. Since several years, our research team (N2IS) had a field of interest in SHM (Structural Health Monitoring) with the objective of doing a smart diagnostic on different heterogeneous structures. Indeed, the maturity of innovative materials such as composites triggering interest among aircraft manufacturers, or even the use of materials like concrete structures of civil engineering, all those heterogeneous structures that require periodic monitoring and / or continuous one. This is to detect cracks, disbond, surface corrosion or even delamination. To do this, existing solutions usually rely on technologies of nondestructive testing (NDT) that incorporate mostly sensor networks low-power systems interfaced with analysis of signals. These approaches have significant functional limitations: they are not versatile and do not allow for continuity of service in a "degraded" when operating on battery power with a minimum level of energy mode. Our research is a view related to the quantization level of robustness of a heterogeneous structure. Its aim is the development and integration of hardware reconfigurable mixed (A / D ) systems. After an investigation of the main technological solutions reprogrammable hardware and given the problems associated with developments in analytical embedded and minimizing the energy consumption of sensor algorithms. The choice was based on technologies like FPAA and FPGA. Initially our research studies have focused on the study of reconfigurable analog hardware analog. The objective was to show a conceptual feasibility of integrating a complex conditioning system (implementation of a synchronous detection technique), considering the tradeoff between a decision on the fly reconfiguration and a rational energy management system. Therefore, the question of how to integrate and store data necessary for the development of an efficient digital processing. A solution based on a hybrid approach with a chip produced by Xilinx called Zynq and embedded on a Zedboard. This solution is more efficient than a PSoC approach and allowed the development and implementation of signal processing techniques with tools for optimization and provided a solution of self-generation code trough a graphic interface. Following this research, the results obtained demonstrate the validity of the concepts implemented and allow us to imagine the next smart generation architectures
Lacouture, Mayleen. "A chemical programming language for orchestrating services : Application to interoperability problems". Thesis, Nantes, Ecole des Mines, 2014. http://www.theses.fr/2014EMNA0011/document.
Pełny tekst źródłaWith the emergence of cloud computing and mobile applications, it is possible to find a web service for almost everything. Moreover, developers can create complex applications by combining several independent services, whose arrangement and execution can be automated with the aid of orchestration languages. Nevertheless, the diversity of technologies and the lack of standardization can hinder the collaboration between services. An example of this limitation is the case of photo management with services such as Flickr and Picasa,which not only differ on the way photos are organized, but also in the services they provide. The heterogeneity of the two services leads to interoperability problems, namely adaptation, integration and coordination problems. We propose a framework for helping at the resolution of these issues, in the form of an architecture that integrates different orchestration languages with heterogeneous service providers around a pivot language. As a pivot language we propose an orchestration language based on the chemical programming paradigm. Concretely, this dissertation presents the language Criojo that implements and extends the Heta-calculus, an original calculus associated to a chemical abstract machine dedicated to service-oriented computing. The consequence of adopting this approach would bean improvement in the interoperability of services and orchestration languages, thus easing the development of composite services. The high level of abstraction of Criojo could allow developers to write very concise orchestrations since message exchanges are represented in a natural and intuitive way
Nazer, Rouba Al. "Système de mesure d'impédance électrique embarqué, application aux batteries Li-ion". Thesis, Grenoble, 2014. http://www.theses.fr/2014GRENT007/document.
Pełny tekst źródłaEmbedded electrical impedance measurement is a key issue to enhance battery monitoring and diagnostic in a vehicle. It provides additional measures to those of the pack's current and cell's voltage to enrich the aging's indicators in a first time, and the battery states in a second time. A classical method for battery impedance measurements is the electrochemical impedance spectroscopy (EIS). At each frequency, a sinusoidal signal current (or voltage) of a variable frequency sweeping a range of frequencies of interest is at the input of the battery and the output is the measured voltage response (or current). An active identification technique based on the use of wideband signals composed of square patterns is proposed. Particularly, simulations were used to compare the performance of different excitation signals commonly used for system identification in several domains and to verify the linear and time invariant behavior for the electrochemical element. The evaluation of the estimation performance is performed using a specific quantity: the spectral coherence. This statistical value is used to give a confidence interval for the module and the phase of the estimated impedance. It allows the selection of the frequency range where the battery respects the assumptions imposed by the non-parametric identification method. To experimentally validate the previous results, an electronic test bench was designed. Experimental results are used to evaluate the wideband frequency impedance identification. A reference circuit is first used to evaluate the performance of the used methodology. Experimentations are then done on a Li–ion battery. Comparative tests with EIS are realized. The specifications are established using a simulator of Li-ion battery. They are used to evaluate the performance of the proposed wide band identification method and fix its usefulness for the battery states estimation: the state of charge and the state of health
Lelong, Lionel. "Architecture SoC-FPGA pour la mesure temps réel par traitement d'image. Conception d'un système embarqué : imageur CMOS et Circuit Logique Programmable". Phd thesis, Université Jean Monnet - Saint-Etienne, 2004. http://tel.archives-ouvertes.fr/tel-00374865.
Pełny tekst źródłaAkgul, Bilge Ebru Saglam. "The System-on-a-Chip Lock Cache". Diss., Georgia Institute of Technology, 2004. http://hdl.handle.net/1853/5253.
Pełny tekst źródłaBuitenga, John. "An embedded microcontroller core for SOC applications". Thesis, National Library of Canada = Bibliothèque nationale du Canada, 2000. http://www.collectionscanada.ca/obj/s4/f2/dsk1/tape4/PQDD_0032/MQ65868.pdf.
Pełny tekst źródłaBuitenga, John. "An embedded microcontroller core for SOC applications". Ottawa : National Library of Canada = Bibliothèque nationale du Canada, 2002. http://www.nlc-bnc.ca/obj/s4/f2/dsk1/tape4/PQDD%5F0032/MQ65868.pdf.
Pełny tekst źródłaKsiążki na temat "SOC APPLICATION"
Yŏnʼguwŏn, Hanʼguk Chŏnja Tʻongsin, red. Onchʻip netʻŭwŏkʻŭ kiban SoC platform kaebal =: SoC platform development based on on-chip network. [Seoul]: Chŏngbo Tʻongsinbu, 2008.
Znajdź pełny tekst źródłaYŏnʼguwŏn, Hanʼguk Chŏnja Tʻongsin, red. Onchʻip netʻŭwŏkʻŭ kiban SoC platform kaebal =: SoC platform development based on on-chip network. [Seoul]: Chŏngbo Tʻongsinbu, 2008.
Znajdź pełny tekst źródłaIEEE International ASIC Conference and Exhibit (12th 1999 Washington, DC). Twelfth Annual IEEE International ASIC/SOC Conference: Proceedings : September 15-18, 1999, DoubleTree Hotel National Airport, Washington, DC. Redaktorzy Büchner Th, Krishnamurthy Ram K, Sridhar Ramalingam, IEEE Solid-State Circuits Society i Institute of Electrical and Electronics Engineers. Rochester Section. Piscataway, New Jersey: IEEE, 1999.
Znajdź pełny tekst źródłaIEEE International ASIC Conference and Exhibit (13th 2000 Arlington, Virginia). 13th Annual IEEE International ASIC/SOC Conference: Proceedings : September 13-16, 2000, Hyatt Regency Crystal City, Arlington, VA. Redaktorzy Büchner Th, Carothers Jo Dale, Krishnamurthy Ram K, IEEE Circuits and Systems Society. i Institute of Electrical and Electronics Engineers. Rochester Section. Piscataway, New Jersey: IEEE, 2000.
Znajdź pełny tekst źródłaIEEE International ASIC/SOC Conference (14th 2001 Arlington, Va.). 14th Annual IEEE International ASIC/SOC Conference: Proceedings : September 12-15, 2001, Hyatt Regency Crystal City, Arlington, VA. Redaktorzy Mukund P. R, Chickanosky John, Krishnamurthy Ram K i IEEE Circuits and Systems Society. Piscataway, N.J: IEEE, 2001.
Znajdź pełny tekst źródłaIEEE International ASIC/SOC Conference (15th 2002 Rochester, N.Y.). 15th Annual IEEE International ASIC/SOC Conference: Proceedings : September 25-28, 2002, RIT Inn and Conference Center, Rochester, NY. Redaktorzy Mukund P. R, Chickanosky John, Krishnamurthy Ram K i IEEE Circuits and Systems Society. Piscataway, N.J: IEEE, 2002.
Znajdź pełny tekst źródłaChang, Henry. Surviving the SOC revolution: A guide to platform-based design. New York: Kluwer Academic, 2002.
Znajdź pełny tekst źródłaHenry, Chang, red. Surviving the SOC revolution: A guide to platform-based design. Boston: Kluwer Academic, 1999.
Znajdź pełny tekst źródłaChonlameth, Arpnikanondt, red. A platform-centric approach to system-on-chip (SoC) design. New York: Springer, 2005.
Znajdź pełny tekst źródłaMadisetti, V. A platform-centric approach to system-on-chip (SOC) design. New York: Springer, 2010.
Znajdź pełny tekst źródłaCzęści książek na temat "SOC APPLICATION"
Chakravarthi, Veena S., i Shivananda R. Koteshwar. "Application-specific SOCs". W System on Chip (SOC) Architecture, 49–63. Cham: Springer Nature Switzerland, 2023. http://dx.doi.org/10.1007/978-3-031-36242-2_4.
Pełny tekst źródłaWang, Zhihua, Hanjun Jiang i Hong Chen. "SoC Design and Application Systems". W CMOS IC Design for Wireless Medical and Health Care, 163–84. New York, NY: Springer New York, 2013. http://dx.doi.org/10.1007/978-1-4614-9503-1_6.
Pełny tekst źródłaKhan, Gul N., i Masoud O. Gharan. "Application Specific Reconfigurable SoC Interconnection Network Architecture". W Architecture of Computing Systems – ARCS 2019, 322–33. Cham: Springer International Publishing, 2019. http://dx.doi.org/10.1007/978-3-030-18656-2_24.
Pełny tekst źródłaHolland, Mark, i Scott Hauck. "Automatic Creation of Reconfigurable PALs/PLAs for SoC". W Field Programmable Logic and Application, 536–45. Berlin, Heidelberg: Springer Berlin Heidelberg, 2004. http://dx.doi.org/10.1007/978-3-540-30117-2_55.
Pełny tekst źródłaSegard, Arthur, i François Verdier. "SOC and RTOS: Managing IPs and Tasks Communications". W Field Programmable Logic and Application, 710–18. Berlin, Heidelberg: Springer Berlin Heidelberg, 2004. http://dx.doi.org/10.1007/978-3-540-30117-2_72.
Pełny tekst źródłaGriese, Björn, Erik Vonnahme, Mario Porrmann i Ulrich Rückert. "Hardware Support for Dynamic Reconfiguration in Reconfigurable SoC Architectures". W Field Programmable Logic and Application, 842–46. Berlin, Heidelberg: Springer Berlin Heidelberg, 2004. http://dx.doi.org/10.1007/978-3-540-30117-2_86.
Pełny tekst źródłaTang, Zhiwei. "The Zynq-7000 SoC on UltraScale Architecture". W Application of Intelligent Systems in Multi-modal Information Analytics, 231–36. Cham: Springer International Publishing, 2020. http://dx.doi.org/10.1007/978-3-030-51556-0_34.
Pełny tekst źródłaBailey, Brian, i Grant Martin. "IP Meta-Models for SoC Assembly and HW/SW Interfaces". W ESL Models and their Application, 33–82. Boston, MA: Springer US, 2009. http://dx.doi.org/10.1007/978-1-4419-0965-7_2.
Pełny tekst źródłaBigot, A., F. Charpentier, H. Krupnova i I. Sans. "Deploying Hardware Platforms for SoC Validation: An Industrial Case Study". W Field Programmable Logic and Application, 64–73. Berlin, Heidelberg: Springer Berlin Heidelberg, 2004. http://dx.doi.org/10.1007/978-3-540-30117-2_9.
Pełny tekst źródłaVaandrager, Lenneke, i Lynne Kennedy. "The Application of Salutogenesis in Communities and Neighborhoods". W The Handbook of Salutogenesis, 349–59. Cham: Springer International Publishing, 2022. http://dx.doi.org/10.1007/978-3-030-79515-3_33.
Pełny tekst źródłaStreszczenia konferencji na temat "SOC APPLICATION"
Becker, Juergen. "Application specific SoC designs". W 2016 29th IEEE International System-on-Chip Conference (SOCC). IEEE, 2016. http://dx.doi.org/10.1109/socc.2016.7905438.
Pełny tekst źródłaLatif, Khalid, Moazzam Niazi, Hannu Tenhunen, Tiberiu Seceleanu i Sakir Sezer. "Application development flow for on-chip distributed architectures". W 2008 IEEE International SOC Conference (SOCC). IEEE, 2008. http://dx.doi.org/10.1109/socc.2008.4641503.
Pełny tekst źródłaWu, Tung-Yeh, Sriram Sambamurthy i Jacob A. Abraham. "Estimation of maximum application-level power supply noise". W 2010 IEEE International SOC Conference (SOCC). IEEE, 2010. http://dx.doi.org/10.1109/socc.2010.5784738.
Pełny tekst źródłaHsu, Chun F., Mong-Kai Ku i Li-Yen Liu. "Support vector machine FPGA implementation for video shot boundary detection application". W 2009 IEEE International SOC Conference (SOCC). IEEE, 2009. http://dx.doi.org/10.1109/soccon.2009.5398049.
Pełny tekst źródłaHammerquist, Mark, i Roman Lysecky. "Design space exploration for application specific FPGAS in system-on-a-chip designs". W 2008 IEEE International SOC Conference (SOCC). IEEE, 2008. http://dx.doi.org/10.1109/socc.2008.4641527.
Pełny tekst źródłaCitro, Ricardo, Miguel Guerrero, Jae-Beom Lee i Maria Pantoja. "A multi-standard micro-programmable deblocking filter architecture and its application to VC-1 video decoder". W 2008 IEEE International SOC Conference (SOCC). IEEE, 2008. http://dx.doi.org/10.1109/socc.2008.4641516.
Pełny tekst źródłaZheng, Yi-Xue, Po-Ping Kan, Liang-Bi Chen, Kai-Yang Hsieh, Bo-Chuan Cheng i Katherine Shu-Min Li. "Fault tolerant application-specific NoC topology synthesis for three-dimensional integrated circuits". W 2011 IEEE 24th International SOC Conference (SOCC). IEEE, 2011. http://dx.doi.org/10.1109/socc.2011.6085088.
Pełny tekst źródłaKim, Sungil, Chulwook Lee, Yongsoon Baek i Jongtae Moon. "Implant Isolation Characteristics for SoC Application". W 2006 European Microwave Integrated Circuits Conference. IEEE, 2006. http://dx.doi.org/10.1109/emicc.2006.282667.
Pełny tekst źródłaYu Mingyan, Xie Xuejun, Wang Jinxiang, Ye Yizheng, Zhang Qingli i Wang Chenxu. "Parterre: an application-general SoC platform". W 2003 5th International Conference on ASIC Proceedings (IEEE Cat No 03TH8690) ICASIC-03. IEEE, 2003. http://dx.doi.org/10.1109/icasic.2003.1277575.
Pełny tekst źródłaNayaka, Raja Jitendra. "Ethernet Packet Processor for SOC Application". W International Conference of Advanced Computer Science & Information Technology. Academy & Industry Research Collaboration Center (AIRCC), 2012. http://dx.doi.org/10.5121/csit.2012.2333.
Pełny tekst źródłaRaporty organizacyjne na temat "SOC APPLICATION"
Withers, J. C., W. Kowbel i R. O. Loutfy. High thermal conductivity SiC/SiC composites for fusion applications. Office of Scientific and Technical Information (OSTI), kwiecień 1997. http://dx.doi.org/10.2172/543693.
Pełny tekst źródłaKowbel, W., K. T. Tsou, J. C. Withers i G. E. Youngblood. High thermal conductivity SiC/SiC composites for fusion applications -- 2. Office of Scientific and Technical Information (OSTI), marzec 1998. http://dx.doi.org/10.2172/335385.
Pełny tekst źródłaHsieh, G., T. O. Mason i L. R. Pederson. Application of impedance spectroscopy to SOFC research. Office of Scientific and Technical Information (OSTI), grudzień 1996. http://dx.doi.org/10.2172/460180.
Pełny tekst źródłaSnead, L. L., i O. J. Schwarz. Advanced SiC composites for fusion applications. Office of Scientific and Technical Information (OSTI), kwiecień 1995. http://dx.doi.org/10.2172/114940.
Pełny tekst źródłaYueh, Ken. SiC Composite for Fuel Structure Applications. Office of Scientific and Technical Information (OSTI), grudzień 2017. http://dx.doi.org/10.2172/1415452.
Pełny tekst źródłaScott Misture. Viscous Glass Sealants for SOFC Applications. Office of Scientific and Technical Information (OSTI), wrzesień 2012. http://dx.doi.org/10.2172/1062658.
Pełny tekst źródłaMurphy, Pamela, red. IEA SHC Annual Report 2020. IEA SHC, maj 2021. http://dx.doi.org/10.18777/ieashc-ar-2021-0001.
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