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Gotowe bibliografie tematyczne / Single-bit sigma-delta modulator

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Gotowa bibliografia na temat „Single-bit sigma-delta modulator”

Autor: Grafiati

Data publikacji: 4 czerwca 2021

Data aktualizacji: 4 lutego 2022

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Artykuły w czasopismach na temat "Single-bit sigma-delta modulator"

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Haimeng, Sun, R. Kochan, O. Kochan i Su Jun. "INTEGRAL NONLINEARITY OF SECOND-ORDER SINGLE-BIT SIGMA-DELTA MODULATOR". Tekhnichna Elektrodynamika 2016, nr 6 (29.09.2016): 63–68. http://dx.doi.org/10.15407/techned2016.06.063.

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NERURKAR, SHAILESH B., i KHALID H. ABED. "A LOW POWER CASCADED FEED-FORWARD DELTA-SIGMA MODULATOR FOR RF WIRELESS APPLICATIONS". Journal of Circuits, Systems and Computers 18, nr 02 (kwiecień 2009): 407–29. http://dx.doi.org/10.1142/s0218126609005149.

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This paper presents a design of a novel cascaded third-order feed-forward delta-sigma analog-to-digital converter (ADC). This ADC is realized using fully differential switched capacitor architecture and produces a 12-bit resolution at a data output rate (DOR) of 2.5 MS/s for RF wireless applications. The delta-sigma modulator consists of a second-order single-bit feed-forward modulator cascaded with a multi-bit first-order modulator. The cascaded feed-forward third-order (2-1) ADC is simulated using Matlab and Simulink. The delta-sigma modulator was designed using Cadence Virtuoso in TSMC 0.18 μm CMOS technology. The power consumption of the designed modulator is 12.74 mW, and the resolution is 11.85 bits for an over-sampling ratio (M = 32). The figure of merit is 1.38 pJ at a sample rate of 80 MS/s. The proposed delta-sigma modulator is compared with other state-of-the-art low-pass delta-sigma modulators in terms of their speed, power, DOR, and the proposed modulator has one of the lowest power consumption.

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Reyhani, S. Z., i O. Hashemipour. "SAR‐based delta–sigma modulator using single‐bit shared‐DAC". Electronics Letters 50, nr 3 (styczeń 2014): 156–58. http://dx.doi.org/10.1049/el.2013.3589.

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Thompson, A. C., P. O'Shea, Z. M. Hussain i B. R. Steele. "Efficient Single-Bit Ternary Digital Filtering Using Sigma-Delta Modulator". IEEE Signal Processing Letters 11, nr 2 (luty 2004): 164–66. http://dx.doi.org/10.1109/lsp.2003.821734.

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Shao, Qi, Qiu Ye Lv, Hao Meng, Qiang Fu i Xiao Wei Liu. "A Feed-Forward Sigma-Delta Modulator Applied in Silicon Gyroscope". Key Engineering Materials 645-646 (maj 2015): 657–61. http://dx.doi.org/10.4028/www.scientific.net/kem.645-646.657.

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Aiming to be applied in silicon gyroscope, a three-order single loop feedforward modulator with three-bit quantizer and local feedback is designed in this paper. Signal band is 200 KHz, sampling rate is 25.6 MHz, OSR is 64. Ideal modulator is then designed and simulated in MATLAB, getting SNR 125dB. Non-ideal factors are also added to ideal model, DWA technology is adopted to restrain the nonlinearity of multi-bit quantizer, getting SNR 104dB. Finally, transistor-level full-difference modulator is designed and simulated in Cadence, fetting SNR 101.3dB.

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Guo, Min, Hong Hui Deng, Bo Wen Ding i Yong Sheng Yin. "Design of a Second-Order Sigma-Delta Modulator". Applied Mechanics and Materials 644-650 (wrzesień 2014): 3797–801. http://dx.doi.org/10.4028/www.scientific.net/amm.644-650.3797.

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A second-order single bit Sigma - Delta modulator which can be applied to pressure sensor is designed in this paper.The modulator uses switched-capacitor circuit,and the operational amplifier adopts a differential folded-cascode structure with PMOS tube as input. Optimizes the coefficients at the system level design using Simulink tool. The schematic simulation and analysis is by the tools of Spectre and MATLAB with Global Foundry 0.35um CMOS technology. The modulator with oversampling rate of 256 is designed at the 3.3V power supply. Finally, this paper shows the circuit simulation results of the sigma-delta modulator whose signal-noise rate is 103.9dB and resolution is 16.97bits.

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Qian, Ying Qi, Chang Chun Zhang, Zhong Chao Liu, Lei Lei Liu, Yu Rong Luan, Yu Ming Fang i Yu Feng Guo. "A High-Performance Sigma-Delta Modulator in 0.18μm CMOS Technology". Applied Mechanics and Materials 519-520 (luty 2014): 1085–88. http://dx.doi.org/10.4028/www.scientific.net/amm.519-520.1085.

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Sigma-Delta (∑∆) modulators are commonly used in high-resolution analog-to-digital converters (ADCs). In this paper, a high-performance modulator targeted for ultra-high-frequency (UHF) radio-frequency identification (RFID) zero-intermediate frequency (ZIF) receivers is designed in standard 0.18μm CMOS technology. The modulator has been designed with switched-capacitor (SC) integrators employing gain-boosted operational amplifiers, voltage comparators and nonoverlapping clock generators to satisfy such requirements as high gain, low voltage and wide bandwidth. The behavioral-level modeling and circuit-level design are carried out with MATLAB/Simulink and Cadence/SpectreRF, respectively. Ultimately, the high-speed and low-power realization of a second-order single-bit modulator with an oversampling ratio (OSR) of 32 is presented. Simulation results shown that, from a 1.8V supply, operated at a sampling frequency of 64MHz, a dynamic range of 53.4dB over a signal bandwidth of 1MHz is achieved.

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Zhai, Huishan, i Bingo Wing-Kuen Ling. "Implementation and Performance Evaluation of the Frequency-Domain-Based Bit Flipping Controller for Stabilizing the Single-Bit High-Order Interpolative Sigma Delta Modulators". Applied Sciences 10, nr 17 (21.08.2020): 5785. http://dx.doi.org/10.3390/app10175785.

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This paper is an extension of the existing works on the frequency-domain-based bit flipping control strategy for stabilizing the single-bit high-order interpolative sigma delta modulator. In particular, this paper proposes the implementation and performs the performance evaluation of the control strategy. For the implementation, a frequency detector is used to detect the resonance frequencies of the input sequence of the sigma delta modulator. Then, a neural-network-based controller is used for finding the solution of the integer programming problem. Finally, the buffers and the combinational logic gates as well as an inverter are used for implementing the proposed control strategy. For the performance evaluation, the stability region in terms of the input dynamical range is evaluated. It is found that the control strategy can significantly increase the input dynamical range from 0.24 to 0.58. Besides, the control strategy can be applied to a wider class of the input signals compared to the clipping method.

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Huang, Fu Xiang, Zhi Qiang Gao i Xiao Wei Liu. "Design of 16 bit 200kHz Feedforward Sigma-Delta ADC Applied in Silicon Gyroscope". Key Engineering Materials 645-646 (maj 2015): 548–54. http://dx.doi.org/10.4028/www.scientific.net/kem.645-646.548.

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Due to the huge potential applications in military and civil fields, silicon micro mechanical gyro has become the most popular research direction in MEMS field today. Therefore, the corresponding interface circuit of silicon gyroscope has also become a hot topic at home and abroad. Now, integration, digitalization and intelligence has become the focus of future research directions of silicon gyroscope, so the research of analog to digital conversion circuit for gyroscope has become a research priority. Therefore, the conduct of Sigma Delta ADCs research for silicon gyro interface circuit has a very important significance and application prospects.This topic briefly introduces the working principle of Sigma Delta ADC. Based on the requirements of the modulator design, Sigma Delta modulator structures are carefully analyzed and also carried on the comparison and optimization. Hereby, a three order three bits quantization in single-loop with partial feedback of feed-forward summation system structure for modulator is designed in this paper, and then the ideal model of modulator system in Matlab is simulated. In addition, the focus of this topic is mainly on the nonlinear factors analysis and modeling, and the Data Weighted Average (DWA) technique used in multi-bit quantization is introduced as well as modeling in system level. Then, the non-ideal modeling of system is simulated in Matlab.In system level design, this paper adopts feed-forward summation and multi-bit quantization structure to reduce the output of the integrator, increase the noise performance of the modulator, and make it easier for the system stability. Furthermore, the use of partial feedback in the structure for zero-point optimization improves the noise shaping ability in signal bandwidth of modulator. This topic employs the single-loop third-order three-bit quantization structure, with the sampling rate 64, signal bandwidth 200 K Hz and the sampling clock frequency 25.6 MHz. For the ideal modeling, the Signal-to-Noise Ratio (SNR) is 125dB, and the Effective Number of Bits (ENOB) is 20.48. When in consideration of modulator’s nonlinear factors, the nonlinear systems Simulink simulation results obtained SNR of 104dB, and the ENOB is 16.98.In order to reduce the harmonic distortion of the modulator, transistor level is implemented by fully-differential switch capacitor circuit. The structure at all levels of the integrator was optimized. To reduce the influence of flicker noise, the integrator adopts Correlated Double Sampling (CDS) technology, and is improved by the partial feedback circuit. The fully-differential operational amplifier with high slew-rate and high bandwidth is designed, and uses switch capacitor circuit as common-mode feedback. Dynamic comparator and multi-bit quantizer are designed to improve the speed of the quantizer and reduce power consumption. The design the nonlinear compensation feedback DAC module--DWA module circuit--realizes noise shaping of capacitance matching error. The overall circuit was simulated in Cadence by 0.6um process. Transistor-level simulation result shows that the SNR is 101.3dB, and the effective number of bits is 16.54bits. The simulation results are consistent with the established non-ideal model of modulator, which verifies the correction of system level design method.

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Li, Haolin, Laurens Breyne, Joris Van Kerrebrouck, Michiel Verplaetse, Chia-Yi Wu, Piet Demeester i Guy Torfs. "A 21-GS/s Single-Bit Second-Order Delta–Sigma Modulator for FPGAs". IEEE Transactions on Circuits and Systems II: Express Briefs 66, nr 3 (marzec 2019): 482–86. http://dx.doi.org/10.1109/tcsii.2018.2855962.

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Rozprawy doktorskie na temat "Single-bit sigma-delta modulator"

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PATEL, VIPUL J. "BEHAVIORAL SIMULATION AND SYNTHESIS ENVIRONMENT FOR CONTINUOUS-TIME SINGLE-LOOP SINGLE-BIT BASEBAND DELTA-SIGMA ANALOG-TO-DIGITAL MODULATORS". University of Cincinnati / OhioLINK, 2006. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1147473065.

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Sadik, Amin, i not supplied. "Signal Processing Using Short Word-Length". RMIT University. Electrical and Computer Engineering, 2006. http://adt.lib.rmit.edu.au/adt/public/adt-VIT20070523.163613.

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Recently short word-length (normally 1 bit or bits) processing has become a promising technique. However, there are unresolved issues in sigma-delta modulation, which is the basis for 1b/2b systems. These issues hindered the full adoption of single-bit techniues in industry. Among these problems is the stability of high-order modulators and the limit cycle behaviour. More importantly, there is no adaptive LMS structure of any kind in 1b/2b domain. The challenge in this problem is the harsh quantization that prevents straightforward LMS application. In this thesis, the focus has been made on three axes: designing new single-bit DSP applications, proposing novel approaches for stability analysis, and tacking the unresolved problems of 1b/2b adaptive filtering. Two structures for 1b digital comb filtering are proposed. A ternary DC blocker structure is also presented and performance is tested. We also proposed a single-bit multiplierless DC-blocking structure. The s tability of a single-bit high-order signma-delta modulator is studied under dc inputs. A new approach for stability analysis is proposed based on analogy with PLL analysis. Finally we succeeded in designing 1b/2b Wiener-like filtering and introduced (for the first time) three 1b/2b adaptive schemes.

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Samid, Lourans. "The design of low power and low voltage continuous time sigma-delta modulators with single bit and multibit quantizer /". [S.l. : s.n.], 2004. http://swbplus.bsz-bw.de/bsz115637230abs.htm.

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Zeller, Sebastian [Verfasser], Robert [Gutachter] Weigel, Christian [Gutachter] Münker i Friedel [Gutachter] Gerfers. "Wide-Bandwidth Single-Bit Continuous-Time-Sigma-Delta-Modulation for Area- and Power-Efficient A/D Conversion with Low Jitter Sensitivity / Sebastian Zeller ; Gutachter: Robert Weigel, Christian Münker, Friedel Gerfers". Erlangen : FAU University Press, 2017. http://d-nb.info/1149368713/34.

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Wu, Chen-Tsung, i 吳振聰. "A Fourth-Order Single-Bit Switch-Capacitor Sigma-Delta Modulator for Audio Applications". Thesis, 2004. http://ndltd.ncl.edu.tw/handle/90377655292904193573.

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碩士
國立成功大學
電機工程學系碩博士班
92
In this thesis, we present the complete design procedure of a fourth-order single-bit switch-capacitor sigma-delta(Σ-Δ) modulator for audio applications. Recently, oversampling technology is very popular for audio applications, but the fourth-order feedforward(FF) architecture is not applied extensively in Taiwan. Because of the stability problem, the coefficients of high-order architecture of Σ-Δ modulator is very difficult to derive. And it takes a lot of time to simulate in the circuit level. Therefore we present a complete design procedure and use a behavioral model to efficiently reduce the simulation time. So as to reduce the possibility of over-design. In our design, we employ a fully differential opamp and a high-speed, low-power comparator including design guidelines and practical performance considerations, which will be very helpful for someone interested in high-order analog oversampling modulator. The final implementation is a four-order, 320 oversampling ratio, single-bit oversampling modulator in TSMC 2.5V, 0.25μm,1P5M CMOS mixed-mode process. Simulation results reveal that the peak SNDR of 87.1dB can be achieved with a signal bandwidth of 20k Hz and the total power dissipation is 17.7mW for sampling frequency of 12.8M Hz.

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Yen-Lung, Lu, i 呂炎龍. "Design and Implementation of Dynamically Dithered Single-Bit Sigma-Delta Modulation Systems Used in Audio DACs". Thesis, 2002. http://ndltd.ncl.edu.tw/handle/04693084401007258105.

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碩士
國立臺灣大學
電機工程學研究所
90
Abstract This study investigates the design of high-order single-bit sigma-delta audio DAC. The performance metrics of the digital sigma-delta modulation system consist of signal-to-noise ratio and dynamic range. The inherent tonal behavior of sigma-delta modulators should be suppressed, or even eliminated. We design a digital sigma-delta modulation system, including a 3rd-order CIFB modulator, a 5-stage 128x interpolator and a dynamic dither generator in this study. Dithering techniques are indispensable for digital audio. In our design, we eliminate the idle-tones effectively by adding an appropriate dither signal before the quantizer while minimizing the degradation of dynamic range. The overall system is programmed into FPGA, and the measured SNR plot is quite linear compared to an undithered one. The dynamic range and signal-to-noise ratio are 108 dB and 110dB, respectively.

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Części książek na temat "Single-bit sigma-delta modulator"

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Geerts, Yves, Michiel Steyaert i Willy Sansen. "Single-Loop Multi-Bit Sigma-Delta Modulators". W CMOS Telecom Data Converters, 277–306. Boston, MA: Springer US, 2003. http://dx.doi.org/10.1007/978-1-4757-3724-0_8.

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Hirata, S., M. K. Kurosawa i T. Katagiri. "Sensor Signal Processing for Ultrasonic Sensors Using Delta–Sigma Modulated Single-Bit Digital Signal". W Acoustical Imaging, 317–22. Dordrecht: Springer Netherlands, 2008. http://dx.doi.org/10.1007/978-1-4020-8823-0_44.

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"Single-Bit Single-Stage ΔΣ Modulators Modeling and Design". W Delta-Sigma Modulators, 77–99. PUBLISHED BY IMPERIAL COLLEGE PRESS AND DISTRIBUTED BY WORLD SCIENTIFIC PUBLISHING CO., 2003. http://dx.doi.org/10.1142/9781848161214_0004.

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Streszczenia konferencji na temat "Single-bit sigma-delta modulator"

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Kochan, Roman, Tomasz Ganczarczyk, Orest Kochan i Halyna Klym. "Integral nonlinearity of third order single bit sigma-delta modulator". W 2016 16th International Conference on Control, Automation and Systems (ICCAS). IEEE, 2016. http://dx.doi.org/10.1109/iccas.2016.7832514.

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Kashmiri, Mahdi, Kofi Makinwa i Lucien Breems. "A multi-bit cascaded sigma-delta modulator with an oversampled single-bit DAC". W 2009 16th IEEE International Conference on Electronics, Circuits and Systems - (ICECS 2009). IEEE, 2009. http://dx.doi.org/10.1109/icecs.2009.5410950.

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Rajabzadeh, Mahdi, Joachim Becker i Maurits Ortmanns. "Evaluation of single-bit sigma-delta modulator DAC for electrical impedance spectroscopy". W 2017 IEEE Biomedical Circuits and Systems Conference (BioCAS). IEEE, 2017. http://dx.doi.org/10.1109/biocas.2017.8325063.

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Jinfeng, Li, Cao Shun i Wang Ying. "A reconfigurable multirate single-bit sigma delta modulator for multi-standard wireless radio receivers". W 2011 IEEE 3rd International Conference on Communication Software and Networks (ICCSN). IEEE, 2011. http://dx.doi.org/10.1109/iccsn.2011.6014667.

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Park, S. J., R. M. Gray i W. Chou. "Analysis of a sigma delta modulator with a multi-level quantizer and single-bit feedback". W [Proceedings] ICASSP 91: 1991 International Conference on Acoustics, Speech, and Signal Processing. IEEE, 1991. http://dx.doi.org/10.1109/icassp.1991.150773.

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Abeda, Aymen, Manel Ben-Romdhane i Chiheb Rebai. "High Order Single-bit Delta Sigma Modulator for Fractional-N Frequency Synthesis in Multi-Standard Transceiver". W 2008 2nd International Conference on Signals, Circuits and Systems (SCS). IEEE, 2008. http://dx.doi.org/10.1109/icscs.2008.4746927.

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Maljar, David, Viera Stopjakova i Daniel Arbet. "Visualization of noise shaping through models of a first-order $\Sigma-\Delta$. modulator with single-bit quantizer". W 2020 18th International Conference on Emerging eLearning Technologies and Applications (ICETA). IEEE, 2020. http://dx.doi.org/10.1109/iceta51985.2020.9379253.

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Chen, Xiao, Zhi-Gong Wang i Fei Li. "A 1-V 90.3-dB DR 100-kHz BW 4th-Order Single Bit Sigma-Delta Modulator in 40-nm CMOS Technology". W 2018 IEEE 3rd International Conference on Integrated Circuits and Microsystems (ICICM). IEEE, 2018. http://dx.doi.org/10.1109/icam.2018.8596548.

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Irfansyah, Astria Nur. "Sine wave synthesis with harmonic-cancellation and single-bit Sigma-Delta modulation". W 2017 International Symposium on Electronics and Smart Devices (ISESD). IEEE, 2017. http://dx.doi.org/10.1109/isesd.2017.8253322.

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Sotiriadis, Paul P., i Charis Basetas. "All-digital single-bit-output RF transmitters using homodyne sigma-delta modulation". W 2017 6th International Conference on Modern Circuits and Systems Technologies (MOCAST). IEEE, 2017. http://dx.doi.org/10.1109/mocast.2017.7937680.

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