Rozprawy doktorskie na temat „Sigma-Delta quantization”

In this thesis, our main focus is Sigma-Delta quantization schemes. These are commonly used in state-of-art Analog-to-digital conversion technology. Their main advantage is the ease of implementation and more importantly their insensitivity to certain circuit imperfections. When we compare sigma-delta scheme with pulse-code modulation (PCM), sigma-delta is inferior in terms of rate distortion because an N-bit kth order sigma-delta quantizer produces an approximation with the error of order O(N-k) whereas the corresponding N-bit PCM scheme has accuracy of O(2−N)). However, this is a raw estimate of the actual rate-distortion characteristic of sigma-delta as one can further compress the bitstreams obtained via sigma-delta quantization. Even though this observation was made earlier in [10] under certain assumptions, to our knowledge, it was not investigated fully. In this thesis, such an investigation is made for first-order sigma-delta quantizers by using some results from symbolic dynamics literature on “Sturmian words”. Surprisingly, it turns out that the approximation error is a function of the “actual bit-rate”, i.e., the bit-rate after compressing an N-bit first-order sigma-delta encoding. In addition, in this thesis, we will introduce a new setup for sampling a bandlimited function and then quantizing these samples via first-order sigma-delta scheme. This simple but surprisingly efficient technique will allow us to get a better bound for the approximation rate of sigma-delta schemes and it will allow us to apply the derived results for compression of the bitstreams.

Thesis (Ph. D.) -- University of Maryland, College Park, 2006.
Thesis research directed by: Mathematics. Title from t.p. of PDF. Includes bibliographical references. Published by UMI Dissertation Services, Ann Arbor, Mich. Also available in paper.

Abstract Oversampling data converters based on Delta-Sigma modulation are a popular solution for modern high-resolution applications. In the design of digital-to-analog or analog-to-digital Delta-sigma converters there are common obstacles due to the difficulties on predicting and verifying their performance. Being a highly nonlinear system, a Delta-Sigma modulator’s (DSM) quantization noise and therefore the spurious tones are difficult to analyze and predict. Multi-bit DACs can be used to improve the performance and linearize the behavior of DSMs. However, this will give rise to the need for linearizing the multi-bit DAC. A popular DAC linearization method, data weighted averaging (DWA) shapes the DAC mismatch noise spectrum. There are many variants of DWA, for low-pass and band-pass DSMs. This thesis proposes a generalization which integrates a few published variants into one, broader DWA scheme. The generalization enables expanding the tone-suppression studies into a larger concept. The performance of one- or multibit DSMs is usually verified by simulations. This thesis proposes a simulation-based qualification (characterization) method that can be used to repeatedly verify and compare the performance of multibit DSM with a DAC mismatch shaping or scrambling scheme. The last contribution of this thesis is a very simple model for tonal behavior. The model enables accurate prediction of spurious tones from both DSMs and DWA-DACs. The model emulates the tone behavior by its true birth-mechanism: frequency modulation. The proposed prediction model for tone-behavior can be used for developing new tone-cancelation methods. Based on the model, a DWA linearization method is also proposed
Tiivistelmä Delta-Sigma modulaatio on suosituin tekniikka ylinäytteistävissä datan muuntimissa. Riippumatta toteutustarkoituksesta (analogia-digitaali- tai digitaali-analogia-muunnos), Delta-Sigma (DS) modulaatiossa on yleisesti tunnettuja käyttäytymisen ennustamiseen liittyviä ongelmia. Nämä ongelmat ovat peräisin modulaattorin luontaisesta epälineaarisuudesta: DS-muunnin on nimittäin vahvasti epälineaarinen takaisinkytketty systeemi, jonka harhatoistojen ennustaminen ja analysointi on erittäin hankalaa. Yksibittisestä monibittiseen DS-muuntimeen siirryttäessä muuntimen suorituskyky paranee, ja muuntimen kohinakäyttäytyminen on lineaarisempaa. Tämä kuitenkin kostautuu tarpeena linearisoida DS-muuntimen digitaali-analogia (D/A) muunnin. Tällä hetkellä tunnetuin linearisointimenetelmä on nimeltään DWA (data weighted averaging) algoritmi. Tässä työssä DWA:lle ja sen lukuisille varianteille esitellään eräänlainen yleistys, jonka avulla algoritmia voidaan soveltaa sekä alipäästö- että kaistanpäästö-DS-muuntimelle. Kuten tunnettua, DS-modulaattorin analyyttinen tarkastelu on raskasta. Yksi- ja monibittisten DS-muuntimien suunnitellun käyttäytymisen varmistaminen tapahtuukin yleensä simulointien avulla. Työssä esitetään simulointiperiaate, jolla voidaan kvalifioida (karakterisoida) monibittinen DS-muunnin. Tarkemmin, kvalifioinnin kohteena on DWA:n kaltaiset D/A -muuntimien linearisointimentelmät. Kyseessä on pyrkimys ennen kaikkea toistettavaan menetelmään, jolla eri menetelmiä voidaan verrata nopeasti ja luotettavasti. Tämän väitöstyön viimeinen kontribuutio on matemaattinen malli harhatoistojen syntymekanismille. Mallilla sekä DS-muunnoksen että DWA-D/A -muunnokseen liittyvät harhatoistot voidaan ennustaa tarkasti. Harhatoistot mallinnetaan yksinkertaisella havaintoihin perustuvalla FM-modulaatiokaavalla. Syntymekanismin mallinnus mahdollistaa DS-muuntimien ennustettavuuden ja täten auttaa harhatoiston kumoamismenetelmien kehittämistä. Työssä esitetään yksi matemaattisen mallin avulla kehitetty DWA-D/A -muunnoksen linearisointimenetelmä

The thesis demonstrates a low-cost, low-bandwidth and low-resolution Analog-to- Digital Converter(ADC) in 0.35 um CMOS Process. A second-order Sigma-Delta modulator is used as the basis of the A/D Converter. A Semi-Uniform quantizer is used with the modulator to take advantage of input distributions that are dominated by smaller-amplitude signals e.g. Audio, Voice and Image-sensor signals. A Single-bit feedback topology is used with a multi-bit quantizer in the modulator. This topology avoids the use of a multi-bit DAC in the feedback loop – hence the system does not need to use digital correction techniques to compensate for a multi-bit DAC nonlinearity.

High-Level Simulations of the second-order Sigma-Delta modulator single-bit feedback topology along with a Semi-Uniform quantizer are performed in Cadence. Results indicate that a 5-bit Semi-Uniform quantizer with a Over-Sampling Ratio of 32, can achieve a resolution of 10 bits, in addition, a semi-uniform quantizer exhibits a 5-6 dB gain in SNR over its uniform counterpart for input amplitudes smaller than –10 dB. Finally, this system is designed in 0.35um CMOS process.

This paper explores the noise shaping and noise producing qualities of Delta-Sigma Modulators (DSM) and Pulse-Width Modulators (PWM). DSM has long been dominant in the Delta Sigma Analog-to-Digital Converter (DSADC) as a noise-shaped quantizer and time discretizer, while PWM, with a similar self oscillating structure, has seen use in Class D Power Amplifiers, performing a similar function. It has been shown that the PWM in Class D Amplifiers outperforms the DSM [1], but could this advantage be used in DSADC use-cases? LTSpice simulation and printed circuit board implementation and test are used to present data on four variations of these modulators: The DSM, PWM, the out-of-loop discretized PWM (OOLDP), and the cascaded modulator. A generic form of an Nth order loop filter is presented, where three orders of this generic topology are analyzed in simulation for each modulator, and two orders are used in physical testing.

This thesis aims to contribute to the developments of wireless communication systems. The work generally consists of three parts: the first part is a discussion on general digital communication systems, the second part focuses on wireless channel modelling and fading mitigation techniques, and in the third part we discuss the possible application of advanced digital signal processing, especially time-frequency representation and blind source separation, to wireless communication systems. The first part considers general digital communication systems which will be incorporated in later parts. Today's wireless communication system is a subbranch of a general digital communication system that employs various techniques of A/D (Analog to Digital) conversion, source coding, error correction, coding, modulation, and synchronization, signal detection in noise, channel estimation, and equalization. We study and develop the digital communication algorithms to enhance the performance of wireless communication systems. In the Second Part we focus on wireless channel modelling and fading mitigation techniques. A modified Jakes' method is developed for Rayleigh fading channels. We investigate the level-crossing rate (LCR), the average duration of fades (ADF), the probability density function (PDF), the cumulative distribution function (CDF) and the autocorrelation functions (ACF) of this model. The simulated results are verified against the analytical Clarke's channel model. We also construct frequency-selective geometrical-based hyperbolically distributed scatterers (GBHDS) for a macro-cell mobile environment with the proper statistical characteristics. The modified Clarke's model and the GBHDS model may be readily expanded to a MIMO channel model thus we study the MIMO fading channel, specifically we model the MIMO channel in the angular domain. A detailed analysis of Gauss-Markov approximation of the fading channel is also given. Two fading mitigation techniques are investigated: Orthogonal Frequency Division Multiplexing (OFDM) and spatial diversity. In the Third Part, we devote ourselves to the exciting fields of Time-Frequency Analysis and Blind Source Separation and investigate the application of these powerful Digital Signal Processing (DSP) tools to improve the performance of wireless communication systems.

NOTE: Text or symbols not renderable in plain ASCII are indicated by [...]. Abstract is included in .pdf document. The trend toward digital signal processing in communication systems has resulted in a large demand for fast, accurate analog-to-digital (A/D) converters, and advances in VLSI technology have made [...] modulator based A/D converters attractive solutions. However, because they are non-linear systems, they have proven difficult to analyze. Rigorous analyses have been previously performed only for a small number of artificial input sequences and then only for the simplest of [...] modulator architectures. This thesis consists of three self-contained papers addressing these and related problems. The first two papers extend the repertoire of tractable input sequences for most of the known DE modulator architectures. The third paper applies the results from the first two papers to develop a scalable architecture for parallel [...] Modulation. The first paper concentrates on the first-order [...] modulator and develops rigorous results for a large class of input sequences. Under the assumptions that some circuit noise is present and that the input sequence does not cause overload, a simple autocorrelation expression is developed that is only locally dependent upon the input sequence. Ergodic properties are derived and various examples are presented. In the second paper, a rigorous analysis of the granular quantization noise in a general class of DE modulators is developed. Again under the assumption that some circuit noise is present, the joint statistics of the granular quantization noise sequences are determined and the sequences are shown to be correlation ergodic. The exact results developed for the granular quantization noise are shown to approximately hold for the overall quantization noise if the quantizers in the [...] modulator overload occasionally. The third paper develops a scalable A/D converter architecture consisting of multiple [...] modulators. By combining [...] modulator based A/D converters, each with an oversampling ratio of N, an effective oversampling ratio of approximately NM is achieved with only an M-fold increase in the quantization noise power. In particular, the special case of N = 1 allows for full-rate analog to digital conversion. Unlike most other approaches to trading modulator complexity for accuracy, the system retains the robustness of the individual [...] modulators to circuit imperfections.

碩士
國立清華大學
電機工程學系
102
In modern wireless communication systems, frequency synthesizers with high frequency resolution are used to up/downconvert signals to desired bands precisely. Phase-locked loops (PLLs) with the delta-sigma technique are a common way to achieve high frequency resolution. However, quantization noise is inevitable introduced during division ratio dithering, it greatly degrades the out-band noise performance especially in a high-bandwidth phase-locked loop. We focus on the study of quantization noise suppression. Analysis of quantization noise from delta-sigma modulation and the interface between continuous-time and discrete-time signal processing in PLLs plays an important role in this thesis. Based on this analysis, we propose a high oversampling rate (H-OSR) delta-sigma frequency synthesizer on which an finite-impulse response (FIR) digital filter and a novel half-integer frequency based on the phase compensation technique are embedded. The simulation result shows that the proposed architecture is able to suppress the quantization noise by 21 dB compared with the conventional MASH 1-1-1 structure. Moreover, the notch filtering effect from the FIR filter can further reduce quantization noise at the specific frequency, and improve the phase jitter performance. The proposed frequency synthesizer was verified by the silicon results in a TSMC 0.18μm CMOS process. Output frequency range is from 2.58 GHz to 3.45 GHz, the core power consumption is 12 mW. At the frequency of 1/5 and 3/5 reference frequency in the phase noise spectrum, the notch filtering effect can be found. Besides, FPGA is used to implement the delta-sigma modulator and the FIR filter during the measurement.

碩士
國立臺北科技大學
電機工程系所
98
This thesis focus on two topics, one is to study the cause of non-ideal effect and the compensations of switched-capacitor (SC) and switched-current (SI) technique.；In this topic, the comparison between the maximum SNDR and chip area is made under the same conditions. Moreover, a switched-capacitor parasitic-insensitive integrator is used to improve the non-idealitie which produced by parasitic capacitor in voltage mode. Conversely, we use sample-and-hold circuit which consists of both a feedback circuit is used to reduce the impedance at the input and a common-mode feedforward (CMFF) circuit to improve the common-mode offset at the output in the current mode. The other one is focused on the design of SC delta-sigma (Δ-Σ) modulator. That is, a high-order multi-bit delta-sigma modulator with dual-quantization technique is proposed in this topic. The dual-quantization technique is not only to reduce the quantization noise of multi-bit quantizer, but also to have intrinsically linear feedback of a single-bit DAC. Notify that the sub-ADC is made of a flash ADC. In this thesis, three systems are proposed and fabricated with TSMC 0.18

abstract: Pulse Density Modulation- (PDM-) based class-D amplifiers can reduce non-linearity and tonal content due to carrier signal in Pulse Width Modulation - (PWM-) based amplifiers. However, their low-voltage analog implementations also require a linear- loop filter and a quantizer. A PDM-based class-D audio amplifier using a frequency-domain quantization is presented in this paper. The digital-intensive frequency domain approach achieves high linearity under low-supply regimes. An analog comparator and a single-bit quantizer are replaced with a Current-Controlled Oscillator- (ICO-) based frequency discriminator. By using the ICO as a phase integrator, a third-order noise shaping is achieved using only two analog integrators. A single-loop, singlebit class-D audio amplifier is presented with an H-bridge switching power stage, which is designed and fabricated on a 0.18 um CMOS process, with 6 layers of metal achieving a total harmonic distortion plus noise (THD+N) of 0.065% and a peak power efficiency of 80% while driving a 4-ohms loudspeaker load. The amplifier can deliver the output power of 280 mW.
Dissertation/Thesis
Ph.D. Electrical Engineering 2011

Research Doctorate - Doctor of Philosophy (PhD)
This thesis presents results on optimal coding and decoding of discrete-time stochastic signals, in the sense of minimizing a distortion metric subject to a constraint on the bit-rate and on the signal transfer function from source to reconstruction. The first (preliminary) contribution of this thesis is the introduction of new distortion metric that extends the mean squared error (MSE) criterion. We give this extension the name Weighted-Correlation MSE (WCMSE), and use it as the distortion metric throughout the thesis. The WCMSE is a weighted sum of two components of the MSE: the variance of the error component uncorrelated to the source, on the one hand, and the remainder of the MSE, on the other. The WCMSE can take account of signal transfer function constraints by assigning a larger weight to deviations from a target signal transfer function than to source-uncorrelated distortion. Within this framework, the second contribution is the solution of a family of feedback quantizer design problems for wide sense stationary sources using an additive noise model for quantization errors. These associated problems consist of finding the frequency response of the filters deployed around a scalar quantizer that minimize the WCMSE for a fixed quantizer signal-to-(granular)-noise ratio (SNR). This general structure, which incorporates pre-, post-, and feedback filters, includes as special cases well known source coding schemes such as pulse coded modulation (PCM), Differential Pulse-Coded Modulation (DPCM), Sigma Delta converters, and noise-shaping coders. The optimal frequency response of each of the filters in this architecture is found for each possible subset of the remaining filters being given and fixed. These results are then applied to oversampled feedback quantization. In particular, it is shown that, within the linear model used, and for a fixed quantizer SNR, the MSE decays exponentially with oversampling ratio, provided optimal filters are used at each oversampling ratio. If a subtractively dithered quantizer is utilized, then the noise model is exact, and the SNR constraint can be directly related to the bit-rate if entropy coding is used, regardless of the number of quantization levels. On the other hand, in the case of fixed-rate quantization, the SNR is related to the number of quantization levels, and hence to the bit-rate, when overload errors are negligible. It is shown that, for sources with unbounded support, the latter condition is violated for sufficiently large oversampling ratios. By deriving an upper bound on the contribution of overload errors to the total WCMSE, a lower bound for the decay rate of the WCMSE as a function of the oversampling ratio is found for fixed-rate quantization of sources with finite or infinite support. The third main contribution of the thesis is the introduction of the rate-distortion function (RDF) when WCMSE is the distortion metric, denoted by WCMSE-RDF. We provide a complete characterization for Gaussian sources. The resulting WCMSE-RDF yields, as special cases, Shannon's RDF, as well as the recently introduced RDF for source-uncorrelated distortions (RDF-SUD). For cases where only source-uncorrelated distortion is allowed, the RDF-SUD is extended to include the possibility of linear-time invariant feedback between reconstructed signal and coder input. It is also shown that feedback quantization schemes can achieve a bit-rate only 0.254 bits/sample above this RDF by using the same filters that minimize the reconstruction MSE for a quantizer-SNR constraint. The fourth main contribution of this thesis is to provide a set of conditions under which knowledge of a realization of the RDF can be used directly to solve encoder-decoder design optimization problems. This result has direct implications in the design of subband coders with feedback, as well as in the design of encoder-decoder pairs for applications such as networked control. As the fifth main contribution of this thesis, the RDF-SUD is utilized to show that, for Gaussian sta-tionary sources with memory and MSE distortion criterion, an upper bound on the information-theoretic causal RDF can be obtained by means of an iterative numerical procedure, at all rates. This bound is tighter than 0:5 bits/sample. Moreover, if there exists a realization of the causal RDF in which the re-construction error is jointly stationary with the source, then the bound obtained coincides with the causal RDF. The iterative procedure proposed here to obtain Ritc(D) also yields a characterization of the filters in a scalar feedback quantizer having an operational rate that exceeds the bound by less than 0:254 bits/sample. This constitutes an upper bound on the optimal performance theoretically attainable by any causal source coder for stationary Gaussian sources under the MSE distortion criterion.