Rozprawy doktorskie na temat „SHIFTER DESIGN”
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SELVARAJ, JAYAPRAKASH. "Phase shifter design & Research study and verification of wideband phase shifter circuits". Thesis, KTH, Skolan för informations- och kommunikationsteknik (ICT), 2012. http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-105074.
Pełny tekst źródłaErcil, Erdinc. "X Band 7 Bit Mmic Phase Shifter Design". Master's thesis, METU, 2006. http://etd.lib.metu.edu.tr/upload/3/12607621/index.pdf.
Pełny tekst źródłaFoundry. All bits of the phase shifter are designed to have low return loss so as to minimize the performance egradation due to loading effects upon cascading. Also some structures studied using the design kit of WIN®
Foundry are presented. Both designs were performed using ADS®
. For the optimum cascading of 7 bits, a MATLAB code was written and used.
Hilding, Amanda. "Evaluation and Consequences Analysis of a Manual Shifter with Modular Design". Thesis, Blekinge Tekniska Högskola, Institutionen för maskinteknik, 2014. http://urn.kb.se/resolve?urn=urn:nbn:se:bth-5202.
Pełny tekst źródłaUnderleverantörerna inom fordonsindustrin har en stor press när det kommer till hålla nere kostnader och att leverera effektiva, optimerade och kvalitativa produkter. Huvudsyftet med studien är att guida och genomföra det första steget i projektet Standard Building Blocks med modulär design, inom affärsområdet, manuella växelreglage. Projektet är direkt framtaget av Kongsberg Automotive, en välkänd underleverantör inom fordonsindustrin. Målet med projektet är att utveckla en standard manuell växelreglage med modulär design innehållande standard building blocks. Fem olika komponenter har valts ut i den manuell växelreglaget för studien. För varje komponent finns det flera koncept hur den specifika komponenten kan designas. Målet med studien är att utvärdera och analysera koncepten och utifrån resultatet avgöra vilka av koncepten som kan bilda standard building blocks. Studien identifierar, utvärderar och analyserar konsekvenser av projektet Standard Building Blocks för de valda koncepten. Resultatet från studien visade att vissa koncept har en större tendens att bilda standard building blocks än andra. I studien blev det bevisat att icke-mätbara värden har lika stor betydelse som uppmätta värdena. Resultatet visade också att de mest lämpade koncepten beror på kundens specifikationer. Konsekvensen analysen presenter många konsekvenser av vad en implementation av standard building blocks kan innebära, från fördelar till eventuella riskfaktorer. Genom konsekvensanalysen kan det studerade företaget bli mer förberedda för framtiden.
Aboofazeli, Ali Reza. "Design of a Multiband Microstrip Differential Phase Shifter for Wireless Systems". Thesis, Université d'Ottawa / University of Ottawa, 2016. http://hdl.handle.net/10393/35497.
Pełny tekst źródłaStampfer, Marcel. "Magnetic and mechanical design calculations of a 4-5 Tesla superconducting wavelength shifter /". [S.l.] : [s.n.], 1995. http://e-collection.ethbib.ethz.ch/show?type=diss&nr=11010.
Pełny tekst źródłaJohnson-Eusebio, Alejandro. "60 GHz 4-Bit Phase Shifter Design with VO2 Switches". The Ohio State University, 2018. http://rave.ohiolink.edu/etdc/view?acc_num=osu1524207662285961.
Pełny tekst źródłaPamuk, Gokhan. "Design And Realization Of Broadband Instantaneous Frequency Discriminator". Master's thesis, METU, 2010. http://etd.lib.metu.edu.tr/upload/3/12612044/index.pdf.
Pełny tekst źródła18 GHz frequency band is designed, simulated and partially realized. The designed structure uses one coarse tier, three medium tiers and one fine tier for frequency discrimination. A novel reflective phase shifting technique is developed which enables the design of very wideband phase shifters using stepped cascaded transmission lines. Compared to the classical phase shifters using coupled transmission lines, the new approach came out to be much easier to design and fabricate with much better responses. This phase shifting technique is used in coarse and medium tiers. In fine frequency measurement tier, I/Q discriminator approach is used because reflective phase shifters would necessitate unacceptably long delay lines. Two I/Q discriminators are designed and fabricated using Lange directional couplers that operate in 2-6 GHz and 6-18 GHz, resulting in satisfactory response. Additionally, 6 GHz HP and 6 GHz LP distributed filters are designed and fabricated to be used for these I/Q discriminators in fine tier. In order to eliminate possible ambiguities in coarse tier, a distributed element LP-HP diplexer with 10 GHz crossover frequency is designed and fabricated successfully to be used for splitting the frequency spectrum into 2-10 GHz and 10-18 GHz to ease the design and realization problems. Three power dividers operating in the ranges 2-18 GHz, 2-6 GHz and 6-18 GHz are designed for splitting incoming signals into different branches. All of these dividers are also fabricated with satisfactory response. The fabricated components are all compact and highly reproducible. The designed IFM can tolerate 48 degrees phase margin for resolving ambiguity in the tiers while special precautions are taken in fine tier to help ambiguity resolving process also. The resulting IFM provides a frequency resolution below 1 MHz in case of using an 8-bit sampler with a frequency accuracy of 0.28 MHz rms for 0 dB input SNR and 20 MHz video bandwidth.
Mansouri, Ahmad, i David Norman. "Strategy Development of Structural Optimization in Design Processes". Thesis, Linköping University, Linköping University, Department of Management and Engineering, 2009. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-17418.
Pełny tekst źródłaThis thesis aims toward developing strategies in the area of structural optimization and to implement these strategies in design processes. At
GM Powertrain Sweden where powertrains are designed and developed, two designs of a differential housing have been chosen for this thesis. The main tasks have been to perform a topology optimization of a model early in a design process, and a shape optimization on a model late in a design process. In addition the shape optimization strategies have also been applied on a fork shifter. This thesis covers the theory of different optimization strategies in general. The optimization processes are explained in detail and the results from the structural optimization of the differential housings as well as the fork shifter are shown and evaluated. The evaluation of the thesis provides enough arguments to suggest an implementation of the optimization strategies in design processes at GM Powertrain
. A Structural Optimization group has great potential of closing the gap between structural designers and structural analysis engineers which in long terms mean that better structures can be developed in less time. To be competitive in the automotive industry these are two of the most important factors for being successful.
Alvarez, Cabrera Tanya. "SBW Feedback : Design of feedback system for increased usability in monostable SBW shifters". Thesis, Luleå tekniska universitet, Institutionen för ekonomi, teknik och samhälle, 2017. http://urn.kb.se/resolve?urn=urn:nbn:se:ltu:diva-62445.
Pełny tekst źródłaElektromekaniska shift-by-wire växlingssystem tillåter nya innovativa designlösningar så som monostabila växelväljare som fjädrar tillbaka till en ursprungsposition efter varje växelval. Dessvärre har den drastiska förändringen i kommunikationen mellan användarna och systemet resulterat i missförstånd och olyckor till följd av fel växelval. Den bristfälliga användbarheten av monostabila växelväljare kan härledas till feedbacken mellan förarens handling och resultat. Syftet med examensarbetet var att utveckla feedbackkoncept som förbättrade användbarheten av en monostabil växelväljare samt att studera om auditiv feedback kunde introduceras i förarsystem. Genom att implementera kunskaperna inom designteori, observationer från benchmarking samt diverse kreativa metoder kunde fem olika koncept presenteras. Koncepten utvärderades i en användbarhetsstudie med 25 testdeltagare. En genomgång av observationerna från användbarhetsstudien, intervjusvaren samt dataanalysen resulterade i det slutgiltiga konceptet VRA. VRA var ett multimodalt koncept som innehöll permanent visuell feedback samt valbar auditiv feedback. Växlingsschemat visades på instrumentpanelen där den aktiva växeln markerades med hjälp av kontraster i ljusintensitet, färg och form. Förkortningarna på aktiva växel visades inuti en solid blå rektangel som var synlig i periferin. Färgen uppfattades som lugn och den starka kontrasten hjälpte personerna att navigera växelväljaren. Den auditiva feedbacken var i form av en kvinnlig maskinröst med svenskt uttal som kompletterade ”P”, ”R” och ”D” växellägena. Inga testpersoner var likgiltiga till auditiv information, vissa beskrev den som omtänksam medan andra ansåg att den var irriterande. Eftersom analysen indikerade att auditiv feedback inte var kritisk var den auditiva feedbacken valbar i VRA. Monostabila växelväljare skiljer sig drastiskt från polystabila, därför bör kommunikationen mellan systemet och människan ses över i och med de fysiska förändringarna. Växlingsschemat bör inkluderas i instrumentpanelen i samband med att monostabila växelväljare används. Det kan nämligen kompensera bristen på den visuella och haptiska feedbacken från den fysiska väljaren. Trots att analysen visade på att auditiv feedbak inte var nödvändig kunde förbättringar observeras bland personer som tyckte om det. Den auditiva informationen skulle mest troligt få ett bättre bemötande om earcons användes istället för tal.
Parthasarathy, Krupa. "Aging Analysis and Aging-Resistant Design for Low-Power Circuits". University of Cincinnati / OhioLINK, 2014. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1415615574.
Pełny tekst źródłaMargalef, rovira Marc. "Design of mm-wave Reflection-Type Phase Shifters with Oscillation-Based Test capabilities". Thesis, Université Grenoble Alpes, 2020. http://www.theses.fr/2020GRALT025.
Pełny tekst źródłaThis work focuses on the design of on-silicon mm-wave Reflection-Type Phase Shifters (RTPS) with Oscillation-Based Test (OBT) capabilities. For more consistency, a single technology was considered, the STM 55-nm BiCMOS. First, the theory and practical implementations of 3-dB couplers is discussed. Particular attention is brought to the Coupled Slow-wave CoPlanar Waveguide (CS-CPW) topology, due to its good performance. Using this topology, the measurements of two 3-dB couplers are reported: (i) a 120-GHz, and (ii) a 185-GHz coupler.Next, the existing topologies of integrated varactors are discussed. Measurement results are reported for an Inversion-mode MOS (I-MOS) varactor from 1 up to 325 GHz. Additionally, the Common-Source MOS (CS-MOS) varactor architecture is proposed and measurement results from 1 to 145 GHz for this architecture are reported.Then, the theory of RTPS is presented and CS-CPW-based couplers together with Accumulation-mode MOS (A-MOS), I-MOS and CS-MOS varactors are used for the design of four RTPS. The measurement and simulation results of these RTPS, with central frequencies ranging from 60 to 200 GHz, are presented.Subsequently, the theory and measurement results of the OBT on an integrated 60-GHz RTPS are discussed.Finally, a mm-wave TRL calibration compaction technique is described using machine-learning tools
Bustamante, Danilo. "High-Precision, Mixed-Signal Mismatch Measurement of Metal-Oxide-Metal Capacitors and a 13-GHz 5-bit 360-Degree Phase Shifter". BYU ScholarsArchive, 2020. https://scholarsarchive.byu.edu/etd/9240.
Pełny tekst źródłaJebelli, Ali. "Design of an Autonomous Underwater Vehicle with Vision Capabilities". Thesis, Université d'Ottawa / University of Ottawa, 2016. http://hdl.handle.net/10393/35358.
Pełny tekst źródłaVivos, Jonathan. "Méthode de conception de déphaseurs à métamatériaux par l'utilisation de lignes composites équilibrée et non équilibrée". Thesis, Toulouse 3, 2019. http://www.theses.fr/2019TOU30327.
Pełny tekst źródłaDifferential phase shifters (DPS) are used in in parallel structures such as Butler matrices, to avoid losses on signal recombination to avoid losses on signal recombination. The DPS are generally composed of two transmission lines out of phase with each other. The phase shift control in these devices line length adjustment, or by integrating elements such as coupled lines or stubs. However, these solutions do not meet the many specifications of the phase shifter in an industrial context. Metamaterials, which are known as structures composed of several small elements, with unique properties, could enable phase shift control with more degrees of freedom. To this end, metamaterials such as composite lines have already been investigated. However they exploit a particular case of metamaterial, the balanced line, to design phase shifters. This thesis objective is to design metamaterial phase shifters by exploiting as much as possible their degrees of freedom, namely without limiting the phase shift design to balanced lines. For this purpose, we have implemented a dedicated design method to obtain from phase shifter specifications solutions with adequate performances for integration on very constrained industrial systems. This method has been illustrated and validated through an application to a case of 180° phase shifter with a 20% bandwidth in C band [4.95GHz -6.05GHz]
Abusitta, M. M. "Design and modelling of beam steering antenna array for mobile and wireless applications using optimisation algorithms. Simulation and measrement of switch and phase shifter for beam steering antenna array by applying reactive loading and time modulated switching techniques, optimised using genetic algorithms and particle swarm methods". Thesis, University of Bradford, 2012. http://hdl.handle.net/10454/5745.
Pełny tekst źródłaAbusitta, Musa M. "Design and modelling of beam steering antenna array for mobile and wireless applications using optimisation algorithms : simulation and measrement of switch and phase shifter for beam steering antenna array by applying reactive loading and time modulated switching techniques, optimised using genetic algorithms and particle swarm methods". Thesis, University of Bradford, 2012. http://hdl.handle.net/10454/5745.
Pełny tekst źródłaKotiyal, Saurabh. "Design Methodologies for Reversible Logic Based Barrel Shifters". Scholar Commons, 2012. http://scholarcommons.usf.edu/etd/4106.
Pełny tekst źródłaZafar, Junaid. "Finite Element Analysis and design of Ferrite Phase Shifters". Thesis, University of Manchester, 2009. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.503653.
Pełny tekst źródłaMa, Xu. "Generalized inverse lithography methods for phase-shifting mask design". Access to citation, abstract and download form provided by ProQuest Information and Learning Company; downloadable PDF file, 38 p, 2007. http://proquest.umi.com/pqdweb?did=1338919391&sid=3&Fmt=2&clientId=8331&RQT=309&VName=PQD.
Pełny tekst źródłaJungkvist, Sophie. "Shifty Weaves : Woven pleats which change upon viewing angle". Thesis, Högskolan i Borås, Akademin för textil, teknik och ekonomi, 2020. http://urn.kb.se/resolve?urn=urn:nbn:se:hb:diva-23804.
Pełny tekst źródłaGane, Victor 1974. "Parametric design : a paradigm shift?" Thesis, Massachusetts Institute of Technology, 2004. http://hdl.handle.net/1721.1/28478.
Pełny tekst źródłaIncludes bibliographical references (p. 96-97).
The variety reflected in constant change became an imperative in the development of the modem world. The society is more insistent in seeking the implementation of quality and customization in most of humans' activities. Such notions as satisfaction or contentment are achieved through having choices at one's disposal. While other creative disciplines are rapidly adapting to depict this evolving reality, architects continued to rely on traditional design methods, which in most cases is synonymous with a process resulting in few slowly developed choices. More recently, the adoption of computational aids did not have a significant impact as the latter are primarily used as tools to facilitate representations of designs. To keep up with the society's dynamism the architects must adopt a new approach to design, one which will facilitate the exploration of rational variety, allow them to programmatically search the solution space and develop systems or tools used in conceiving multiple designs. This thesis investigates parametric design as a possible remedy.
by Victor Gane.
S.M.
Alvianto, Priyanto Criss. "Shift Design and Driver Scheduling Problem". Thesis, KTH, Optimeringslära och systemteori, 2018. http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-227263.
Pełny tekst źródłaSchemaläggning och skiftdesignsproblem är välkända och välstuderade NP-svåra beslutsproblem inom optimeringsområdet. Oftast så studeras dessa problem enskilt, men i detta arbete så studeras en kombination av båda problemen. Mer specifikt är målet med detta arbete att föreslå ett förnuftigt handlingsätt till att skapa ett veckoschema där skift inte är predefinierade för alla veckor. Starttiden, sluttiden och varaktigheten av ett skift kan förändras från vecka till vecka. Därför har problemet delats upp till två delar: Veckoschemaläggnings- och dagsschemaläggningsproblem. Trots uppdelningen så är båda delproblem för komplexa för att lösas exakt. Därför har två metaheuristiska metoder använts som lösningsmetoder: Simulerad Glödgning och Genetisk Algoritm. I detta arbete bevisas båda lösningsmetoderna till att vara bra nog, och dessutom studeras även skalbarheten av modellen. Detta senare är särskilt viktigt eftersom antal anställda som ska schemaläggas förväntas att öka genomåren. De erhållna resultaten har visat sig vara lovande och bevisligen så kan modellen expanderas med er villkor
Jaz, I. J. "Construction of experimental designs using cyclic shifts". Thesis, University of Kent, 1991. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.293152.
Pełny tekst źródłaIlnicki, Andrew Patrick. "A Shift In Perspective". VCU Scholars Compass, 2006. http://scholarscompass.vcu.edu/etd/1376.
Pełny tekst źródłaBryant, Scott T. "User centred engineering in automotive design: A shift from technology-driven product development". Thesis, Queensland University of Technology, 2015. https://eprints.qut.edu.au/84793/1/Scott_Bryant_Thesis.pdf.
Pełny tekst źródłaFan, Zhang. "Torque Characteristic Design Verification Method for Shift Quality Calibration". Thesis, KTH, Maskinkonstruktion (Inst.), 2014. http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-168939.
Pełny tekst źródłaAt Volvo Cars Corporation (VCC), crankshaft torque is a control signal for calibrating the gearbox for gear shifting operations. The goal of this master thesis is to design a verification method (DVM) for crankshaft torque. Based on the wheel torque, the crankshaft torque is calculated by compensating the torque losses step by step. The relative torque loss data are provided by the previous measurements. The torque losses are classified by different components in the vehicle transmission system. The modeled crankshaft torque signal will be used as a reference signal to evaluate the performance of the Design Verification Method. The reference signal is certificated within a certain range by VCC.
Su, Hao-Zhi, i 蘇浩志. "Low Power Multiplier & Shifter Design". Thesis, 2002. http://ndltd.ncl.edu.tw/handle/35224197962087219363.
Pełny tekst źródła國立臺灣大學
資訊工程學研究所
90
This thesis presents a design methodology for the low power multiplier and the low power shifter. In the low power multiplier, the modified Booth architecture and the efficient sign extension can decrease the addition operation among partial products. By using fewer adders compared with the Braun-Wooley multiplier, the power consumption can be reduced. In order to enhance the performance of the multiplier, pipeline registers are inserted inside the multiplier to increase the throughput of the multiplier and Wallace tree 4:2 compressors are used to speed up the addition operation of partial products. According to the simulation results, using the MUX-based 4:2 compressor can increase the power saving ratio compared with the ADD-based one. In the low power shifter, the simulation results demonstrate that the logarithmic shifter consumes less power than the array shifter. So we use the logarithmic right shifter as the core of the fully functional barrel shifter, and insert additional stages and control circuits to achieve right rotation, logical/arithmetic right shifting, left rotation, and logical left shifting operations. Due to the fully functional barrel shifter is constructed by pass transistors, placing appropriate buffers is necessary. Based on the experimental results, the fully functional barrel shifter with three layers buffer of 1x size (W/L = 0.3/0.24) has less power consumption.
Chen, Po-Yu, i 陳柏佑. "Design of MMIC Active Phase Shifter". Thesis, 2002. http://ndltd.ncl.edu.tw/handle/14931688921021085983.
Pełny tekst źródła國立臺灣大學
電信工程學研究所
90
Phase shifter plays a critical role in many microwave/millimeter wave systems. For example, in an electronically scanned array (ESA) system, the phase shifter is the key essential component to provide differential phase shift to scan an angle off broadband. For those applications, there are usually thousand of phase shifters needed to construct the phase array system. Due to these reasons, the relatively low-cost GaAs based monolithic microwave integrated circuits (MMICs) are the preferred approach to realize phase shifter circuit. Recently the new architecture of active phase shifter using vector sum method has been proposed. The advantage of the new architecture is more efficient than previous architecture in size, power and number of circuit. According to vector sum theorem, the variable gain amplifier plays the most critical role in the active phase shifter since it provides gain and phase controlling of the phase shifter. Instead of using packaged dual-gate FET, monolithic circuits of variable gain amplifier are integrated in active phase shifter in this thesis. The active phase shifters are designed and implemented up to K band using HBT and PHEMT technology. At first, the variable gain amplifier and active phase shifter circuits are designed at 18 GHz using commercial InGaP/GaAs HBT foundry process. The GaAs HBT phase shifter has been measured with maximum phase error 11°. The root mean square phase error at 18 GHz is 6.9 degree. The average gain achieves 8.87 dB. The size is 6 mm2. It is the first time to design the circuit at 18 GHz using MMIC technology. The phase shifter using AlGaAs/GaInAs/GaAs PHEMT is designed at 20 GHz. The critical component variable-gain amplifier, has a different architecture from the one using HBT process. The measured performances show that the maximum phase error reaches 11° and the root mean square error is 4.7° at 20.4 GHz. The average gain is 3.85 dB. The same chip size of 6 mm2 is compared with HBT phase shifter.
Lin, Wei Zhen, i 林威震. "Phase Shifter Design Based on Vector Modulator". Thesis, 2013. http://ndltd.ncl.edu.tw/handle/84466605828983783191.
Pełny tekst źródła國立交通大學
電子研究所
101
The phase shifter is phase shifter is one of the most important circuit in multi-antenna communication system, such as phased array system. By the function of the phase shifter, we decide what direction of beam we want. In the thesis, two phase shifters are proposed. The first chip is 2.25 GHz 4-bit phase shifter in TSMC 0.18-μm CMOS technology. The phase shifter is composed with quadrature phase generator and variable gain amplifier. From the measurement results, when the phase shifter is at the center frequency, it generates 16 states of phase. The root mean square (RMS) phase error and the root mean square (RMS) magnitude error are lower than 1 degree, and 0.3 dB, respectively. The gain of phase shifter is -2.74 dB. The DC power consumption of core circuit is 10.28 mW from 1.8 V supply. The second chip is 0.75~2.67 GHz 5-bit phase shifter in TSMC 0.18-μm CMOS technology. The phase shifter is composed with quadrature phase generator, amplifier, and attenuator. From the measurement results, when operating frequency of phase shifter is 0.75~2.67 GHz, it generates 32 states of phase. The root mean square (RMS) phase error and the root mean square (RMS) magnitude error are lower than 3.5 degree, and 0.4 dB, respectively. The gain of phase shifter is 3.6~-17.22 dB. The DC power consumption of core circuit is 6.39 mW from 1.8 V supply.
Wang, Hsien-Tang, i 王憲棠. "77-110GHz 65nm-CMOS Wideband Phase Shifter Design". Thesis, 2015. http://ndltd.ncl.edu.tw/handle/65367470130377839249.
Pełny tekst źródła國立交通大學
電子工程學系 電子研究所
104
This thesis will propose a NC broadband phase shifter designed in TSMC 65nm-CMOS technology. The circuit is designed for millimeter-wave imaging system, by changing the phase of input signal to achieve the purpose of operation of antenna array. The phase shifter circuit comprises two series sub-circuits: coarse and supporting phase shifter. The former one allows 32 different phase outputs with unit step 11.25 degree by giving 5 bit control signals. The series supporting phase shifter provides extra phase delay and fine tunes the output signal phase to grid 1 degree. The design approach and behavior of this circuit will be well discussed and clearly illustrated in the following thesis.
Yu, Hao-Hsiang, i 游皓翔. "W-band Phase Shifter Design in CMOS process". Thesis, 2018. http://ndltd.ncl.edu.tw/handle/t5d9bb.
Pełny tekst źródła國立交通大學
電子研究所
106
Architecture for digital-control phase shifters is introduced in this thesis. The implementation of the phase shifter in W-band integrated circuits is discussed. The operational principles of the phase shifter and the characteristics of the sub-circuits are examined. Two processes, TSMC 65nm-CMOS and TSMC 40nm-CMOS, are proposed to fabricate the phase shifter. The phase shifter fed with three-bit digital signals in time sequence can offers 32 phase delay outputs within the range from 0˚ to 360˚ in a step of 11.25˚. A broadband receiver comprising the phase shifter, a mixer, a tripler, and an IF amplifier was designed and fabricated in a single chip through the 40nm-version process. The receiver offers tunable phase delays and simultaneous down-conversion for the signals. This result demonstrates the feature of high integration of the proposed phase shifter. At the end, based on the fabrication results of the phase shifters by the two proposed processes, the advantages and disadvantages of their characteristics and associated sub-circuit structures are discussed.
Li, Ruei-Syuan, i 李睿軒. "Design of Tunable Phase Shifter for Smart Antenna System". Thesis, 2007. http://ndltd.ncl.edu.tw/handle/46158991871504782977.
Pełny tekst źródła國立中正大學
電機工程所
95
Abstract In this thesis work, a novel design of broadband compact tunable phase shifter has been proposed, constructed and measured for the multi-beam smart antenna system. Without changing any TX/RX circuitries, the proposed phase shifter can be combined with existing switched-beam antenna system to provide the tuning mechanism, where the space multiplexing ability of this array system can be further increased. The reflection-type phase shifter, which consists of a quadrature coupler and two identical reflection loads, is chosen for this work. In order to integrate with our existing multi-layer 8×8 Butler matrix, the three-layer, strip-line configuration is adopted in the quadrature coupler. Additionally, it has been found that the asymmetric coupler with impedances at I/O ports different from the impedance at load port could increase the phase tuning range dramatically. Therefore, the matching network based on Chebyshev and linear tapered formulas are both utilized to design this asymmetric coupler(50Ω-25Ω). The measurement data shows that the phase tuning range is >130o within the desired bandwidth(1.5-2.8 GHz). Moreover, the 360o tunable phase shifter using two varactors and one inductor as reflection load is also designed and successfully demonstrated in this work. To reveal the beamforming function of proposed phase shifter, an 8×8 Butler matrix, a fully planar monopole 1×8 antenna array and 8 newly designed broadband phase shifter are integrated to structure a tunable switched-beam phase antenna array. The Butler matrix initially provides eight kinds of phase distribution, whereas the phase shifters offer the additional phase tuning range with bias voltage properly applied. The scanning angle is thus expanded from 105o to 132o, and the direction of beams can be swept continuously.
Liu, Yi-Chen, i 劉懿稹. "Design of Microwave CMOS-MEMS Refection-Type Phase Shifter". Thesis, 2014. http://ndltd.ncl.edu.tw/handle/yf4n33.
Pełny tekst źródła國立中正大學
電機工程研究所
102
In this thesis, three types of phase shifter using CMOS-MEMS technologies based on different structures are analyzed, designed and fabricated. By changing the spacing of interdigitated capacitors, the reactance can be varied, leading to the phase change. The first circuit is a branch-line coupler-based reflection-type phase shifter with continuous-phase-tuning mechanism, which is fabricated in TSMC 0.18-μm CMOS process. The main goal of this work is to investigate the cantilever displacement due to the electrostatic attraction before pull-in happens, which will give the circuit a certain range for continuously phase tuning. The second circuit is Wilkinson power-divider-based reflection-type phase shifter fabricated in UMC 0.18-μm CMOS-MEMS process. Instead of using two identical loadings, this topology only requires single loading. In this case, the single-end interdigital capacitance is constructed using two rotor fingers to move asymmetrically with one stator comb set in the middle of them, therefore nine states can be achieved. The measurement results show that maximum phase range is , and the chip size is 1.03 mm2. The third design is an active-circulator-based reflection-type phase shifter in TSMC 0.18-μm CMOS-MEMS process. The nine-states single-end interdigital capacitance is integrated with an active circulator, while two buffers are added to boost the output power. Simulation result shows the phase range is at 24 GHz, and the whole chip size is 1.86 mm2.
Chen, Shin-Gang, i 陳信綱. "360 degree Voltage Control Phase Shifter Design and Fabrication". Thesis, 2009. http://ndltd.ncl.edu.tw/handle/56057948596492662444.
Pełny tekst źródła國立成功大學
微電子工程研究所碩博士班
97
The main purpose of this thesis is to investigate 360 degree tunable voltage controlled phase shifter at 2.4Ghz. All of these Rf circuits are fabricated with Fr4 pcboard. The basic parameters of the Fr4 pcboard are shown as follows. The dielectric constant is 4.3. Board thickness is 1mm. Copper layer thickness is 0.035mm. Losstangent is 0.018. In this thesis we present several kinds of area reduced couplers which can be used to reduce the area of the phase shifter. These couplers are T-shape transmission line coupler, super small coupler , and impedance discontinuous coupler. The parameters of T-shape transmission line coupler are shown as follows. Output magnitude are -3.416dB and -3.82dB.Output phase are 145.6 and -127.3 degree. Returnloss is -17.81dB.The area is 49.13% (14.14mm X16.4mm) as compared to conventional one. The parameters of impedance discontinuous coupler are shown as follows. Output magnitude are -3.567dB and -3.58dB. Output phase are 164.1and-116.1degree.Returnloss is -19.88dB.The area is 47.82% (19.4mmX 24.33 mm)as compared to the traditional one. The parameters of super small coupler are shown as fllows. Output magnitude are -3.39dB and-3.45dB.Output angle are 168.9 and -94.41 degree. Returnloss is -18.04dB. The area is 22.69%(7mmX15.3mm) as compared to conventional one. In addition,square retrace coupler can also be used for making reflective type phase shifter. The parameters of square retrace are shown as follows. Output magnitude are -3.767dB and -4.437dB.Output phase are 49.9 and 120.9 degree. Returnloss is -15.02dB.The area is 19.618%(16.9141mmX16.9141mmX )as compared to traditional ratrace coupler .There are two ways in the thesis of fabricating analog phase shifter. They are called Type-B and Type-C phase shifters. The size of Type-B and Type-C phase shifter is2.4cmX3.1cm and 2.43cmX3.164cm.When controlvoltage (Between 0v and 16.5v) applied to Type-B phase shifter. The phase angle can be tuned from 6.6 degree to 368.875 degree. The total tunable range is 362.275 degree. Insertion loss is ranging from -2.1dB to -2.65dB. Returnloss is ranging from -10.76dB to -14.04dB.The angle-voltage curve performances as straight line between 100 degree and 320 degree. Type-B phase shifter has 220 degree linear control range. When controlvoltage (Between 0v and 22v) applied to Type-C phase shifter. The phase angle can be tuned from 39.4degree to 406 degree. The total tuning range is 366.6 degree. Insertionloss is ranging from-2dB to -2.5dB. Returnloss is ranging from -7.45dB to -8.108dB. The angle-voltage curve performances as a straight line between 145 degree and 350 degree. Type-C phase shifter has 205 degree linear control range.
Lin, Kai-Chieh, i 林楷傑. "Design of Isolated Gate Driver with Voltage Level Shifter". Thesis, 2018. http://ndltd.ncl.edu.tw/handle/pr3bq6.
Pełny tekst źródła國立彰化師範大學
電機工程學系
106
Abstract This study introduces an isolated gate driver design using the TSMC highvoltage (HV) bulk 0.25-μm CMOS process. The isolated gate driver design with a voltage level shifter can effectively reduce input drive voltage requirements and the overall energy needed to the power gate drivers. This study also details the on-chip transformer and on-chip inductor used. The structure of the on-chip transformer comprises a stacked transformer (featuring increased coupling rate) and a tapped transformer (featuring superior voltage isolation). The circuit designed in this study will use the TSMC high-voltage (HV) bulk 0.25-μm CMOS process to manufacture the wafers. Comparison of actual measurement and simulation shows that this circuit is feasible. Finally, the experimental results show that circuit with a voltage level shifter can indeed reduce the power required for the input and increase the circuit efficiency. Keywords : isolated gate driver ; voltage level shifter ; on-chip transformer ; on-chip inductor ; tapped transformer ; stacked transformer
LIN, KUAN-TING, i 林冠廷. "Circuit Design of 25GBaud Optical Receiver Module withLevel Shifter". Thesis, 2019. http://ndltd.ncl.edu.tw/handle/j6x8yz.
Pełny tekst źródła國立高雄科技大學
電子工程系
107
This thesis is divided into two parts, which discuss the characteristics of Panasonic M7 high-frequency circuit board, the introduction of signal modulation and the circuit design of four-channel short-wavelength fourth-order amplitude modulation optical receiving module and the verification of high-frequency transmission technology. In the part of the high-frequency circuit board design, the dielectric constant of the Panasonic M7 sheet material and the characteristics of the loss factor under high-frequency transmission are discussed, and the results of the metallographic analysis are added to confirm the credibility of the measured data. The goal is to achieve a single channel of 25GBaud, 50GBaud transmission, and compare it with the lab-used Panasonic Megtron 6 printed circuit board and verify the potential of the Panasonic M7. Design and verification of the part of the four-channel short-wavelength fourth-order amplitude modulation optical receiver (850nm). The module is first implemented using the specifications of the Quad Small Form Factor Pluggable (QSFP-28), the photodiode and the transimpedance amplifier. Design, a total of four channels are used as receiving channels. Through NRZ modulation, three channels can achieve error-free transmission. First, 25Gb/s 215-1 pseudo-random binary sequence signal is used for NRZ modulation signal measurement, and optical reception. After the signal-to-noise ratio is 5.418, the rise time is 23ps, the fall time is 28ps, the jitter value is 13.8ps, and the back-to-back transmission can achieve no error. After consideration, it is decided to add a clock data recovery circuit IC, combined with a voltage level converter to enable the microcontroller, the transimpedance amplifier and the clock data recovery circuit IC to communicate with each other. A total of four channels are used as receiving channels, and a 25Gb/s 215-1 pseudo-random binary sequence signal is used for NRZ modulation signal measurement. The signal-to-noise ratio after light reception is 12.857, the rise time is 23.4ps, and the fall time is 24.2ps, jitter value of 10.8ps, back-to-back transmission can achieve no error. Four channels can achieve error-free transmission. Finally, the commercial optical emission module is used to measure the two versions of the circuit, and the 50Mb/s 47-1 pseudo-random four-bit sequence is used for the PAM4 modulation signal measurement. After the measurement, the version one receiving module is tested. Back-to-back, transmission of 110m, 210m OM4 multimode fiber can achieve error-free transmission after FEC.
ZHU, FU-SHENG, i 朱富聖. "Design and Implementation of CMOS Attenuator and Phase Shifter". Thesis, 2019. http://ndltd.ncl.edu.tw/handle/ec4tr6.
Pełny tekst źródła國立臺北科技大學
電子工程系
107
This thesis includes two sections, the first section is a 4-bit ultra-wideband CMOS attenuator made in a standard 0.18-μm complementary metal-oxide-semiconductor (CMOS) process. This design adopts switched bridge-T type topologies for each attenuation bit. Based on insertion losses and input P1dB considerations, the circuit performances can be optimized by the proper bit ordering arrangement. Therefore, the bit ordering 0.5-4-2-1 dB is employed in the 4-bit attenuator. Moreover, series inductors are added between each bit to further improve the input and output return losses. Measured results demonstrate that the attenuation range of the circuit is 7.5 dB with 0.5 dB step and the root-mean-square (RMS) amplitude error is between 0.11 and 0.13 dB from 3.1 to 10.8 GHz. The differences between simulated and measured RMS amplitude errors are less than 0.2 dB which demonstrates the good agreement and feasibility of the design concept. The measured input P1dB is 15 dBm at 5 GHz and the chip area is 1.12 mm2 including all testing pads. The second section presents a 3-bit 9~11 GHz CMOS phase shifter on standard 0.18 CMOS process which is provided by TSMC. The simulated phase range of the circuit is about 180° with 22.5° step at 9-11 GHz and the root-mean-square (RMS) phase error is less than 5° at 9-11 GHz. The simulated input P1dB is 12 dBm at 10 GHz and the chip area is 1195 × 1000 mm2 including all testing pads.
RIKHARI, MOHIT. "ENERGY EFFICIENT VOLTAGE LEVEL SHIFTER DESIGN IN NTV REGIME". Thesis, 2023. http://dspace.dtu.ac.in:8080/jspui/handle/repository/20129.
Pełny tekst źródłaHuang, Lin-Yi, i 黃麟懿. "Butler Matrix and Low Loss Reflective-Type Phase Shifter Design". Thesis, 2017. http://ndltd.ncl.edu.tw/handle/03614615263606183960.
Pełny tekst źródła國立交通大學
電子研究所
105
The phased array system is the one of the most important technique in the multi-antenna system. By the function of the phase shifter, we can control the beam directions and the signal will be transmitted and received more efficiently. In the thesis, an 11 GHz 4x4 Butler matrix, a 38 GHz single-pole-four-throw(SP4T) switch and a 38 GHz low loss reflective-type phase shifter (RTPS) are proposed. The 11 GHz 4x4 Butler matrix is designed in Rogers board (RO-4003C). The 4x4 Butler matrix provides four different beam directions. From the measurement results, the insertion loss are 7~10 dB, the return loss are above 10 dB and the error of phase difference are about ±15°. The 38 GHz single-pole-four-throw(SP4T) switch is designed and implemented in TSMC 0.18 m CMOS technology. The switch is used to choose the different output paths. From measurement results, the insertion loss are 6.2 dB, the isolation are 25 dB and the return loss are 6 dB. The 38 GHz low loss reflective type phase shifter is designed and implemented in TSMC 90 nm CMOS technology. The negative resistance is used in reflective load for compensating the loss of phase shifter. From measurement results, the insertion loss are 1.45±0.35 dB, the phase tuning range is 161°, the return loss are above 10 dB, the linearity(Pi,1dB) are -9~-3 dBm and noise figure are 9~12.5 dB under different tuning voltage. The DC power consumption is 9.6 mW from 1.2 V supply.
Peng, Pen-Jui, i 彭朋瑞. "Design of Phase Shifter for Microwave and Millimeter-wave Applications". Thesis, 2010. http://ndltd.ncl.edu.tw/handle/57478622892028928487.
Pełny tekst źródła臺灣大學
電信工程學研究所
98
Three phase shifters in CMOS technology are implemented in this thesis. It can be used in a direct conversion system and phase array system. The first phase shifter is applied in a 60 GHz sub-harmonic mixing direct conversion system. The LO frequency is set to be 30 GHz due to the sub-harmonic architecture. The most important problem in a direct conversion system is the IQ mismatch since the signal quality will be degraded by IQ mismatch. Reducing the IQ mismatch can increase the signal quality substantially. Therefore, a 30 GHz continuously tunable phase shifter using 65 nm CMOS technology is presented in this thesis. This phase shifter is set after the LO, dividing the LO signal into IQ paths and the IQ signals will be inserted to the IQ mixer, respectively. The IQ signals can be generated by a 45° phase shifter due to the sub-harmonic architecture. Using the continuously tunable phase shifter, this phase shifter can provide 45° ± 10° phase difference, and ±2 dB amplitude imbalance. Therefore, the IQ signals will have good match by using the phase shifter. The second and the third phase shifters are applied in a 60 GHz phase array system. Phase array system has been widely used in nowadays communication system since the high spatial selectivity and the high array gain can improve the spectral efficiency. Since the CMOS technology have high integration, the phase array system can be applied in many respects. The second circuit is a switching type phase shifter using 65 nm CMOS technology. Since the losses in different phase state are not the same, it will cause the amplitude error. To minimize the amplitude error of the STPS, a variable gain amplifier (VGA) can be cascaded with the phase shifter to compensate the different loss in each state. However, when VGA provides different gain to compensate the different loss of each state, the insertion phase of the VGA will also be changed. Therefore, it is difficult to achieve low RMS phase error and low RMS gain error simultaneously. In this design, a STPS using a VGA with a new phase compensation technique is presented. The phase compensated VGA can provide variable gain without changing the insertion phase. Using the phase compensated VGA, the gain error of the STPS can be minimized without degrading the phase error. The measured RMS phase error and amplitude error are under 7.2° and 0.2 dB respectively in 60 to 66 GHz. The average amplitude is about -7 dB. The third circuit is a vector sum phase shifter using 90 nm CMOS technology. The vector sum phase shifter can synthesize any amplitude and phase at certain frequency, so the phase error and amplitude error can be minimized. However, the vector sum phase shifter usually suffered from its narrow bandwidth since the IQ signals cannot be precise in wide frequency range. The proposed vector sum phase shifter using a wideband quadrature Wilkinson power divider to achieve low phase error in wideband. The measured RMS phase error and amplitude error are under 5° and 0.5 dB respectively in 57 to 66 GHz. The average amplitude is about -5 dB.
KUMAR, AJAY. "DESIGN OF DIGITAL PHASE SHIFTER WITH VARIOUS ORDERS OF BPF". Thesis, 2011. http://dspace.dtu.ac.in:8080/jspui/handle/repository/13879.
Pełny tekst źródłaThis thesis presents the theory and a design method for distributed digital phase shifters, where both the phase‐error bandwidth and the return‐loss bandwidth are considered simultaneously. The proposed topology of each phase bit consists of a transmission‐line (TL) branch and a bandpass filter (BPF) branch. The BPF branch uses grounded shunt quarter wavelength stubs to achieve phase alignment with the insertion phase of the TL branch. By increasing the number of transmission poles of the BPF branch, the returnloss bandwidth can be increased. Analysis of the BPF topology with one, two, and three transmission poles is provided. The design parameters for 22.5 , 45 , 90 , are provided for bandwidths of 30%, 50%. The three bit digital phase shifter is designed with minimum phase shift of 22.50 and maximum phase provided is 157.50. Results of all three bit phase shifts are produced and their respective phase errors and return losses are compared.
Lata, Poonam. "Design, Development, And Integration Of A Meso-scale Eletrostatic Phase Shifter On Microwave Laminate". Thesis, 2011. https://etd.iisc.ac.in/handle/2005/2356.
Pełny tekst źródłaLata, Poonam. "Design, Development, And Integration Of A Meso-scale Eletrostatic Phase Shifter On Microwave Laminate". Thesis, 2011. http://hdl.handle.net/2005/2356.
Pełny tekst źródłaLo, Chi-Hung, i 駱祈宏. "High speed level shifter design based on high voltage BCD process". Thesis, 2017. http://ndltd.ncl.edu.tw/handle/65120581713177885179.
Pełny tekst źródła國立中央大學
電機工程學系
105
Two novel level-shifter architectures based on cross-coupled latch pairs for high voltage level-shifter applications was proposed and analyzed in this thesis. Since high votlage power transistors were employed as isolated protection devcies inside the level shifters, and the delay caused by Miller effect exists while power transistors switch on and off, two different high voltage level shilfters with resisitive loading and zener diode in series with a resistor, respectively, were designed to increase the transtion speed of the level shifters. In addition, to understand the roles of DPW_NBL isolated ring of the high votlage process while different reverse bias votlage applied with and effects on the performance of the level shifters, the N+ deep burried layer in the low voltage region and the high voltage region, respectively, were applied with the same and different voltage levels, separately, to examine the effects. In order to verify the proposed architectures, three kinds of different high voltage level shifters, including level-shifting from low voltage to high voltage, and high voltage to low voltage, were designed using TSMC 0.25um 60V Bipolar-CMOS-DMOS (BCD) process. The performance matrix (Figure of merit) was built and analyzed. The designed 7 different level-shifter circutis with the capability of shifting a 0 ~ 5V, 5MHz square wave to a 20 ~ 25V square wave occupy total area of 2603um x 611um, and the other 7 circutis with the capability of shifting a 0 ~ 5V, 5MHz square wave to a -20 ~ -25V square wave occupy the area of 2595.7um x 649.4um, respectively.
Wen, Shao-Yen, i 溫紹彥. "A study of the multi-speed shifter design for city bike". Thesis, 2003. http://ndltd.ncl.edu.tw/handle/08833827894163333009.
Pełny tekst źródła長庚大學
工業設計研究所
91
This paper is aimed to study the comfort of the multi-speed shifter design for the city bike. First, investigate the general situation of current products and generalize a property database of product samples. And second, apply the “Category Classification” theory of Kansei Engineering to infer the relation between users’ perceptual requirements to the shifter and design elements of product properties. Finally, according to results from the experiment conducted in this research, twenty product samples were evaluated by twenty subjects, including their looking- aesthetic, looking- comfort and holding- comfort. By results from the experiment, these eight properties were all important to the multi-speed shifter design. The smaller size of the outer-tube was notable uncomfortable no matter in looking or holding situation, and neither was the pellet-prominence of “friction of the surface”. This research has proposed design guidelines to the multi-speed shifter design for city bike, and it should be helpful to the practice design and related studies.
Lyu, Kan-Syue, i 呂侃學. "Design of Phase Shifter and OOK Receivers for K-band Applications". Thesis, 2018. http://ndltd.ncl.edu.tw/handle/7472qe.
Pełny tekst źródłaHsu, Chia-Wei, i 許家瑋. "Design of S-Band Passive and Active Digital Phase Shifter Chips". Thesis, 2019. http://ndltd.ncl.edu.tw/handle/qw93ep.
Pełny tekst źródła國立中央大學
電機工程學系
107
Phased array is commonly used in radar systems for beam steering. In 5th generation mobile communication system that will be deployed soon, phased array also plays an important role. Phase shifter, used for providing tunable phase shift, is one of the essential circuit components in phase arrays. In this thesis, two types of phase shifters, which are passive phase shifter based on magnetically coupled all-pass networks and vector-summing active phase shifter using area-resizing technique, are proposed. The phase shifters are realized in integrated circuit form and operate in S-band. All-pass networks have been used in phase-shifter design. Magnetically coupled all-pass network (MCAPN) with positive coupling coefficient may be used to increase the amount of phase shift. In Chapter 2 of this thesis, a 2.45-GHz 5-bit passive phase shifter is designed based on MCAPN with positive coupling coefficient. The design goal is to achieve 180° phase shift with only one stage of network. The switched capacitors in the phase shifter are implemented using TSMC 0.18-μm CMOS technology. The coupled inductors are realized on a silicon carrier substrate using an integrated passive device (IPD) process. Finally, the phase shifter is completed by assembling the CMOS chip and IPD carrier substrate with flip-chip bonding. Measurement results show that, if the switched capacitors are controlled in the originally intended way, the phase shifter exhibits 179.4° phase shift at 2.45 GHz but the return loss is however not greater than 10 dB for all 32 states. If the controlling bits for individual switched capacitors are properly modified, ending up in 23 sets of states, then at 2 GHz, the return loss is greater than 10 dB and the insertion loss is less than 14.5 dB for these 23 sets of states. The phase shift achieved is 147.8° at 2 GHz. Vector-summing architecture is usually adopted for the design of active phase shifters. In Chapter 3 of this thesis, a 3.5-GHz 6-bit vector-summing active phase shifter is designed in TSMC 0.18-μm CMOS. In addition, area-resizing technique is adopted for the design of the variable gain amplifiers (VGAs) in the vector-summing phase shifter. The advantage of the area-resizing technique is that the phase and amplitude errors may be indefinitely reduced by increasing the number of the controlling bits of the VGAs. Measurement results show that, from 3.3 to 3.8 GHz, the rms phase error is less than 1.15° and the amplitude error is within ±0.45 dB. For all 64 states, the input return loss is greater than 15 dB, the output return loss is greater than 7.9 dB, and the gain is greater than −8.81 dB. Moreover, between 2.46 and 4.68 GHz, the rms phase error is less than 2°. Quadrature generation network is a necessity in vector-summing phase shifter. Common quadrature generation networks include R-C poly-phase filter and quadrature all-pass filter (QAF). In Chapter 4 of this thesis, QAF with magnetic coupling is proposed for reducing the chip area. 1.8–2.2 GHz QAFs are implemented using a GaAs-based IPD process. Measurement results show that, given that the circuit performances are similar, the magnetically coupled QAF (MCQAF) occupies a chip area of 0.101 mm2 whereas conventional QAF occupies 0.154 mm2. This translates into a 34% reduction in chip area. In this work, S-band passive and active digital phase shifter chips are successfully realized and MCQAF is proposed. Among them, the vector-summing phase shifter that adopts area-resizing technique exhibits competitively low phase and amplitude errors. Besides, it is also demonstrated that the proposed MCQAF could considerably save chip area.
Yu, Hao-Chun, i 俞皓鈞. "The Design of Ku-band Phase Shifter and Power Amplifier Integrated Circuits". Thesis, 2010. http://ndltd.ncl.edu.tw/handle/32721297141091848852.
Pełny tekst źródła元智大學
通訊工程學系
99
The design of the Ku-band phase shifter and power amplifier for phase array system applications are presented in this thesis. A 2-bit and a 3-bit phase shifter MMIC using switch-type topology are designed and fabricated on WIN 0.15 μm pHEMT process. The 2-bit switch-type phase shifter MMIC with 90° phase resolution achieves a maximum insertion loss of 6.3 dB at 12 GHz. The RMS phase error of the 2-bit phase shifter is 2.099 degree and the RMS gain error is 0.382 dB. The chip size is 1.5 mm2 including all testing pads. Another 3-bit switch-type phase shifter MMIC with 45° phase resolution achieves a maximum insertion loss of 7.9 dB at 12 GHz. The RMS phase error of the 3-bit phase shifter is 1.62 degree and the RMS gain error is 0.308 dB. The chip size is 1.5 mm2. The simulated and measured results have good agreement for the presented MMICs. A 12 GHz fully-integrated power amplifier is designed and fabricated on TSMC 0.18 μm CMOS technology. The CMOS power amplifier MMIC achieves a small signal gain of 16.9 dB at 12 GHz with chip size 0.81511 × 0.575 mm2. The output power and output 1 dB compression point is 15.27 dBm and 11.26 dBm, respectively. The power added efficiency is 15.3 %.
Wei, Shih-Chiang, i 魏士強. "Design of V-band Substrate Integrated Waveguide Phase Shifter and Mechanical Switch". Thesis, 2016. http://ndltd.ncl.edu.tw/handle/89798602740891697228.
Pełny tekst źródła國立交通大學
電信工程研究所
104
In this thesis, a V-band phase shifters and a V-band mechanical switches are proposed using the substrate integrated waveguide (SIW). The substrate integrated waveguide is manufactured on a Rogers RT-Duroid 5880® low loss substrate with a dielectric constant of 2.2 and a thickness of 10 mil. The single-pole-single-throw (SPST) and single-pole-double-throw (SPDT) switches are proposed with a center frequency of 60 GHz where the so-called cross centered copper ring structure are adopted. The on and off of the switches are mechanically controlled by a piece of conducting material to lift or contact the specified area of the switch. On the other hand, the proposed phase shifter cascades three different phase shifters which include a 90 degree digital phase shifter, a 180 degree digital phase shifter and a 90 degree tunable phase shifter. Finally, the proposed switches and the proposed phase shifter are measured by a network analyzer with the V-band (WR-15) waveguide extenders through the newly developed SIW to rectangular waveguide transition. The advantage of this newly developed transition is no electrical contact with the metal of the rectangular waveguide.
D'Amato, Giulio. "Design of a revised DDS-PLL phase shifter architecture for phased arrays". Doctoral thesis, 2019. http://hdl.handle.net/11589/159909.
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